cbus_drivers_&_functional_image
 
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stm32l4a6xx.h
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1
33#ifndef __STM32L4A6xx_H
34#define __STM32L4A6xx_H
35
36#ifdef __cplusplus
37 extern "C" {
38#endif /* __cplusplus */
39
47#define __CM4_REV 0x0001U
48#define __MPU_PRESENT 1U
49#define __NVIC_PRIO_BITS 4U
50#define __Vendor_SysTickConfig 0U
51#define __FPU_PRESENT 1U
65typedef enum
66{
67/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
68 NonMaskableInt_IRQn = -14,
69 HardFault_IRQn = -13,
70 MemoryManagement_IRQn = -12,
71 BusFault_IRQn = -11,
72 UsageFault_IRQn = -10,
73 SVCall_IRQn = -5,
74 DebugMonitor_IRQn = -4,
75 PendSV_IRQn = -2,
76 SysTick_IRQn = -1,
77/****** STM32 specific Interrupt Numbers **********************************************************************/
78 WWDG_IRQn = 0,
79 PVD_PVM_IRQn = 1,
80 TAMP_STAMP_IRQn = 2,
81 RTC_WKUP_IRQn = 3,
82 FLASH_IRQn = 4,
83 RCC_IRQn = 5,
84 EXTI0_IRQn = 6,
85 EXTI1_IRQn = 7,
86 EXTI2_IRQn = 8,
87 EXTI3_IRQn = 9,
88 EXTI4_IRQn = 10,
89 DMA1_Channel1_IRQn = 11,
90 DMA1_Channel2_IRQn = 12,
91 DMA1_Channel3_IRQn = 13,
92 DMA1_Channel4_IRQn = 14,
93 DMA1_Channel5_IRQn = 15,
94 DMA1_Channel6_IRQn = 16,
95 DMA1_Channel7_IRQn = 17,
96 ADC1_2_IRQn = 18,
97 CAN1_TX_IRQn = 19,
98 CAN1_RX0_IRQn = 20,
99 CAN1_RX1_IRQn = 21,
100 CAN1_SCE_IRQn = 22,
101 EXTI9_5_IRQn = 23,
102 TIM1_BRK_TIM15_IRQn = 24,
103 TIM1_UP_TIM16_IRQn = 25,
104 TIM1_TRG_COM_TIM17_IRQn = 26,
105 TIM1_CC_IRQn = 27,
106 TIM2_IRQn = 28,
107 TIM3_IRQn = 29,
108 TIM4_IRQn = 30,
109 I2C1_EV_IRQn = 31,
110 I2C1_ER_IRQn = 32,
111 I2C2_EV_IRQn = 33,
112 I2C2_ER_IRQn = 34,
113 SPI1_IRQn = 35,
114 SPI2_IRQn = 36,
115 USART1_IRQn = 37,
116 USART2_IRQn = 38,
117 USART3_IRQn = 39,
118 EXTI15_10_IRQn = 40,
119 RTC_Alarm_IRQn = 41,
120 DFSDM1_FLT3_IRQn = 42,
121 TIM8_BRK_IRQn = 43,
122 TIM8_UP_IRQn = 44,
123 TIM8_TRG_COM_IRQn = 45,
124 TIM8_CC_IRQn = 46,
125 ADC3_IRQn = 47,
126 FMC_IRQn = 48,
127 SDMMC1_IRQn = 49,
128 TIM5_IRQn = 50,
129 SPI3_IRQn = 51,
130 UART4_IRQn = 52,
131 UART5_IRQn = 53,
132 TIM6_DAC_IRQn = 54,
133 TIM7_IRQn = 55,
134 DMA2_Channel1_IRQn = 56,
135 DMA2_Channel2_IRQn = 57,
136 DMA2_Channel3_IRQn = 58,
137 DMA2_Channel4_IRQn = 59,
138 DMA2_Channel5_IRQn = 60,
139 DFSDM1_FLT0_IRQn = 61,
140 DFSDM1_FLT1_IRQn = 62,
141 DFSDM1_FLT2_IRQn = 63,
142 COMP_IRQn = 64,
143 LPTIM1_IRQn = 65,
144 LPTIM2_IRQn = 66,
145 OTG_FS_IRQn = 67,
146 DMA2_Channel6_IRQn = 68,
147 DMA2_Channel7_IRQn = 69,
148 LPUART1_IRQn = 70,
149 QUADSPI_IRQn = 71,
150 I2C3_EV_IRQn = 72,
151 I2C3_ER_IRQn = 73,
152 SAI1_IRQn = 74,
153 SAI2_IRQn = 75,
154 SWPMI1_IRQn = 76,
155 TSC_IRQn = 77,
156 LCD_IRQn = 78,
157 AES_IRQn = 79,
158 HASH_RNG_IRQn = 80,
159 FPU_IRQn = 81,
160 CRS_IRQn = 82,
161 I2C4_EV_IRQn = 83,
162 I2C4_ER_IRQn = 84,
163 DCMI_IRQn = 85,
164 CAN2_TX_IRQn = 86,
165 CAN2_RX0_IRQn = 87,
166 CAN2_RX1_IRQn = 88,
167 CAN2_SCE_IRQn = 89,
168 DMA2D_IRQn = 90
169} IRQn_Type;
170
175#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
176#include "system_stm32l4xx.h"
177#include <stdint.h>
178
187typedef struct
188{
189 __IO uint32_t ISR;
190 __IO uint32_t IER;
191 __IO uint32_t CR;
192 __IO uint32_t CFGR;
193 __IO uint32_t CFGR2;
194 __IO uint32_t SMPR1;
195 __IO uint32_t SMPR2;
196 uint32_t RESERVED1;
197 __IO uint32_t TR1;
198 __IO uint32_t TR2;
199 __IO uint32_t TR3;
200 uint32_t RESERVED2;
201 __IO uint32_t SQR1;
202 __IO uint32_t SQR2;
203 __IO uint32_t SQR3;
204 __IO uint32_t SQR4;
205 __IO uint32_t DR;
206 uint32_t RESERVED3;
207 uint32_t RESERVED4;
208 __IO uint32_t JSQR;
209 uint32_t RESERVED5[4];
210 __IO uint32_t OFR1;
211 __IO uint32_t OFR2;
212 __IO uint32_t OFR3;
213 __IO uint32_t OFR4;
214 uint32_t RESERVED6[4];
215 __IO uint32_t JDR1;
216 __IO uint32_t JDR2;
217 __IO uint32_t JDR3;
218 __IO uint32_t JDR4;
219 uint32_t RESERVED7[4];
220 __IO uint32_t AWD2CR;
221 __IO uint32_t AWD3CR;
222 uint32_t RESERVED8;
223 uint32_t RESERVED9;
224 __IO uint32_t DIFSEL;
225 __IO uint32_t CALFACT;
227} ADC_TypeDef;
228
229typedef struct
230{
231 __IO uint32_t CSR;
232 uint32_t RESERVED;
233 __IO uint32_t CCR;
234 __IO uint32_t CDR;
235} ADC_Common_TypeDef;
236
241typedef struct
242{
243 __IO uint32_t CR;
244 __IO uint32_t SR;
245 __IO uint32_t RISR;
246 __IO uint32_t IER;
247 __IO uint32_t MISR;
248 __IO uint32_t ICR;
249 __IO uint32_t ESCR;
250 __IO uint32_t ESUR;
251 __IO uint32_t CWSTRTR;
252 __IO uint32_t CWSIZER;
253 __IO uint32_t DR;
254} DCMI_TypeDef;
255
260typedef struct
261{
262 __IO uint32_t TIR;
263 __IO uint32_t TDTR;
264 __IO uint32_t TDLR;
265 __IO uint32_t TDHR;
266} CAN_TxMailBox_TypeDef;
267
272typedef struct
273{
274 __IO uint32_t RIR;
275 __IO uint32_t RDTR;
276 __IO uint32_t RDLR;
277 __IO uint32_t RDHR;
278} CAN_FIFOMailBox_TypeDef;
279
284typedef struct
285{
286 __IO uint32_t FR1;
287 __IO uint32_t FR2;
288} CAN_FilterRegister_TypeDef;
289
294typedef struct
295{
296 __IO uint32_t MCR;
297 __IO uint32_t MSR;
298 __IO uint32_t TSR;
299 __IO uint32_t RF0R;
300 __IO uint32_t RF1R;
301 __IO uint32_t IER;
302 __IO uint32_t ESR;
303 __IO uint32_t BTR;
304 uint32_t RESERVED0[88];
305 CAN_TxMailBox_TypeDef sTxMailBox[3];
306 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
307 uint32_t RESERVED1[12];
308 __IO uint32_t FMR;
309 __IO uint32_t FM1R;
310 uint32_t RESERVED2;
311 __IO uint32_t FS1R;
312 uint32_t RESERVED3;
313 __IO uint32_t FFA1R;
314 uint32_t RESERVED4;
315 __IO uint32_t FA1R;
316 uint32_t RESERVED5[8];
317 CAN_FilterRegister_TypeDef sFilterRegister[28];
318} CAN_TypeDef;
319
320
325typedef struct
326{
327 __IO uint32_t CSR;
328} COMP_TypeDef;
329
330typedef struct
331{
332 __IO uint32_t CSR;
333} COMP_Common_TypeDef;
334
339typedef struct
340{
341 __IO uint32_t DR;
342 __IO uint8_t IDR;
343 uint8_t RESERVED0;
344 uint16_t RESERVED1;
345 __IO uint32_t CR;
346 uint32_t RESERVED2;
347 __IO uint32_t INIT;
348 __IO uint32_t POL;
349} CRC_TypeDef;
350
354typedef struct
355{
356__IO uint32_t CR;
357__IO uint32_t CFGR;
358__IO uint32_t ISR;
359__IO uint32_t ICR;
360} CRS_TypeDef;
361
366typedef struct
367{
368 __IO uint32_t CR;
369 __IO uint32_t SWTRIGR;
370 __IO uint32_t DHR12R1;
371 __IO uint32_t DHR12L1;
372 __IO uint32_t DHR8R1;
373 __IO uint32_t DHR12R2;
374 __IO uint32_t DHR12L2;
375 __IO uint32_t DHR8R2;
376 __IO uint32_t DHR12RD;
377 __IO uint32_t DHR12LD;
378 __IO uint32_t DHR8RD;
379 __IO uint32_t DOR1;
380 __IO uint32_t DOR2;
381 __IO uint32_t SR;
382 __IO uint32_t CCR;
383 __IO uint32_t MCR;
384 __IO uint32_t SHSR1;
385 __IO uint32_t SHSR2;
386 __IO uint32_t SHHR;
387 __IO uint32_t SHRR;
388} DAC_TypeDef;
389
393typedef struct
394{
395 __IO uint32_t FLTCR1;
396 __IO uint32_t FLTCR2;
397 __IO uint32_t FLTISR;
398 __IO uint32_t FLTICR;
399 __IO uint32_t FLTJCHGR;
400 __IO uint32_t FLTFCR;
401 __IO uint32_t FLTJDATAR;
402 __IO uint32_t FLTRDATAR;
403 __IO uint32_t FLTAWHTR;
404 __IO uint32_t FLTAWLTR;
405 __IO uint32_t FLTAWSR;
406 __IO uint32_t FLTAWCFR;
407 __IO uint32_t FLTEXMAX;
408 __IO uint32_t FLTEXMIN;
409 __IO uint32_t FLTCNVTIMR;
410} DFSDM_Filter_TypeDef;
411
415typedef struct
416{
417 __IO uint32_t CHCFGR1;
418 __IO uint32_t CHCFGR2;
419 __IO uint32_t CHAWSCDR;
421 __IO uint32_t CHWDATAR;
422 __IO uint32_t CHDATINR;
423} DFSDM_Channel_TypeDef;
424
429typedef struct
430{
431 __IO uint32_t IDCODE;
432 __IO uint32_t CR;
433 __IO uint32_t APB1FZR1;
434 __IO uint32_t APB1FZR2;
435 __IO uint32_t APB2FZ;
436} DBGMCU_TypeDef;
437
438
443typedef struct
444{
445 __IO uint32_t CCR;
446 __IO uint32_t CNDTR;
447 __IO uint32_t CPAR;
448 __IO uint32_t CMAR;
449} DMA_Channel_TypeDef;
450
451typedef struct
452{
453 __IO uint32_t ISR;
454 __IO uint32_t IFCR;
455} DMA_TypeDef;
456
457typedef struct
458{
459 __IO uint32_t CSELR;
460} DMA_Request_TypeDef;
461
462/* Legacy define */
463#define DMA_request_TypeDef DMA_Request_TypeDef
464
465
470typedef struct
471{
472 __IO uint32_t CR;
473 __IO uint32_t ISR;
474 __IO uint32_t IFCR;
475 __IO uint32_t FGMAR;
476 __IO uint32_t FGOR;
477 __IO uint32_t BGMAR;
478 __IO uint32_t BGOR;
479 __IO uint32_t FGPFCCR;
480 __IO uint32_t FGCOLR;
481 __IO uint32_t BGPFCCR;
482 __IO uint32_t BGCOLR;
483 __IO uint32_t FGCMAR;
484 __IO uint32_t BGCMAR;
485 __IO uint32_t OPFCCR;
486 __IO uint32_t OCOLR;
487 __IO uint32_t OMAR;
488 __IO uint32_t OOR;
489 __IO uint32_t NLR;
490 __IO uint32_t LWR;
491 __IO uint32_t AMTCR;
492 uint32_t RESERVED[236];
493 __IO uint32_t FGCLUT[256];
494 __IO uint32_t BGCLUT[256];
495} DMA2D_TypeDef;
496
501typedef struct
502{
503 __IO uint32_t IMR1;
504 __IO uint32_t EMR1;
505 __IO uint32_t RTSR1;
506 __IO uint32_t FTSR1;
507 __IO uint32_t SWIER1;
508 __IO uint32_t PR1;
509 uint32_t RESERVED1;
510 uint32_t RESERVED2;
511 __IO uint32_t IMR2;
512 __IO uint32_t EMR2;
513 __IO uint32_t RTSR2;
514 __IO uint32_t FTSR2;
515 __IO uint32_t SWIER2;
516 __IO uint32_t PR2;
517} EXTI_TypeDef;
518
519
524typedef struct
525{
526 __IO uint32_t CSSA;
527 __IO uint32_t CSL;
528 __IO uint32_t NVDSSA;
529 __IO uint32_t NVDSL;
530 __IO uint32_t VDSSA ;
531 __IO uint32_t VDSL ;
532 uint32_t RESERVED1;
533 uint32_t RESERVED2;
534 __IO uint32_t CR ;
535} FIREWALL_TypeDef;
536
537
542typedef struct
543{
544 __IO uint32_t ACR;
545 __IO uint32_t PDKEYR;
546 __IO uint32_t KEYR;
547 __IO uint32_t OPTKEYR;
548 __IO uint32_t SR;
549 __IO uint32_t CR;
550 __IO uint32_t ECCR;
551 __IO uint32_t RESERVED1;
552 __IO uint32_t OPTR;
553 __IO uint32_t PCROP1SR;
554 __IO uint32_t PCROP1ER;
555 __IO uint32_t WRP1AR;
556 __IO uint32_t WRP1BR;
557 uint32_t RESERVED2[4];
558 __IO uint32_t PCROP2SR;
559 __IO uint32_t PCROP2ER;
560 __IO uint32_t WRP2AR;
561 __IO uint32_t WRP2BR;
562} FLASH_TypeDef;
563
564
569typedef struct
570{
571 __IO uint32_t BTCR[8];
572} FMC_Bank1_TypeDef;
573
578typedef struct
579{
580 __IO uint32_t BWTR[7];
581} FMC_Bank1E_TypeDef;
582
587typedef struct
588{
589 __IO uint32_t PCR;
590 __IO uint32_t SR;
591 __IO uint32_t PMEM;
592 __IO uint32_t PATT;
593 uint32_t RESERVED0;
594 __IO uint32_t ECCR;
595} FMC_Bank3_TypeDef;
596
601typedef struct
602{
603 __IO uint32_t MODER;
604 __IO uint32_t OTYPER;
605 __IO uint32_t OSPEEDR;
606 __IO uint32_t PUPDR;
607 __IO uint32_t IDR;
608 __IO uint32_t ODR;
609 __IO uint32_t BSRR;
610 __IO uint32_t LCKR;
611 __IO uint32_t AFR[2];
612 __IO uint32_t BRR;
614} GPIO_TypeDef;
615
616
621typedef struct
622{
623 __IO uint32_t CR1;
624 __IO uint32_t CR2;
625 __IO uint32_t OAR1;
626 __IO uint32_t OAR2;
627 __IO uint32_t TIMINGR;
628 __IO uint32_t TIMEOUTR;
629 __IO uint32_t ISR;
630 __IO uint32_t ICR;
631 __IO uint32_t PECR;
632 __IO uint32_t RXDR;
633 __IO uint32_t TXDR;
634} I2C_TypeDef;
635
640typedef struct
641{
642 __IO uint32_t KR;
643 __IO uint32_t PR;
644 __IO uint32_t RLR;
645 __IO uint32_t SR;
646 __IO uint32_t WINR;
647} IWDG_TypeDef;
648
653typedef struct
654{
655 __IO uint32_t CR;
656 __IO uint32_t FCR;
657 __IO uint32_t SR;
658 __IO uint32_t CLR;
659 uint32_t RESERVED;
660 __IO uint32_t RAM[16];
661} LCD_TypeDef;
662
666typedef struct
667{
668 __IO uint32_t ISR;
669 __IO uint32_t ICR;
670 __IO uint32_t IER;
671 __IO uint32_t CFGR;
672 __IO uint32_t CR;
673 __IO uint32_t CMP;
674 __IO uint32_t ARR;
675 __IO uint32_t CNT;
676 __IO uint32_t OR;
677} LPTIM_TypeDef;
678
683typedef struct
684{
685 __IO uint32_t CSR;
686 __IO uint32_t OTR;
687 __IO uint32_t LPOTR;
688} OPAMP_TypeDef;
689
690typedef struct
691{
692 __IO uint32_t CSR;
693} OPAMP_Common_TypeDef;
694
699typedef struct
700{
701 __IO uint32_t CR1;
702 __IO uint32_t CR2;
703 __IO uint32_t CR3;
704 __IO uint32_t CR4;
705 __IO uint32_t SR1;
706 __IO uint32_t SR2;
707 __IO uint32_t SCR;
708 uint32_t RESERVED;
709 __IO uint32_t PUCRA;
710 __IO uint32_t PDCRA;
711 __IO uint32_t PUCRB;
712 __IO uint32_t PDCRB;
713 __IO uint32_t PUCRC;
714 __IO uint32_t PDCRC;
715 __IO uint32_t PUCRD;
716 __IO uint32_t PDCRD;
717 __IO uint32_t PUCRE;
718 __IO uint32_t PDCRE;
719 __IO uint32_t PUCRF;
720 __IO uint32_t PDCRF;
721 __IO uint32_t PUCRG;
722 __IO uint32_t PDCRG;
723 __IO uint32_t PUCRH;
724 __IO uint32_t PDCRH;
725 __IO uint32_t PUCRI;
726 __IO uint32_t PDCRI;
727} PWR_TypeDef;
728
729
734typedef struct
735{
736 __IO uint32_t CR;
737 __IO uint32_t DCR;
738 __IO uint32_t SR;
739 __IO uint32_t FCR;
740 __IO uint32_t DLR;
741 __IO uint32_t CCR;
742 __IO uint32_t AR;
743 __IO uint32_t ABR;
744 __IO uint32_t DR;
745 __IO uint32_t PSMKR;
746 __IO uint32_t PSMAR;
747 __IO uint32_t PIR;
748 __IO uint32_t LPTR;
749} QUADSPI_TypeDef;
750
751
756typedef struct
757{
758 __IO uint32_t CR;
759 __IO uint32_t ICSCR;
760 __IO uint32_t CFGR;
761 __IO uint32_t PLLCFGR;
762 __IO uint32_t PLLSAI1CFGR;
763 __IO uint32_t PLLSAI2CFGR;
764 __IO uint32_t CIER;
765 __IO uint32_t CIFR;
766 __IO uint32_t CICR;
767 uint32_t RESERVED0;
768 __IO uint32_t AHB1RSTR;
769 __IO uint32_t AHB2RSTR;
770 __IO uint32_t AHB3RSTR;
771 uint32_t RESERVED1;
772 __IO uint32_t APB1RSTR1;
773 __IO uint32_t APB1RSTR2;
774 __IO uint32_t APB2RSTR;
775 uint32_t RESERVED2;
776 __IO uint32_t AHB1ENR;
777 __IO uint32_t AHB2ENR;
778 __IO uint32_t AHB3ENR;
779 uint32_t RESERVED3;
780 __IO uint32_t APB1ENR1;
781 __IO uint32_t APB1ENR2;
782 __IO uint32_t APB2ENR;
783 uint32_t RESERVED4;
784 __IO uint32_t AHB1SMENR;
785 __IO uint32_t AHB2SMENR;
786 __IO uint32_t AHB3SMENR;
787 uint32_t RESERVED5;
788 __IO uint32_t APB1SMENR1;
789 __IO uint32_t APB1SMENR2;
790 __IO uint32_t APB2SMENR;
791 uint32_t RESERVED6;
792 __IO uint32_t CCIPR;
793 uint32_t RESERVED7;
794 __IO uint32_t BDCR;
795 __IO uint32_t CSR;
796 __IO uint32_t CRRCR;
797 __IO uint32_t CCIPR2;
798} RCC_TypeDef;
799
804typedef struct
805{
806 __IO uint32_t TR;
807 __IO uint32_t DR;
808 __IO uint32_t CR;
809 __IO uint32_t ISR;
810 __IO uint32_t PRER;
811 __IO uint32_t WUTR;
812 uint32_t reserved;
813 __IO uint32_t ALRMAR;
814 __IO uint32_t ALRMBR;
815 __IO uint32_t WPR;
816 __IO uint32_t SSR;
817 __IO uint32_t SHIFTR;
818 __IO uint32_t TSTR;
819 __IO uint32_t TSDR;
820 __IO uint32_t TSSSR;
821 __IO uint32_t CALR;
822 __IO uint32_t TAMPCR;
823 __IO uint32_t ALRMASSR;
824 __IO uint32_t ALRMBSSR;
825 __IO uint32_t OR;
826 __IO uint32_t BKP0R;
827 __IO uint32_t BKP1R;
828 __IO uint32_t BKP2R;
829 __IO uint32_t BKP3R;
830 __IO uint32_t BKP4R;
831 __IO uint32_t BKP5R;
832 __IO uint32_t BKP6R;
833 __IO uint32_t BKP7R;
834 __IO uint32_t BKP8R;
835 __IO uint32_t BKP9R;
836 __IO uint32_t BKP10R;
837 __IO uint32_t BKP11R;
838 __IO uint32_t BKP12R;
839 __IO uint32_t BKP13R;
840 __IO uint32_t BKP14R;
841 __IO uint32_t BKP15R;
842 __IO uint32_t BKP16R;
843 __IO uint32_t BKP17R;
844 __IO uint32_t BKP18R;
845 __IO uint32_t BKP19R;
846 __IO uint32_t BKP20R;
847 __IO uint32_t BKP21R;
848 __IO uint32_t BKP22R;
849 __IO uint32_t BKP23R;
850 __IO uint32_t BKP24R;
851 __IO uint32_t BKP25R;
852 __IO uint32_t BKP26R;
853 __IO uint32_t BKP27R;
854 __IO uint32_t BKP28R;
855 __IO uint32_t BKP29R;
856 __IO uint32_t BKP30R;
857 __IO uint32_t BKP31R;
858} RTC_TypeDef;
859
864typedef struct
865{
866 __IO uint32_t GCR;
867} SAI_TypeDef;
868
869typedef struct
870{
871 __IO uint32_t CR1;
872 __IO uint32_t CR2;
873 __IO uint32_t FRCR;
874 __IO uint32_t SLOTR;
875 __IO uint32_t IMR;
876 __IO uint32_t SR;
877 __IO uint32_t CLRFR;
878 __IO uint32_t DR;
879} SAI_Block_TypeDef;
880
881
886typedef struct
887{
888 __IO uint32_t POWER;
889 __IO uint32_t CLKCR;
890 __IO uint32_t ARG;
891 __IO uint32_t CMD;
892 __I uint32_t RESPCMD;
893 __I uint32_t RESP1;
894 __I uint32_t RESP2;
895 __I uint32_t RESP3;
896 __I uint32_t RESP4;
897 __IO uint32_t DTIMER;
898 __IO uint32_t DLEN;
899 __IO uint32_t DCTRL;
900 __I uint32_t DCOUNT;
901 __I uint32_t STA;
902 __IO uint32_t ICR;
903 __IO uint32_t MASK;
904 uint32_t RESERVED0[2];
905 __I uint32_t FIFOCNT;
906 uint32_t RESERVED1[13];
907 __IO uint32_t FIFO;
908} SDMMC_TypeDef;
909
910
915typedef struct
916{
917 __IO uint32_t CR1;
918 __IO uint32_t CR2;
919 __IO uint32_t SR;
920 __IO uint32_t DR;
921 __IO uint32_t CRCPR;
922 __IO uint32_t RXCRCR;
923 __IO uint32_t TXCRCR;
924} SPI_TypeDef;
925
926
931typedef struct
932{
933 __IO uint32_t CR;
934 __IO uint32_t BRR;
935 uint32_t RESERVED1;
936 __IO uint32_t ISR;
937 __IO uint32_t ICR;
938 __IO uint32_t IER;
939 __IO uint32_t RFL;
940 __IO uint32_t TDR;
941 __IO uint32_t RDR;
942 __IO uint32_t OR;
943} SWPMI_TypeDef;
944
945
950typedef struct
951{
952 __IO uint32_t MEMRMP;
953 __IO uint32_t CFGR1;
954 __IO uint32_t EXTICR[4];
955 __IO uint32_t SCSR;
956 __IO uint32_t CFGR2;
957 __IO uint32_t SWPR;
958 __IO uint32_t SKR;
959 __IO uint32_t SWPR2;
960} SYSCFG_TypeDef;
961
962
967typedef struct
968{
969 __IO uint32_t CR1;
970 __IO uint32_t CR2;
971 __IO uint32_t SMCR;
972 __IO uint32_t DIER;
973 __IO uint32_t SR;
974 __IO uint32_t EGR;
975 __IO uint32_t CCMR1;
976 __IO uint32_t CCMR2;
977 __IO uint32_t CCER;
978 __IO uint32_t CNT;
979 __IO uint32_t PSC;
980 __IO uint32_t ARR;
981 __IO uint32_t RCR;
982 __IO uint32_t CCR1;
983 __IO uint32_t CCR2;
984 __IO uint32_t CCR3;
985 __IO uint32_t CCR4;
986 __IO uint32_t BDTR;
987 __IO uint32_t DCR;
988 __IO uint32_t DMAR;
989 __IO uint32_t OR1;
990 __IO uint32_t CCMR3;
991 __IO uint32_t CCR5;
992 __IO uint32_t CCR6;
993 __IO uint32_t OR2;
994 __IO uint32_t OR3;
995} TIM_TypeDef;
996
997
1002typedef struct
1003{
1004 __IO uint32_t CR;
1005 __IO uint32_t IER;
1006 __IO uint32_t ICR;
1007 __IO uint32_t ISR;
1008 __IO uint32_t IOHCR;
1009 uint32_t RESERVED1;
1010 __IO uint32_t IOASCR;
1011 uint32_t RESERVED2;
1012 __IO uint32_t IOSCR;
1013 uint32_t RESERVED3;
1014 __IO uint32_t IOCCR;
1015 uint32_t RESERVED4;
1016 __IO uint32_t IOGCSR;
1017 __IO uint32_t IOGXCR[8];
1018} TSC_TypeDef;
1019
1024typedef struct
1025{
1026 __IO uint32_t CR1;
1027 __IO uint32_t CR2;
1028 __IO uint32_t CR3;
1029 __IO uint32_t BRR;
1030 __IO uint16_t GTPR;
1031 uint16_t RESERVED2;
1032 __IO uint32_t RTOR;
1033 __IO uint16_t RQR;
1034 uint16_t RESERVED3;
1035 __IO uint32_t ISR;
1036 __IO uint32_t ICR;
1037 __IO uint16_t RDR;
1038 uint16_t RESERVED4;
1039 __IO uint16_t TDR;
1040 uint16_t RESERVED5;
1041} USART_TypeDef;
1042
1047typedef struct
1048{
1049 __IO uint32_t CSR;
1050 __IO uint32_t CCR;
1051} VREFBUF_TypeDef;
1052
1057typedef struct
1058{
1059 __IO uint32_t CR;
1060 __IO uint32_t CFR;
1061 __IO uint32_t SR;
1062} WWDG_TypeDef;
1063
1068typedef struct
1069{
1070 __IO uint32_t CR;
1071 __IO uint32_t SR;
1072 __IO uint32_t DINR;
1073 __IO uint32_t DOUTR;
1074 __IO uint32_t KEYR0;
1075 __IO uint32_t KEYR1;
1076 __IO uint32_t KEYR2;
1077 __IO uint32_t KEYR3;
1078 __IO uint32_t IVR0;
1079 __IO uint32_t IVR1;
1080 __IO uint32_t IVR2;
1081 __IO uint32_t IVR3;
1082 __IO uint32_t KEYR4;
1083 __IO uint32_t KEYR5;
1084 __IO uint32_t KEYR6;
1085 __IO uint32_t KEYR7;
1086 __IO uint32_t SUSP0R;
1087 __IO uint32_t SUSP1R;
1088 __IO uint32_t SUSP2R;
1089 __IO uint32_t SUSP3R;
1090 __IO uint32_t SUSP4R;
1091 __IO uint32_t SUSP5R;
1092 __IO uint32_t SUSP6R;
1093 __IO uint32_t SUSP7R;
1094} AES_TypeDef;
1095
1100typedef struct
1101{
1102 __IO uint32_t CR;
1103 __IO uint32_t DIN;
1104 __IO uint32_t STR;
1105 __IO uint32_t HR[5];
1106 __IO uint32_t IMR;
1107 __IO uint32_t SR;
1108 uint32_t RESERVED[52];
1109 __IO uint32_t CSR[54];
1110} HASH_TypeDef;
1111
1116typedef struct
1117{
1118 __IO uint32_t HR[8];
1119} HASH_DIGEST_TypeDef;
1120
1125typedef struct
1126{
1127 __IO uint32_t CR;
1128 __IO uint32_t SR;
1129 __IO uint32_t DR;
1130} RNG_TypeDef;
1131
1135typedef struct
1136{
1137 __IO uint32_t GOTGCTL;
1138 __IO uint32_t GOTGINT;
1139 __IO uint32_t GAHBCFG;
1140 __IO uint32_t GUSBCFG;
1141 __IO uint32_t GRSTCTL;
1142 __IO uint32_t GINTSTS;
1143 __IO uint32_t GINTMSK;
1144 __IO uint32_t GRXSTSR;
1145 __IO uint32_t GRXSTSP;
1146 __IO uint32_t GRXFSIZ;
1147 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1148 __IO uint32_t HNPTXSTS;
1149 uint32_t Reserved30[2];
1150 __IO uint32_t GCCFG;
1151 __IO uint32_t CID;
1152 __IO uint32_t GSNPSID;
1153 __IO uint32_t GHWCFG1;
1154 __IO uint32_t GHWCFG2;
1155 __IO uint32_t GHWCFG3;
1156 uint32_t Reserved6;
1157 __IO uint32_t GLPMCFG;
1158 __IO uint32_t GPWRDN;
1159 __IO uint32_t GDFIFOCFG;
1160 __IO uint32_t GADPCTL;
1161 uint32_t Reserved43[39];
1162 __IO uint32_t HPTXFSIZ;
1163 __IO uint32_t DIEPTXF[0x0F];
1164} USB_OTG_GlobalTypeDef;
1165
1169typedef struct
1170{
1171 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
1172 __IO uint32_t DCTL; /* dev Control Register 804h*/
1173 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
1174 uint32_t Reserved0C; /* Reserved 80Ch*/
1175 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
1176 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
1177 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
1178 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
1179 uint32_t Reserved20; /* Reserved 820h*/
1180 uint32_t Reserved24; /* Reserved 824h*/
1181 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
1182 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
1183 __IO uint32_t DTHRCTL; /* dev thr 830h*/
1184 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
1185 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
1186 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
1187 uint32_t Reserved40; /* Reserved 840h*/
1188 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
1189 uint32_t Reserved44[15]; /* Reserved 848-880h*/
1190 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
1191} USB_OTG_DeviceTypeDef;
1192
1196typedef struct
1197{
1198 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
1199 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
1200 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
1201 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
1202 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
1203 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
1204 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
1205 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
1206} USB_OTG_INEndpointTypeDef;
1207
1211typedef struct
1212{
1213 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
1214 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
1215 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
1216 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
1217 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
1218 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
1219 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
1220} USB_OTG_OUTEndpointTypeDef;
1221
1225typedef struct
1226{
1227 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
1228 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
1229 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
1230 uint32_t Reserved40C; /* Reserved 40Ch*/
1231 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
1232 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
1233 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
1234} USB_OTG_HostTypeDef;
1235
1239typedef struct
1240{
1241 __IO uint32_t HCCHAR;
1242 __IO uint32_t HCSPLT;
1243 __IO uint32_t HCINT;
1244 __IO uint32_t HCINTMSK;
1245 __IO uint32_t HCTSIZ;
1246 __IO uint32_t HCDMA;
1247 uint32_t Reserved[2];
1248} USB_OTG_HostChannelTypeDef;
1249
1257#define FLASH_BASE (0x08000000UL)
1258#define FLASH_END (0x080FFFFFUL)
1259#define FLASH_BANK1_END (0x0807FFFFUL)
1260#define FLASH_BANK2_END (0x080FFFFFUL)
1261#define SRAM1_BASE (0x20000000UL)
1262#define SRAM2_BASE (0x10000000UL)
1263#define PERIPH_BASE (0x40000000UL)
1264#define FMC_BASE (0x60000000UL)
1265#define QSPI_BASE (0x90000000UL)
1267#define FMC_R_BASE (0xA0000000UL)
1268#define QSPI_R_BASE (0xA0001000UL)
1269#define SRAM1_BB_BASE (0x22000000UL)
1270#define PERIPH_BB_BASE (0x42000000UL)
1272/* Legacy defines */
1273#define SRAM_BASE SRAM1_BASE
1274#define SRAM_BB_BASE SRAM1_BB_BASE
1275
1276#define SRAM1_SIZE_MAX (0x00040000UL)
1277#define SRAM2_SIZE (0x00010000UL)
1279#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
1280
1281#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU))== 0x0000FFFFU)) ? (0x400U << 10U) : \
1282 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
1283
1285#define APB1PERIPH_BASE PERIPH_BASE
1286#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1287#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1288#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
1289
1290#define FMC_BANK1 FMC_BASE
1291#define FMC_BANK1_1 FMC_BANK1
1292#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)
1293#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)
1294#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)
1295#define FMC_BANK3 (FMC_BASE + 0x20000000UL)
1296
1298#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
1299#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
1300#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
1301#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
1302#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
1303#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
1304#define LCD_BASE (APB1PERIPH_BASE + 0x2400UL)
1305#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
1306#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
1307#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
1308#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
1309#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
1310#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
1311#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
1312#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
1313#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
1314#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
1315#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
1316#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
1317#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL)
1318#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
1319#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
1320#define I2C4_BASE (APB1PERIPH_BASE + 0x8400UL)
1321#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
1322#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
1323#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL)
1324#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL)
1325#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL)
1326#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810UL)
1327#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
1328#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
1329#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL)
1330#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL)
1331
1332
1334#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
1335#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
1336#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
1337#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
1338#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
1339#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL)
1340#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL)
1341#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
1342#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
1343#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
1344#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
1345#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
1346#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
1347#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
1348#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
1349#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
1350#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
1351#define SAI2_BASE (APB2PERIPH_BASE + 0x5800UL)
1352#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL)
1353#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL)
1354#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL)
1355#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x0000UL)
1356#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x0020UL)
1357#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x0040UL)
1358#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x0060UL)
1359#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x0080UL)
1360#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0x00A0UL)
1361#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0x00C0UL)
1362#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0x00E0UL)
1363#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x0100UL)
1364#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x0180UL)
1365#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x0200UL)
1366#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x0280UL)
1367
1369#define DMA1_BASE (AHB1PERIPH_BASE)
1370#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
1371#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
1372#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
1373#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1374#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL)
1375#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL)
1376
1377
1378#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
1379#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
1380#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
1381#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
1382#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
1383#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
1384#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
1385#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL)
1386
1387
1388#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
1389#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
1390#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
1391#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
1392#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
1393#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
1394#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
1395#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL)
1396
1397
1399#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
1400#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
1401#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
1402#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
1403#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
1404#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
1405#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)
1406#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL)
1407#define GPIOI_BASE (AHB2PERIPH_BASE + 0x2000UL)
1408
1409#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000UL)
1410
1411#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL)
1412#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100UL)
1413#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200UL)
1414#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL)
1415
1416#define DCMI_BASE (AHB2PERIPH_BASE + 0x08050000UL)
1417
1418#define AES_BASE (AHB2PERIPH_BASE + 0x08060000UL)
1419#define HASH_BASE (AHB2PERIPH_BASE + 0x08060400UL)
1420#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x08060710UL)
1421#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
1422
1423
1425#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
1426#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
1427#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
1428
1429/* Debug MCU registers base address */
1430#define DBGMCU_BASE (0xE0042000UL)
1431
1433#define USB_OTG_FS_PERIPH_BASE (0x50000000UL)
1434
1435#define USB_OTG_GLOBAL_BASE (0x00000000UL)
1436#define USB_OTG_DEVICE_BASE (0x00000800UL)
1437#define USB_OTG_IN_ENDPOINT_BASE (0x00000900UL)
1438#define USB_OTG_OUT_ENDPOINT_BASE (0x00000B00UL)
1439#define USB_OTG_EP_REG_SIZE (0x00000020UL)
1440#define USB_OTG_HOST_BASE (0x00000400UL)
1441#define USB_OTG_HOST_PORT_BASE (0x00000440UL)
1442#define USB_OTG_HOST_CHANNEL_BASE (0x00000500UL)
1443#define USB_OTG_HOST_CHANNEL_SIZE (0x00000020UL)
1444#define USB_OTG_PCGCCTL_BASE (0x00000E00UL)
1445#define USB_OTG_FIFO_BASE (0x00001000UL)
1446#define USB_OTG_FIFO_SIZE (0x00001000UL)
1447
1448
1449#define PACKAGE_BASE (0x1FFF7500UL)
1450#define UID_BASE (0x1FFF7590UL)
1451#define FLASHSIZE_BASE (0x1FFF75E0UL)
1459#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1460#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1461#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1462#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1463#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1464#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1465#define LCD ((LCD_TypeDef *) LCD_BASE)
1466#define RTC ((RTC_TypeDef *) RTC_BASE)
1467#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1468#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1469#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1470#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1471#define USART2 ((USART_TypeDef *) USART2_BASE)
1472#define USART3 ((USART_TypeDef *) USART3_BASE)
1473#define UART4 ((USART_TypeDef *) UART4_BASE)
1474#define UART5 ((USART_TypeDef *) UART5_BASE)
1475#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1476#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1477#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1478#define CRS ((CRS_TypeDef *) CRS_BASE)
1479#define CAN ((CAN_TypeDef *) CAN1_BASE)
1480#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1481#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1482#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1483#define PWR ((PWR_TypeDef *) PWR_BASE)
1484#define DAC ((DAC_TypeDef *) DAC1_BASE)
1485#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
1486#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
1487#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
1488#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
1489#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
1490#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1491#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
1492#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
1493#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
1494
1495#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1496#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
1497#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
1498#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
1499#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
1500#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1501#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
1502#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1503#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1504#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1505#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1506#define USART1 ((USART_TypeDef *) USART1_BASE)
1507#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1508#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1509#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
1510#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1511#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1512#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1513#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1514#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1515#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1516#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1517#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1518#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1519#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1520#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
1521#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
1522#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
1523#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
1524#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1525#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1526#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
1527#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
1528/* Aliases to keep compatibility after DFSDM renaming */
1529#define DFSDM_Channel0 DFSDM1_Channel0
1530#define DFSDM_Channel1 DFSDM1_Channel1
1531#define DFSDM_Channel2 DFSDM1_Channel2
1532#define DFSDM_Channel3 DFSDM1_Channel3
1533#define DFSDM_Channel4 DFSDM1_Channel4
1534#define DFSDM_Channel5 DFSDM1_Channel5
1535#define DFSDM_Channel6 DFSDM1_Channel6
1536#define DFSDM_Channel7 DFSDM1_Channel7
1537#define DFSDM_Filter0 DFSDM1_Filter0
1538#define DFSDM_Filter1 DFSDM1_Filter1
1539#define DFSDM_Filter2 DFSDM1_Filter2
1540#define DFSDM_Filter3 DFSDM1_Filter3
1541#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1542#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1543#define RCC ((RCC_TypeDef *) RCC_BASE)
1544#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1545#define CRC ((CRC_TypeDef *) CRC_BASE)
1546#define TSC ((TSC_TypeDef *) TSC_BASE)
1547
1548#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1549#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1550#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1551#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1552#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1553#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1554#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1555#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1556#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1557#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1558#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1559#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1560#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1561#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1562#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1563#define HASH ((HASH_TypeDef *) HASH_BASE)
1564#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1565#define AES ((AES_TypeDef *) AES_BASE)
1566#define RNG ((RNG_TypeDef *) RNG_BASE)
1567
1568
1569#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1570#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1571#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1572#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1573#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1574#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1575#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1576#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
1577
1578
1579#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1580#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1581#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1582#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1583#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1584#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1585#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1586#define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
1587
1588
1589#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1590#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1591#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1592
1593#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1594
1595#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1596
1597#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1609#define LSI_STARTUP_TIME 130U
1619/******************************************************************************/
1620/* Peripheral Registers_Bits_Definition */
1621/******************************************************************************/
1622
1623/******************************************************************************/
1624/* */
1625/* Analog to Digital Converter */
1626/* */
1627/******************************************************************************/
1628
1629/*
1630 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
1631 */
1632#define ADC_MULTIMODE_SUPPORT
1634/******************** Bit definition for ADC_ISR register *******************/
1635#define ADC_ISR_ADRDY_Pos (0U)
1636#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)
1637#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk
1638#define ADC_ISR_EOSMP_Pos (1U)
1639#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)
1640#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk
1641#define ADC_ISR_EOC_Pos (2U)
1642#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)
1643#define ADC_ISR_EOC ADC_ISR_EOC_Msk
1644#define ADC_ISR_EOS_Pos (3U)
1645#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)
1646#define ADC_ISR_EOS ADC_ISR_EOS_Msk
1647#define ADC_ISR_OVR_Pos (4U)
1648#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)
1649#define ADC_ISR_OVR ADC_ISR_OVR_Msk
1650#define ADC_ISR_JEOC_Pos (5U)
1651#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)
1652#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk
1653#define ADC_ISR_JEOS_Pos (6U)
1654#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)
1655#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk
1656#define ADC_ISR_AWD1_Pos (7U)
1657#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)
1658#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk
1659#define ADC_ISR_AWD2_Pos (8U)
1660#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)
1661#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk
1662#define ADC_ISR_AWD3_Pos (9U)
1663#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)
1664#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk
1665#define ADC_ISR_JQOVF_Pos (10U)
1666#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)
1667#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk
1669/******************** Bit definition for ADC_IER register *******************/
1670#define ADC_IER_ADRDYIE_Pos (0U)
1671#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)
1672#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk
1673#define ADC_IER_EOSMPIE_Pos (1U)
1674#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)
1675#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk
1676#define ADC_IER_EOCIE_Pos (2U)
1677#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)
1678#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk
1679#define ADC_IER_EOSIE_Pos (3U)
1680#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)
1681#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk
1682#define ADC_IER_OVRIE_Pos (4U)
1683#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)
1684#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk
1685#define ADC_IER_JEOCIE_Pos (5U)
1686#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)
1687#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk
1688#define ADC_IER_JEOSIE_Pos (6U)
1689#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)
1690#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk
1691#define ADC_IER_AWD1IE_Pos (7U)
1692#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)
1693#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk
1694#define ADC_IER_AWD2IE_Pos (8U)
1695#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)
1696#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk
1697#define ADC_IER_AWD3IE_Pos (9U)
1698#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)
1699#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk
1700#define ADC_IER_JQOVFIE_Pos (10U)
1701#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)
1702#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk
1704/* Legacy defines */
1705#define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
1706#define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
1707#define ADC_IER_EOC (ADC_IER_EOCIE)
1708#define ADC_IER_EOS (ADC_IER_EOSIE)
1709#define ADC_IER_OVR (ADC_IER_OVRIE)
1710#define ADC_IER_JEOC (ADC_IER_JEOCIE)
1711#define ADC_IER_JEOS (ADC_IER_JEOSIE)
1712#define ADC_IER_AWD1 (ADC_IER_AWD1IE)
1713#define ADC_IER_AWD2 (ADC_IER_AWD2IE)
1714#define ADC_IER_AWD3 (ADC_IER_AWD3IE)
1715#define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
1716
1717/******************** Bit definition for ADC_CR register ********************/
1718#define ADC_CR_ADEN_Pos (0U)
1719#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)
1720#define ADC_CR_ADEN ADC_CR_ADEN_Msk
1721#define ADC_CR_ADDIS_Pos (1U)
1722#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)
1723#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk
1724#define ADC_CR_ADSTART_Pos (2U)
1725#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)
1726#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk
1727#define ADC_CR_JADSTART_Pos (3U)
1728#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)
1729#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk
1730#define ADC_CR_ADSTP_Pos (4U)
1731#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)
1732#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk
1733#define ADC_CR_JADSTP_Pos (5U)
1734#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)
1735#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk
1736#define ADC_CR_ADVREGEN_Pos (28U)
1737#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)
1738#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk
1739#define ADC_CR_DEEPPWD_Pos (29U)
1740#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos)
1741#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk
1742#define ADC_CR_ADCALDIF_Pos (30U)
1743#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)
1744#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk
1745#define ADC_CR_ADCAL_Pos (31U)
1746#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)
1747#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk
1749/******************** Bit definition for ADC_CFGR register ******************/
1750#define ADC_CFGR_DMAEN_Pos (0U)
1751#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos)
1752#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk
1753#define ADC_CFGR_DMACFG_Pos (1U)
1754#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos)
1755#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk
1757#define ADC_CFGR_DFSDMCFG_Pos (2U)
1758#define ADC_CFGR_DFSDMCFG_Msk (0x1UL << ADC_CFGR_DFSDMCFG_Pos)
1759#define ADC_CFGR_DFSDMCFG ADC_CFGR_DFSDMCFG_Msk
1761#define ADC_CFGR_RES_Pos (3U)
1762#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos)
1763#define ADC_CFGR_RES ADC_CFGR_RES_Msk
1764#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)
1765#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)
1767#define ADC_CFGR_ALIGN_Pos (5U)
1768#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos)
1769#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk
1771#define ADC_CFGR_EXTSEL_Pos (6U)
1772#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos)
1773#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk
1774#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos)
1775#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos)
1776#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos)
1777#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos)
1779#define ADC_CFGR_EXTEN_Pos (10U)
1780#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)
1781#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk
1782#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)
1783#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)
1785#define ADC_CFGR_OVRMOD_Pos (12U)
1786#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)
1787#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk
1788#define ADC_CFGR_CONT_Pos (13U)
1789#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)
1790#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk
1791#define ADC_CFGR_AUTDLY_Pos (14U)
1792#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)
1793#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk
1795#define ADC_CFGR_DISCEN_Pos (16U)
1796#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)
1797#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk
1799#define ADC_CFGR_DISCNUM_Pos (17U)
1800#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)
1801#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk
1802#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)
1803#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)
1804#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)
1806#define ADC_CFGR_JDISCEN_Pos (20U)
1807#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)
1808#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk
1809#define ADC_CFGR_JQM_Pos (21U)
1810#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)
1811#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk
1812#define ADC_CFGR_AWD1SGL_Pos (22U)
1813#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)
1814#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk
1815#define ADC_CFGR_AWD1EN_Pos (23U)
1816#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)
1817#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk
1818#define ADC_CFGR_JAWD1EN_Pos (24U)
1819#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)
1820#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk
1821#define ADC_CFGR_JAUTO_Pos (25U)
1822#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)
1823#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk
1825#define ADC_CFGR_AWD1CH_Pos (26U)
1826#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)
1827#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk
1828#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)
1829#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)
1830#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)
1831#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)
1832#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)
1834#define ADC_CFGR_JQDIS_Pos (31U)
1835#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos)
1836#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk
1838/******************** Bit definition for ADC_CFGR2 register *****************/
1839#define ADC_CFGR2_ROVSE_Pos (0U)
1840#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos)
1841#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk
1842#define ADC_CFGR2_JOVSE_Pos (1U)
1843#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos)
1844#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk
1846#define ADC_CFGR2_OVSR_Pos (2U)
1847#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos)
1848#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk
1849#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos)
1850#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos)
1851#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos)
1853#define ADC_CFGR2_OVSS_Pos (5U)
1854#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)
1855#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk
1856#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)
1857#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)
1858#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)
1859#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)
1861#define ADC_CFGR2_TROVS_Pos (9U)
1862#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos)
1863#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk
1864#define ADC_CFGR2_ROVSM_Pos (10U)
1865#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos)
1866#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk
1868/******************** Bit definition for ADC_SMPR1 register *****************/
1869#define ADC_SMPR1_SMP0_Pos (0U)
1870#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)
1871#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk
1872#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)
1873#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)
1874#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)
1876#define ADC_SMPR1_SMP1_Pos (3U)
1877#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)
1878#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk
1879#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)
1880#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)
1881#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)
1883#define ADC_SMPR1_SMP2_Pos (6U)
1884#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)
1885#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk
1886#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)
1887#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)
1888#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)
1890#define ADC_SMPR1_SMP3_Pos (9U)
1891#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)
1892#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk
1893#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)
1894#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)
1895#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)
1897#define ADC_SMPR1_SMP4_Pos (12U)
1898#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)
1899#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk
1900#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)
1901#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)
1902#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)
1904#define ADC_SMPR1_SMP5_Pos (15U)
1905#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)
1906#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk
1907#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)
1908#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)
1909#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)
1911#define ADC_SMPR1_SMP6_Pos (18U)
1912#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)
1913#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk
1914#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)
1915#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)
1916#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)
1918#define ADC_SMPR1_SMP7_Pos (21U)
1919#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)
1920#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk
1921#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)
1922#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)
1923#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)
1925#define ADC_SMPR1_SMP8_Pos (24U)
1926#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)
1927#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk
1928#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)
1929#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)
1930#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)
1932#define ADC_SMPR1_SMP9_Pos (27U)
1933#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)
1934#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk
1935#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)
1936#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)
1937#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)
1939#define ADC_SMPR1_SMPPLUS_Pos (31U)
1940#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos)
1941#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk
1943/******************** Bit definition for ADC_SMPR2 register *****************/
1944#define ADC_SMPR2_SMP10_Pos (0U)
1945#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)
1946#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk
1947#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)
1948#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)
1949#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)
1951#define ADC_SMPR2_SMP11_Pos (3U)
1952#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)
1953#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk
1954#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)
1955#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)
1956#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)
1958#define ADC_SMPR2_SMP12_Pos (6U)
1959#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)
1960#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk
1961#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)
1962#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)
1963#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)
1965#define ADC_SMPR2_SMP13_Pos (9U)
1966#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)
1967#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk
1968#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)
1969#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)
1970#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)
1972#define ADC_SMPR2_SMP14_Pos (12U)
1973#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)
1974#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk
1975#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)
1976#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)
1977#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)
1979#define ADC_SMPR2_SMP15_Pos (15U)
1980#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)
1981#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk
1982#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)
1983#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)
1984#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)
1986#define ADC_SMPR2_SMP16_Pos (18U)
1987#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)
1988#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk
1989#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)
1990#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)
1991#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)
1993#define ADC_SMPR2_SMP17_Pos (21U)
1994#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)
1995#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk
1996#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)
1997#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)
1998#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)
2000#define ADC_SMPR2_SMP18_Pos (24U)
2001#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)
2002#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk
2003#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)
2004#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)
2005#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)
2007/******************** Bit definition for ADC_TR1 register *******************/
2008#define ADC_TR1_LT1_Pos (0U)
2009#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos)
2010#define ADC_TR1_LT1 ADC_TR1_LT1_Msk
2011#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos)
2012#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos)
2013#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos)
2014#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos)
2015#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos)
2016#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos)
2017#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos)
2018#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos)
2019#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos)
2020#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos)
2021#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos)
2022#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos)
2024#define ADC_TR1_HT1_Pos (16U)
2025#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos)
2026#define ADC_TR1_HT1 ADC_TR1_HT1_Msk
2027#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos)
2028#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos)
2029#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos)
2030#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos)
2031#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos)
2032#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos)
2033#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos)
2034#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos)
2035#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos)
2036#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos)
2037#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos)
2038#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos)
2040/******************** Bit definition for ADC_TR2 register *******************/
2041#define ADC_TR2_LT2_Pos (0U)
2042#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos)
2043#define ADC_TR2_LT2 ADC_TR2_LT2_Msk
2044#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos)
2045#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos)
2046#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos)
2047#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos)
2048#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos)
2049#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos)
2050#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos)
2051#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos)
2053#define ADC_TR2_HT2_Pos (16U)
2054#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos)
2055#define ADC_TR2_HT2 ADC_TR2_HT2_Msk
2056#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos)
2057#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos)
2058#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos)
2059#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos)
2060#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos)
2061#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos)
2062#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos)
2063#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos)
2065/******************** Bit definition for ADC_TR3 register *******************/
2066#define ADC_TR3_LT3_Pos (0U)
2067#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos)
2068#define ADC_TR3_LT3 ADC_TR3_LT3_Msk
2069#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos)
2070#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos)
2071#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos)
2072#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos)
2073#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos)
2074#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos)
2075#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos)
2076#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos)
2078#define ADC_TR3_HT3_Pos (16U)
2079#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos)
2080#define ADC_TR3_HT3 ADC_TR3_HT3_Msk
2081#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos)
2082#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos)
2083#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos)
2084#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos)
2085#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos)
2086#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos)
2087#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos)
2088#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos)
2090/******************** Bit definition for ADC_SQR1 register ******************/
2091#define ADC_SQR1_L_Pos (0U)
2092#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
2093#define ADC_SQR1_L ADC_SQR1_L_Msk
2094#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
2095#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
2096#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
2097#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
2099#define ADC_SQR1_SQ1_Pos (6U)
2100#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)
2101#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk
2102#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)
2103#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)
2104#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)
2105#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)
2106#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)
2108#define ADC_SQR1_SQ2_Pos (12U)
2109#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)
2110#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk
2111#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)
2112#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)
2113#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)
2114#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)
2115#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)
2117#define ADC_SQR1_SQ3_Pos (18U)
2118#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)
2119#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk
2120#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)
2121#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)
2122#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)
2123#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)
2124#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos)
2126#define ADC_SQR1_SQ4_Pos (24U)
2127#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)
2128#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk
2129#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)
2130#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)
2131#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)
2132#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)
2133#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)
2135/******************** Bit definition for ADC_SQR2 register ******************/
2136#define ADC_SQR2_SQ5_Pos (0U)
2137#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)
2138#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk
2139#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)
2140#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)
2141#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)
2142#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)
2143#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)
2145#define ADC_SQR2_SQ6_Pos (6U)
2146#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)
2147#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk
2148#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)
2149#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)
2150#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)
2151#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)
2152#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)
2154#define ADC_SQR2_SQ7_Pos (12U)
2155#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
2156#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
2157#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
2158#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
2159#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
2160#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
2161#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
2163#define ADC_SQR2_SQ8_Pos (18U)
2164#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
2165#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
2166#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
2167#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
2168#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
2169#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
2170#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
2172#define ADC_SQR2_SQ9_Pos (24U)
2173#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
2174#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
2175#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
2176#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
2177#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
2178#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
2179#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
2181/******************** Bit definition for ADC_SQR3 register ******************/
2182#define ADC_SQR3_SQ10_Pos (0U)
2183#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)
2184#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk
2185#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)
2186#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)
2187#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)
2188#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)
2189#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)
2191#define ADC_SQR3_SQ11_Pos (6U)
2192#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)
2193#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk
2194#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)
2195#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)
2196#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)
2197#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)
2198#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)
2200#define ADC_SQR3_SQ12_Pos (12U)
2201#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)
2202#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk
2203#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)
2204#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)
2205#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)
2206#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)
2207#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)
2209#define ADC_SQR3_SQ13_Pos (18U)
2210#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)
2211#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk
2212#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)
2213#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)
2214#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)
2215#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)
2216#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)
2218#define ADC_SQR3_SQ14_Pos (24U)
2219#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)
2220#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk
2221#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)
2222#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)
2223#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)
2224#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)
2225#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)
2227/******************** Bit definition for ADC_SQR4 register ******************/
2228#define ADC_SQR4_SQ15_Pos (0U)
2229#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)
2230#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk
2231#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)
2232#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)
2233#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)
2234#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)
2235#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)
2237#define ADC_SQR4_SQ16_Pos (6U)
2238#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)
2239#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk
2240#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)
2241#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)
2242#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)
2243#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)
2244#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)
2246/******************** Bit definition for ADC_DR register ********************/
2247#define ADC_DR_RDATA_Pos (0U)
2248#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos)
2249#define ADC_DR_RDATA ADC_DR_RDATA_Msk
2250#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos)
2251#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos)
2252#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos)
2253#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos)
2254#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos)
2255#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos)
2256#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos)
2257#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos)
2258#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos)
2259#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos)
2260#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos)
2261#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos)
2262#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos)
2263#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos)
2264#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos)
2265#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos)
2267/******************** Bit definition for ADC_JSQR register ******************/
2268#define ADC_JSQR_JL_Pos (0U)
2269#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
2270#define ADC_JSQR_JL ADC_JSQR_JL_Msk
2271#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
2272#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
2274#define ADC_JSQR_JEXTSEL_Pos (2U)
2275#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos)
2276#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk
2277#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos)
2278#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos)
2279#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos)
2280#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos)
2282#define ADC_JSQR_JEXTEN_Pos (6U)
2283#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)
2284#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk
2285#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)
2286#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)
2288#define ADC_JSQR_JSQ1_Pos (8U)
2289#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
2290#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
2291#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
2292#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
2293#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
2294#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
2295#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
2297#define ADC_JSQR_JSQ2_Pos (14U)
2298#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
2299#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
2300#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
2301#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
2302#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
2303#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
2304#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
2306#define ADC_JSQR_JSQ3_Pos (20U)
2307#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
2308#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
2309#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
2310#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
2311#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
2312#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
2313#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
2315#define ADC_JSQR_JSQ4_Pos (26U)
2316#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
2317#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
2318#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
2319#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
2320#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
2321#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
2322#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
2324/******************** Bit definition for ADC_OFR1 register ******************/
2325#define ADC_OFR1_OFFSET1_Pos (0U)
2326#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos)
2327#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk
2328#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos)
2329#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos)
2330#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos)
2331#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos)
2332#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos)
2333#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos)
2334#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos)
2335#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos)
2336#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos)
2337#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos)
2338#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos)
2339#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos)
2341#define ADC_OFR1_OFFSET1_CH_Pos (26U)
2342#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)
2343#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk
2344#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)
2345#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)
2346#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)
2347#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)
2348#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)
2350#define ADC_OFR1_OFFSET1_EN_Pos (31U)
2351#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)
2352#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk
2354/******************** Bit definition for ADC_OFR2 register ******************/
2355#define ADC_OFR2_OFFSET2_Pos (0U)
2356#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos)
2357#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk
2358#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos)
2359#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos)
2360#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos)
2361#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos)
2362#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos)
2363#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos)
2364#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos)
2365#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos)
2366#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos)
2367#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos)
2368#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos)
2369#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos)
2371#define ADC_OFR2_OFFSET2_CH_Pos (26U)
2372#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)
2373#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk
2374#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)
2375#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)
2376#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)
2377#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)
2378#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)
2380#define ADC_OFR2_OFFSET2_EN_Pos (31U)
2381#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)
2382#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk
2384/******************** Bit definition for ADC_OFR3 register ******************/
2385#define ADC_OFR3_OFFSET3_Pos (0U)
2386#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos)
2387#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk
2388#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos)
2389#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos)
2390#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos)
2391#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos)
2392#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos)
2393#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos)
2394#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos)
2395#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos)
2396#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos)
2397#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos)
2398#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos)
2399#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos)
2401#define ADC_OFR3_OFFSET3_CH_Pos (26U)
2402#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)
2403#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk
2404#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)
2405#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)
2406#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)
2407#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)
2408#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)
2410#define ADC_OFR3_OFFSET3_EN_Pos (31U)
2411#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)
2412#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk
2414/******************** Bit definition for ADC_OFR4 register ******************/
2415#define ADC_OFR4_OFFSET4_Pos (0U)
2416#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos)
2417#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk
2418#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos)
2419#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos)
2420#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos)
2421#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos)
2422#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos)
2423#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos)
2424#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos)
2425#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos)
2426#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos)
2427#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos)
2428#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos)
2429#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos)
2431#define ADC_OFR4_OFFSET4_CH_Pos (26U)
2432#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)
2433#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk
2434#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)
2435#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)
2436#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)
2437#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)
2438#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)
2440#define ADC_OFR4_OFFSET4_EN_Pos (31U)
2441#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)
2442#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk
2444/******************** Bit definition for ADC_JDR1 register ******************/
2445#define ADC_JDR1_JDATA_Pos (0U)
2446#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
2447#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
2448#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos)
2449#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos)
2450#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos)
2451#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos)
2452#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos)
2453#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos)
2454#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos)
2455#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos)
2456#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos)
2457#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos)
2458#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos)
2459#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos)
2460#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos)
2461#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos)
2462#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos)
2463#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos)
2465/******************** Bit definition for ADC_JDR2 register ******************/
2466#define ADC_JDR2_JDATA_Pos (0U)
2467#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
2468#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
2469#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos)
2470#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos)
2471#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos)
2472#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos)
2473#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos)
2474#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos)
2475#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos)
2476#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos)
2477#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos)
2478#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos)
2479#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos)
2480#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos)
2481#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos)
2482#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos)
2483#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos)
2484#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos)
2486/******************** Bit definition for ADC_JDR3 register ******************/
2487#define ADC_JDR3_JDATA_Pos (0U)
2488#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
2489#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
2490#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos)
2491#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos)
2492#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos)
2493#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos)
2494#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos)
2495#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos)
2496#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos)
2497#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos)
2498#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos)
2499#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos)
2500#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos)
2501#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos)
2502#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos)
2503#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos)
2504#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos)
2505#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos)
2507/******************** Bit definition for ADC_JDR4 register ******************/
2508#define ADC_JDR4_JDATA_Pos (0U)
2509#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
2510#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
2511#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos)
2512#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos)
2513#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos)
2514#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos)
2515#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos)
2516#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos)
2517#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos)
2518#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos)
2519#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos)
2520#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos)
2521#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos)
2522#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos)
2523#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos)
2524#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos)
2525#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos)
2526#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos)
2528/******************** Bit definition for ADC_AWD2CR register ****************/
2529#define ADC_AWD2CR_AWD2CH_Pos (0U)
2530#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)
2531#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk
2532#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)
2533#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)
2534#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)
2535#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)
2536#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)
2537#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)
2538#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)
2539#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)
2540#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)
2541#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)
2542#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)
2543#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)
2544#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)
2545#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)
2546#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)
2547#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)
2548#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)
2549#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)
2550#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)
2552/******************** Bit definition for ADC_AWD3CR register ****************/
2553#define ADC_AWD3CR_AWD3CH_Pos (0U)
2554#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)
2555#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk
2556#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)
2557#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)
2558#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)
2559#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)
2560#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)
2561#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)
2562#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)
2563#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)
2564#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)
2565#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)
2566#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)
2567#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)
2568#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)
2569#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)
2570#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)
2571#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)
2572#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)
2573#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)
2574#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)
2576/******************** Bit definition for ADC_DIFSEL register ****************/
2577#define ADC_DIFSEL_DIFSEL_Pos (0U)
2578#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)
2579#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk
2580#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)
2581#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)
2582#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)
2583#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)
2584#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)
2585#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)
2586#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)
2587#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)
2588#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)
2589#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)
2590#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)
2591#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)
2592#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)
2593#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)
2594#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)
2595#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)
2596#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)
2597#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)
2598#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)
2600/******************** Bit definition for ADC_CALFACT register ***************/
2601#define ADC_CALFACT_CALFACT_S_Pos (0U)
2602#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)
2603#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk
2604#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos)
2605#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos)
2606#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos)
2607#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos)
2608#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos)
2609#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos)
2610#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos)
2612#define ADC_CALFACT_CALFACT_D_Pos (16U)
2613#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)
2614#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk
2615#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos)
2616#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos)
2617#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos)
2618#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos)
2619#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos)
2620#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos)
2621#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos)
2623/************************* ADC Common registers *****************************/
2624/******************** Bit definition for ADC_CSR register *******************/
2625#define ADC_CSR_ADRDY_MST_Pos (0U)
2626#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos)
2627#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk
2628#define ADC_CSR_EOSMP_MST_Pos (1U)
2629#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos)
2630#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk
2631#define ADC_CSR_EOC_MST_Pos (2U)
2632#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos)
2633#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk
2634#define ADC_CSR_EOS_MST_Pos (3U)
2635#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos)
2636#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk
2637#define ADC_CSR_OVR_MST_Pos (4U)
2638#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos)
2639#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk
2640#define ADC_CSR_JEOC_MST_Pos (5U)
2641#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos)
2642#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk
2643#define ADC_CSR_JEOS_MST_Pos (6U)
2644#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos)
2645#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk
2646#define ADC_CSR_AWD1_MST_Pos (7U)
2647#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos)
2648#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk
2649#define ADC_CSR_AWD2_MST_Pos (8U)
2650#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos)
2651#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk
2652#define ADC_CSR_AWD3_MST_Pos (9U)
2653#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos)
2654#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk
2655#define ADC_CSR_JQOVF_MST_Pos (10U)
2656#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos)
2657#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk
2659#define ADC_CSR_ADRDY_SLV_Pos (16U)
2660#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos)
2661#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk
2662#define ADC_CSR_EOSMP_SLV_Pos (17U)
2663#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos)
2664#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk
2665#define ADC_CSR_EOC_SLV_Pos (18U)
2666#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos)
2667#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk
2668#define ADC_CSR_EOS_SLV_Pos (19U)
2669#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos)
2670#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk
2671#define ADC_CSR_OVR_SLV_Pos (20U)
2672#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos)
2673#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk
2674#define ADC_CSR_JEOC_SLV_Pos (21U)
2675#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos)
2676#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk
2677#define ADC_CSR_JEOS_SLV_Pos (22U)
2678#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos)
2679#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk
2680#define ADC_CSR_AWD1_SLV_Pos (23U)
2681#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos)
2682#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk
2683#define ADC_CSR_AWD2_SLV_Pos (24U)
2684#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos)
2685#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk
2686#define ADC_CSR_AWD3_SLV_Pos (25U)
2687#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos)
2688#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk
2689#define ADC_CSR_JQOVF_SLV_Pos (26U)
2690#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos)
2691#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk
2693/******************** Bit definition for ADC_CCR register *******************/
2694#define ADC_CCR_DUAL_Pos (0U)
2695#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos)
2696#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk
2697#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos)
2698#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos)
2699#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos)
2700#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos)
2701#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos)
2703#define ADC_CCR_DELAY_Pos (8U)
2704#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
2705#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
2706#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
2707#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
2708#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
2709#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
2711#define ADC_CCR_DMACFG_Pos (13U)
2712#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos)
2713#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk
2715#define ADC_CCR_MDMA_Pos (14U)
2716#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos)
2717#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk
2718#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos)
2719#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos)
2721#define ADC_CCR_CKMODE_Pos (16U)
2722#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)
2723#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk
2724#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)
2725#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)
2727#define ADC_CCR_PRESC_Pos (18U)
2728#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)
2729#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk
2730#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)
2731#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)
2732#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)
2733#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)
2735#define ADC_CCR_VREFEN_Pos (22U)
2736#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)
2737#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk
2738#define ADC_CCR_TSEN_Pos (23U)
2739#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)
2740#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk
2741#define ADC_CCR_VBATEN_Pos (24U)
2742#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)
2743#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk
2745/******************** Bit definition for ADC_CDR register *******************/
2746#define ADC_CDR_RDATA_MST_Pos (0U)
2747#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)
2748#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk
2749#define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos)
2750#define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos)
2751#define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos)
2752#define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos)
2753#define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos)
2754#define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos)
2755#define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos)
2756#define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos)
2757#define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos)
2758#define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos)
2759#define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos)
2760#define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos)
2761#define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos)
2762#define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos)
2763#define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos)
2764#define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos)
2766#define ADC_CDR_RDATA_SLV_Pos (16U)
2767#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)
2768#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk
2769#define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos)
2770#define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos)
2771#define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos)
2772#define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos)
2773#define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos)
2774#define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos)
2775#define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos)
2776#define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos)
2777#define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos)
2778#define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos)
2779#define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos)
2780#define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos)
2781#define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos)
2782#define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos)
2783#define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos)
2784#define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos)
2786/******************************************************************************/
2787/* */
2788/* Controller Area Network */
2789/* */
2790/******************************************************************************/
2792/******************* Bit definition for CAN_MCR register ********************/
2793#define CAN_MCR_INRQ_Pos (0U)
2794#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
2795#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
2796#define CAN_MCR_SLEEP_Pos (1U)
2797#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
2798#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
2799#define CAN_MCR_TXFP_Pos (2U)
2800#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
2801#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
2802#define CAN_MCR_RFLM_Pos (3U)
2803#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
2804#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
2805#define CAN_MCR_NART_Pos (4U)
2806#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
2807#define CAN_MCR_NART CAN_MCR_NART_Msk
2808#define CAN_MCR_AWUM_Pos (5U)
2809#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
2810#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
2811#define CAN_MCR_ABOM_Pos (6U)
2812#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
2813#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
2814#define CAN_MCR_TTCM_Pos (7U)
2815#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
2816#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
2817#define CAN_MCR_RESET_Pos (15U)
2818#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
2819#define CAN_MCR_RESET CAN_MCR_RESET_Msk
2821/******************* Bit definition for CAN_MSR register ********************/
2822#define CAN_MSR_INAK_Pos (0U)
2823#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
2824#define CAN_MSR_INAK CAN_MSR_INAK_Msk
2825#define CAN_MSR_SLAK_Pos (1U)
2826#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
2827#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
2828#define CAN_MSR_ERRI_Pos (2U)
2829#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
2830#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
2831#define CAN_MSR_WKUI_Pos (3U)
2832#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
2833#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
2834#define CAN_MSR_SLAKI_Pos (4U)
2835#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
2836#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
2837#define CAN_MSR_TXM_Pos (8U)
2838#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
2839#define CAN_MSR_TXM CAN_MSR_TXM_Msk
2840#define CAN_MSR_RXM_Pos (9U)
2841#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
2842#define CAN_MSR_RXM CAN_MSR_RXM_Msk
2843#define CAN_MSR_SAMP_Pos (10U)
2844#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
2845#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
2846#define CAN_MSR_RX_Pos (11U)
2847#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
2848#define CAN_MSR_RX CAN_MSR_RX_Msk
2850/******************* Bit definition for CAN_TSR register ********************/
2851#define CAN_TSR_RQCP0_Pos (0U)
2852#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
2853#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
2854#define CAN_TSR_TXOK0_Pos (1U)
2855#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
2856#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
2857#define CAN_TSR_ALST0_Pos (2U)
2858#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
2859#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
2860#define CAN_TSR_TERR0_Pos (3U)
2861#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
2862#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
2863#define CAN_TSR_ABRQ0_Pos (7U)
2864#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
2865#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
2866#define CAN_TSR_RQCP1_Pos (8U)
2867#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
2868#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
2869#define CAN_TSR_TXOK1_Pos (9U)
2870#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
2871#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
2872#define CAN_TSR_ALST1_Pos (10U)
2873#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
2874#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
2875#define CAN_TSR_TERR1_Pos (11U)
2876#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
2877#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
2878#define CAN_TSR_ABRQ1_Pos (15U)
2879#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
2880#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
2881#define CAN_TSR_RQCP2_Pos (16U)
2882#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
2883#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
2884#define CAN_TSR_TXOK2_Pos (17U)
2885#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
2886#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
2887#define CAN_TSR_ALST2_Pos (18U)
2888#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
2889#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
2890#define CAN_TSR_TERR2_Pos (19U)
2891#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
2892#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
2893#define CAN_TSR_ABRQ2_Pos (23U)
2894#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
2895#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
2896#define CAN_TSR_CODE_Pos (24U)
2897#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
2898#define CAN_TSR_CODE CAN_TSR_CODE_Msk
2900#define CAN_TSR_TME_Pos (26U)
2901#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
2902#define CAN_TSR_TME CAN_TSR_TME_Msk
2903#define CAN_TSR_TME0_Pos (26U)
2904#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
2905#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
2906#define CAN_TSR_TME1_Pos (27U)
2907#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
2908#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
2909#define CAN_TSR_TME2_Pos (28U)
2910#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
2911#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
2913#define CAN_TSR_LOW_Pos (29U)
2914#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
2915#define CAN_TSR_LOW CAN_TSR_LOW_Msk
2916#define CAN_TSR_LOW0_Pos (29U)
2917#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
2918#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
2919#define CAN_TSR_LOW1_Pos (30U)
2920#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
2921#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
2922#define CAN_TSR_LOW2_Pos (31U)
2923#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
2924#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
2926/******************* Bit definition for CAN_RF0R register *******************/
2927#define CAN_RF0R_FMP0_Pos (0U)
2928#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
2929#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
2930#define CAN_RF0R_FULL0_Pos (3U)
2931#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
2932#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
2933#define CAN_RF0R_FOVR0_Pos (4U)
2934#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
2935#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
2936#define CAN_RF0R_RFOM0_Pos (5U)
2937#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
2938#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
2940/******************* Bit definition for CAN_RF1R register *******************/
2941#define CAN_RF1R_FMP1_Pos (0U)
2942#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
2943#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
2944#define CAN_RF1R_FULL1_Pos (3U)
2945#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
2946#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
2947#define CAN_RF1R_FOVR1_Pos (4U)
2948#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
2949#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
2950#define CAN_RF1R_RFOM1_Pos (5U)
2951#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
2952#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
2954/******************** Bit definition for CAN_IER register *******************/
2955#define CAN_IER_TMEIE_Pos (0U)
2956#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
2957#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
2958#define CAN_IER_FMPIE0_Pos (1U)
2959#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
2960#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
2961#define CAN_IER_FFIE0_Pos (2U)
2962#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
2963#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
2964#define CAN_IER_FOVIE0_Pos (3U)
2965#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
2966#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
2967#define CAN_IER_FMPIE1_Pos (4U)
2968#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
2969#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
2970#define CAN_IER_FFIE1_Pos (5U)
2971#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
2972#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
2973#define CAN_IER_FOVIE1_Pos (6U)
2974#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
2975#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
2976#define CAN_IER_EWGIE_Pos (8U)
2977#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
2978#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
2979#define CAN_IER_EPVIE_Pos (9U)
2980#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
2981#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
2982#define CAN_IER_BOFIE_Pos (10U)
2983#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
2984#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
2985#define CAN_IER_LECIE_Pos (11U)
2986#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
2987#define CAN_IER_LECIE CAN_IER_LECIE_Msk
2988#define CAN_IER_ERRIE_Pos (15U)
2989#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
2990#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
2991#define CAN_IER_WKUIE_Pos (16U)
2992#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
2993#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
2994#define CAN_IER_SLKIE_Pos (17U)
2995#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
2996#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
2998/******************** Bit definition for CAN_ESR register *******************/
2999#define CAN_ESR_EWGF_Pos (0U)
3000#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
3001#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
3002#define CAN_ESR_EPVF_Pos (1U)
3003#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
3004#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
3005#define CAN_ESR_BOFF_Pos (2U)
3006#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
3007#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
3009#define CAN_ESR_LEC_Pos (4U)
3010#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
3011#define CAN_ESR_LEC CAN_ESR_LEC_Msk
3012#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
3013#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
3014#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
3016#define CAN_ESR_TEC_Pos (16U)
3017#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
3018#define CAN_ESR_TEC CAN_ESR_TEC_Msk
3019#define CAN_ESR_REC_Pos (24U)
3020#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
3021#define CAN_ESR_REC CAN_ESR_REC_Msk
3023/******************* Bit definition for CAN_BTR register ********************/
3024#define CAN_BTR_BRP_Pos (0U)
3025#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
3026#define CAN_BTR_BRP CAN_BTR_BRP_Msk
3027#define CAN_BTR_TS1_Pos (16U)
3028#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
3029#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
3030#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
3031#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
3032#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
3033#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
3034#define CAN_BTR_TS2_Pos (20U)
3035#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
3036#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
3037#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
3038#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
3039#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
3040#define CAN_BTR_SJW_Pos (24U)
3041#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
3042#define CAN_BTR_SJW CAN_BTR_SJW_Msk
3043#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
3044#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
3045#define CAN_BTR_LBKM_Pos (30U)
3046#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
3047#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
3048#define CAN_BTR_SILM_Pos (31U)
3049#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
3050#define CAN_BTR_SILM CAN_BTR_SILM_Msk
3053/****************** Bit definition for CAN_TI0R register ********************/
3054#define CAN_TI0R_TXRQ_Pos (0U)
3055#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
3056#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
3057#define CAN_TI0R_RTR_Pos (1U)
3058#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
3059#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
3060#define CAN_TI0R_IDE_Pos (2U)
3061#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
3062#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
3063#define CAN_TI0R_EXID_Pos (3U)
3064#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
3065#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
3066#define CAN_TI0R_STID_Pos (21U)
3067#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
3068#define CAN_TI0R_STID CAN_TI0R_STID_Msk
3070/****************** Bit definition for CAN_TDT0R register *******************/
3071#define CAN_TDT0R_DLC_Pos (0U)
3072#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
3073#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
3074#define CAN_TDT0R_TGT_Pos (8U)
3075#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
3076#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
3077#define CAN_TDT0R_TIME_Pos (16U)
3078#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
3079#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
3081/****************** Bit definition for CAN_TDL0R register *******************/
3082#define CAN_TDL0R_DATA0_Pos (0U)
3083#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
3084#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
3085#define CAN_TDL0R_DATA1_Pos (8U)
3086#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
3087#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
3088#define CAN_TDL0R_DATA2_Pos (16U)
3089#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
3090#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
3091#define CAN_TDL0R_DATA3_Pos (24U)
3092#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
3093#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
3095/****************** Bit definition for CAN_TDH0R register *******************/
3096#define CAN_TDH0R_DATA4_Pos (0U)
3097#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
3098#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
3099#define CAN_TDH0R_DATA5_Pos (8U)
3100#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
3101#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
3102#define CAN_TDH0R_DATA6_Pos (16U)
3103#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
3104#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
3105#define CAN_TDH0R_DATA7_Pos (24U)
3106#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
3107#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
3109/******************* Bit definition for CAN_TI1R register *******************/
3110#define CAN_TI1R_TXRQ_Pos (0U)
3111#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
3112#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
3113#define CAN_TI1R_RTR_Pos (1U)
3114#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
3115#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
3116#define CAN_TI1R_IDE_Pos (2U)
3117#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
3118#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
3119#define CAN_TI1R_EXID_Pos (3U)
3120#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
3121#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
3122#define CAN_TI1R_STID_Pos (21U)
3123#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
3124#define CAN_TI1R_STID CAN_TI1R_STID_Msk
3126/******************* Bit definition for CAN_TDT1R register ******************/
3127#define CAN_TDT1R_DLC_Pos (0U)
3128#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
3129#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
3130#define CAN_TDT1R_TGT_Pos (8U)
3131#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
3132#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
3133#define CAN_TDT1R_TIME_Pos (16U)
3134#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
3135#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
3137/******************* Bit definition for CAN_TDL1R register ******************/
3138#define CAN_TDL1R_DATA0_Pos (0U)
3139#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
3140#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
3141#define CAN_TDL1R_DATA1_Pos (8U)
3142#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
3143#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
3144#define CAN_TDL1R_DATA2_Pos (16U)
3145#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
3146#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
3147#define CAN_TDL1R_DATA3_Pos (24U)
3148#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
3149#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
3151/******************* Bit definition for CAN_TDH1R register ******************/
3152#define CAN_TDH1R_DATA4_Pos (0U)
3153#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
3154#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
3155#define CAN_TDH1R_DATA5_Pos (8U)
3156#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
3157#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
3158#define CAN_TDH1R_DATA6_Pos (16U)
3159#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
3160#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
3161#define CAN_TDH1R_DATA7_Pos (24U)
3162#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
3163#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
3165/******************* Bit definition for CAN_TI2R register *******************/
3166#define CAN_TI2R_TXRQ_Pos (0U)
3167#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
3168#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
3169#define CAN_TI2R_RTR_Pos (1U)
3170#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
3171#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
3172#define CAN_TI2R_IDE_Pos (2U)
3173#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
3174#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
3175#define CAN_TI2R_EXID_Pos (3U)
3176#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
3177#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
3178#define CAN_TI2R_STID_Pos (21U)
3179#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
3180#define CAN_TI2R_STID CAN_TI2R_STID_Msk
3182/******************* Bit definition for CAN_TDT2R register ******************/
3183#define CAN_TDT2R_DLC_Pos (0U)
3184#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
3185#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
3186#define CAN_TDT2R_TGT_Pos (8U)
3187#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
3188#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
3189#define CAN_TDT2R_TIME_Pos (16U)
3190#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
3191#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
3193/******************* Bit definition for CAN_TDL2R register ******************/
3194#define CAN_TDL2R_DATA0_Pos (0U)
3195#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
3196#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
3197#define CAN_TDL2R_DATA1_Pos (8U)
3198#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
3199#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
3200#define CAN_TDL2R_DATA2_Pos (16U)
3201#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
3202#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
3203#define CAN_TDL2R_DATA3_Pos (24U)
3204#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
3205#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
3207/******************* Bit definition for CAN_TDH2R register ******************/
3208#define CAN_TDH2R_DATA4_Pos (0U)
3209#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
3210#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
3211#define CAN_TDH2R_DATA5_Pos (8U)
3212#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
3213#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
3214#define CAN_TDH2R_DATA6_Pos (16U)
3215#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
3216#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
3217#define CAN_TDH2R_DATA7_Pos (24U)
3218#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
3219#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
3221/******************* Bit definition for CAN_RI0R register *******************/
3222#define CAN_RI0R_RTR_Pos (1U)
3223#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
3224#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
3225#define CAN_RI0R_IDE_Pos (2U)
3226#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
3227#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
3228#define CAN_RI0R_EXID_Pos (3U)
3229#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
3230#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
3231#define CAN_RI0R_STID_Pos (21U)
3232#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
3233#define CAN_RI0R_STID CAN_RI0R_STID_Msk
3235/******************* Bit definition for CAN_RDT0R register ******************/
3236#define CAN_RDT0R_DLC_Pos (0U)
3237#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
3238#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
3239#define CAN_RDT0R_FMI_Pos (8U)
3240#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
3241#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
3242#define CAN_RDT0R_TIME_Pos (16U)
3243#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
3244#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
3246/******************* Bit definition for CAN_RDL0R register ******************/
3247#define CAN_RDL0R_DATA0_Pos (0U)
3248#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
3249#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
3250#define CAN_RDL0R_DATA1_Pos (8U)
3251#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
3252#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
3253#define CAN_RDL0R_DATA2_Pos (16U)
3254#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
3255#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
3256#define CAN_RDL0R_DATA3_Pos (24U)
3257#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
3258#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
3260/******************* Bit definition for CAN_RDH0R register ******************/
3261#define CAN_RDH0R_DATA4_Pos (0U)
3262#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
3263#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
3264#define CAN_RDH0R_DATA5_Pos (8U)
3265#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
3266#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
3267#define CAN_RDH0R_DATA6_Pos (16U)
3268#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
3269#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
3270#define CAN_RDH0R_DATA7_Pos (24U)
3271#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
3272#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
3274/******************* Bit definition for CAN_RI1R register *******************/
3275#define CAN_RI1R_RTR_Pos (1U)
3276#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
3277#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
3278#define CAN_RI1R_IDE_Pos (2U)
3279#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
3280#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
3281#define CAN_RI1R_EXID_Pos (3U)
3282#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
3283#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
3284#define CAN_RI1R_STID_Pos (21U)
3285#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
3286#define CAN_RI1R_STID CAN_RI1R_STID_Msk
3288/******************* Bit definition for CAN_RDT1R register ******************/
3289#define CAN_RDT1R_DLC_Pos (0U)
3290#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
3291#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
3292#define CAN_RDT1R_FMI_Pos (8U)
3293#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
3294#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
3295#define CAN_RDT1R_TIME_Pos (16U)
3296#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
3297#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
3299/******************* Bit definition for CAN_RDL1R register ******************/
3300#define CAN_RDL1R_DATA0_Pos (0U)
3301#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
3302#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
3303#define CAN_RDL1R_DATA1_Pos (8U)
3304#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
3305#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
3306#define CAN_RDL1R_DATA2_Pos (16U)
3307#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
3308#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
3309#define CAN_RDL1R_DATA3_Pos (24U)
3310#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
3311#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
3313/******************* Bit definition for CAN_RDH1R register ******************/
3314#define CAN_RDH1R_DATA4_Pos (0U)
3315#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
3316#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
3317#define CAN_RDH1R_DATA5_Pos (8U)
3318#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
3319#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
3320#define CAN_RDH1R_DATA6_Pos (16U)
3321#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
3322#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
3323#define CAN_RDH1R_DATA7_Pos (24U)
3324#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
3325#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
3328/******************* Bit definition for CAN_FMR register ********************/
3329#define CAN_FMR_FINIT_Pos (0U)
3330#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
3331#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
3332#define CAN_FMR_CAN2SB_Pos (8U)
3333#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
3334#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
3336/******************* Bit definition for CAN_FM1R register *******************/
3337#define CAN_FM1R_FBM_Pos (0U)
3338#define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos)
3339#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
3340#define CAN_FM1R_FBM0_Pos (0U)
3341#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
3342#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
3343#define CAN_FM1R_FBM1_Pos (1U)
3344#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
3345#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
3346#define CAN_FM1R_FBM2_Pos (2U)
3347#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
3348#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
3349#define CAN_FM1R_FBM3_Pos (3U)
3350#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
3351#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
3352#define CAN_FM1R_FBM4_Pos (4U)
3353#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
3354#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
3355#define CAN_FM1R_FBM5_Pos (5U)
3356#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
3357#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
3358#define CAN_FM1R_FBM6_Pos (6U)
3359#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
3360#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
3361#define CAN_FM1R_FBM7_Pos (7U)
3362#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
3363#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
3364#define CAN_FM1R_FBM8_Pos (8U)
3365#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
3366#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
3367#define CAN_FM1R_FBM9_Pos (9U)
3368#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
3369#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
3370#define CAN_FM1R_FBM10_Pos (10U)
3371#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
3372#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
3373#define CAN_FM1R_FBM11_Pos (11U)
3374#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
3375#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
3376#define CAN_FM1R_FBM12_Pos (12U)
3377#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
3378#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
3379#define CAN_FM1R_FBM13_Pos (13U)
3380#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
3381#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
3383/******************* Bit definition for CAN_FS1R register *******************/
3384#define CAN_FS1R_FSC_Pos (0U)
3385#define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos)
3386#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
3387#define CAN_FS1R_FSC0_Pos (0U)
3388#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
3389#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
3390#define CAN_FS1R_FSC1_Pos (1U)
3391#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
3392#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
3393#define CAN_FS1R_FSC2_Pos (2U)
3394#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
3395#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
3396#define CAN_FS1R_FSC3_Pos (3U)
3397#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
3398#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
3399#define CAN_FS1R_FSC4_Pos (4U)
3400#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
3401#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
3402#define CAN_FS1R_FSC5_Pos (5U)
3403#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
3404#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
3405#define CAN_FS1R_FSC6_Pos (6U)
3406#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
3407#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
3408#define CAN_FS1R_FSC7_Pos (7U)
3409#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
3410#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
3411#define CAN_FS1R_FSC8_Pos (8U)
3412#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
3413#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
3414#define CAN_FS1R_FSC9_Pos (9U)
3415#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
3416#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
3417#define CAN_FS1R_FSC10_Pos (10U)
3418#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
3419#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
3420#define CAN_FS1R_FSC11_Pos (11U)
3421#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
3422#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
3423#define CAN_FS1R_FSC12_Pos (12U)
3424#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
3425#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
3426#define CAN_FS1R_FSC13_Pos (13U)
3427#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
3428#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
3430/****************** Bit definition for CAN_FFA1R register *******************/
3431#define CAN_FFA1R_FFA_Pos (0U)
3432#define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos)
3433#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
3434#define CAN_FFA1R_FFA0_Pos (0U)
3435#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
3436#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
3437#define CAN_FFA1R_FFA1_Pos (1U)
3438#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
3439#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
3440#define CAN_FFA1R_FFA2_Pos (2U)
3441#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
3442#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
3443#define CAN_FFA1R_FFA3_Pos (3U)
3444#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
3445#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
3446#define CAN_FFA1R_FFA4_Pos (4U)
3447#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
3448#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
3449#define CAN_FFA1R_FFA5_Pos (5U)
3450#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
3451#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
3452#define CAN_FFA1R_FFA6_Pos (6U)
3453#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
3454#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
3455#define CAN_FFA1R_FFA7_Pos (7U)
3456#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
3457#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
3458#define CAN_FFA1R_FFA8_Pos (8U)
3459#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
3460#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
3461#define CAN_FFA1R_FFA9_Pos (9U)
3462#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
3463#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
3464#define CAN_FFA1R_FFA10_Pos (10U)
3465#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
3466#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
3467#define CAN_FFA1R_FFA11_Pos (11U)
3468#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
3469#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
3470#define CAN_FFA1R_FFA12_Pos (12U)
3471#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
3472#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
3473#define CAN_FFA1R_FFA13_Pos (13U)
3474#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
3475#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
3477/******************* Bit definition for CAN_FA1R register *******************/
3478#define CAN_FA1R_FACT_Pos (0U)
3479#define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos)
3480#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
3481#define CAN_FA1R_FACT0_Pos (0U)
3482#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
3483#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
3484#define CAN_FA1R_FACT1_Pos (1U)
3485#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
3486#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
3487#define CAN_FA1R_FACT2_Pos (2U)
3488#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
3489#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
3490#define CAN_FA1R_FACT3_Pos (3U)
3491#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
3492#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
3493#define CAN_FA1R_FACT4_Pos (4U)
3494#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
3495#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
3496#define CAN_FA1R_FACT5_Pos (5U)
3497#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
3498#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
3499#define CAN_FA1R_FACT6_Pos (6U)
3500#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
3501#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
3502#define CAN_FA1R_FACT7_Pos (7U)
3503#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
3504#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
3505#define CAN_FA1R_FACT8_Pos (8U)
3506#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
3507#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
3508#define CAN_FA1R_FACT9_Pos (9U)
3509#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
3510#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
3511#define CAN_FA1R_FACT10_Pos (10U)
3512#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
3513#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
3514#define CAN_FA1R_FACT11_Pos (11U)
3515#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
3516#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
3517#define CAN_FA1R_FACT12_Pos (12U)
3518#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
3519#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
3520#define CAN_FA1R_FACT13_Pos (13U)
3521#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
3522#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
3524/******************* Bit definition for CAN_F0R1 register *******************/
3525#define CAN_F0R1_FB0_Pos (0U)
3526#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
3527#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
3528#define CAN_F0R1_FB1_Pos (1U)
3529#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
3530#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
3531#define CAN_F0R1_FB2_Pos (2U)
3532#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
3533#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
3534#define CAN_F0R1_FB3_Pos (3U)
3535#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
3536#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
3537#define CAN_F0R1_FB4_Pos (4U)
3538#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
3539#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
3540#define CAN_F0R1_FB5_Pos (5U)
3541#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
3542#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
3543#define CAN_F0R1_FB6_Pos (6U)
3544#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
3545#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
3546#define CAN_F0R1_FB7_Pos (7U)
3547#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
3548#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
3549#define CAN_F0R1_FB8_Pos (8U)
3550#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
3551#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
3552#define CAN_F0R1_FB9_Pos (9U)
3553#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
3554#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
3555#define CAN_F0R1_FB10_Pos (10U)
3556#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
3557#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
3558#define CAN_F0R1_FB11_Pos (11U)
3559#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
3560#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
3561#define CAN_F0R1_FB12_Pos (12U)
3562#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
3563#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
3564#define CAN_F0R1_FB13_Pos (13U)
3565#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
3566#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
3567#define CAN_F0R1_FB14_Pos (14U)
3568#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
3569#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
3570#define CAN_F0R1_FB15_Pos (15U)
3571#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
3572#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
3573#define CAN_F0R1_FB16_Pos (16U)
3574#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
3575#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
3576#define CAN_F0R1_FB17_Pos (17U)
3577#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
3578#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
3579#define CAN_F0R1_FB18_Pos (18U)
3580#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
3581#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
3582#define CAN_F0R1_FB19_Pos (19U)
3583#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
3584#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
3585#define CAN_F0R1_FB20_Pos (20U)
3586#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
3587#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
3588#define CAN_F0R1_FB21_Pos (21U)
3589#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
3590#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
3591#define CAN_F0R1_FB22_Pos (22U)
3592#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
3593#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
3594#define CAN_F0R1_FB23_Pos (23U)
3595#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
3596#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
3597#define CAN_F0R1_FB24_Pos (24U)
3598#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
3599#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
3600#define CAN_F0R1_FB25_Pos (25U)
3601#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
3602#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
3603#define CAN_F0R1_FB26_Pos (26U)
3604#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
3605#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
3606#define CAN_F0R1_FB27_Pos (27U)
3607#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
3608#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
3609#define CAN_F0R1_FB28_Pos (28U)
3610#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
3611#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
3612#define CAN_F0R1_FB29_Pos (29U)
3613#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
3614#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
3615#define CAN_F0R1_FB30_Pos (30U)
3616#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
3617#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
3618#define CAN_F0R1_FB31_Pos (31U)
3619#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
3620#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
3622/******************* Bit definition for CAN_F1R1 register *******************/
3623#define CAN_F1R1_FB0_Pos (0U)
3624#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
3625#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
3626#define CAN_F1R1_FB1_Pos (1U)
3627#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
3628#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
3629#define CAN_F1R1_FB2_Pos (2U)
3630#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
3631#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
3632#define CAN_F1R1_FB3_Pos (3U)
3633#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
3634#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
3635#define CAN_F1R1_FB4_Pos (4U)
3636#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
3637#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
3638#define CAN_F1R1_FB5_Pos (5U)
3639#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
3640#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
3641#define CAN_F1R1_FB6_Pos (6U)
3642#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
3643#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
3644#define CAN_F1R1_FB7_Pos (7U)
3645#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
3646#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
3647#define CAN_F1R1_FB8_Pos (8U)
3648#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
3649#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
3650#define CAN_F1R1_FB9_Pos (9U)
3651#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
3652#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
3653#define CAN_F1R1_FB10_Pos (10U)
3654#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
3655#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
3656#define CAN_F1R1_FB11_Pos (11U)
3657#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
3658#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
3659#define CAN_F1R1_FB12_Pos (12U)
3660#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
3661#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
3662#define CAN_F1R1_FB13_Pos (13U)
3663#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
3664#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
3665#define CAN_F1R1_FB14_Pos (14U)
3666#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
3667#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
3668#define CAN_F1R1_FB15_Pos (15U)
3669#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
3670#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
3671#define CAN_F1R1_FB16_Pos (16U)
3672#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
3673#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
3674#define CAN_F1R1_FB17_Pos (17U)
3675#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
3676#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
3677#define CAN_F1R1_FB18_Pos (18U)
3678#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
3679#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
3680#define CAN_F1R1_FB19_Pos (19U)
3681#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
3682#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
3683#define CAN_F1R1_FB20_Pos (20U)
3684#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
3685#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
3686#define CAN_F1R1_FB21_Pos (21U)
3687#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
3688#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
3689#define CAN_F1R1_FB22_Pos (22U)
3690#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
3691#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
3692#define CAN_F1R1_FB23_Pos (23U)
3693#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
3694#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
3695#define CAN_F1R1_FB24_Pos (24U)
3696#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
3697#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
3698#define CAN_F1R1_FB25_Pos (25U)
3699#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
3700#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
3701#define CAN_F1R1_FB26_Pos (26U)
3702#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
3703#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
3704#define CAN_F1R1_FB27_Pos (27U)
3705#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
3706#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
3707#define CAN_F1R1_FB28_Pos (28U)
3708#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
3709#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
3710#define CAN_F1R1_FB29_Pos (29U)
3711#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
3712#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
3713#define CAN_F1R1_FB30_Pos (30U)
3714#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
3715#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
3716#define CAN_F1R1_FB31_Pos (31U)
3717#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
3718#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
3720/******************* Bit definition for CAN_F2R1 register *******************/
3721#define CAN_F2R1_FB0_Pos (0U)
3722#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
3723#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
3724#define CAN_F2R1_FB1_Pos (1U)
3725#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
3726#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
3727#define CAN_F2R1_FB2_Pos (2U)
3728#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
3729#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
3730#define CAN_F2R1_FB3_Pos (3U)
3731#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
3732#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
3733#define CAN_F2R1_FB4_Pos (4U)
3734#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
3735#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
3736#define CAN_F2R1_FB5_Pos (5U)
3737#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
3738#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
3739#define CAN_F2R1_FB6_Pos (6U)
3740#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
3741#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
3742#define CAN_F2R1_FB7_Pos (7U)
3743#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
3744#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
3745#define CAN_F2R1_FB8_Pos (8U)
3746#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
3747#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
3748#define CAN_F2R1_FB9_Pos (9U)
3749#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
3750#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
3751#define CAN_F2R1_FB10_Pos (10U)
3752#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
3753#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
3754#define CAN_F2R1_FB11_Pos (11U)
3755#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
3756#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
3757#define CAN_F2R1_FB12_Pos (12U)
3758#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
3759#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
3760#define CAN_F2R1_FB13_Pos (13U)
3761#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
3762#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
3763#define CAN_F2R1_FB14_Pos (14U)
3764#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
3765#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
3766#define CAN_F2R1_FB15_Pos (15U)
3767#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
3768#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
3769#define CAN_F2R1_FB16_Pos (16U)
3770#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
3771#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
3772#define CAN_F2R1_FB17_Pos (17U)
3773#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
3774#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
3775#define CAN_F2R1_FB18_Pos (18U)
3776#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
3777#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
3778#define CAN_F2R1_FB19_Pos (19U)
3779#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
3780#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
3781#define CAN_F2R1_FB20_Pos (20U)
3782#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
3783#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
3784#define CAN_F2R1_FB21_Pos (21U)
3785#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
3786#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
3787#define CAN_F2R1_FB22_Pos (22U)
3788#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
3789#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
3790#define CAN_F2R1_FB23_Pos (23U)
3791#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
3792#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
3793#define CAN_F2R1_FB24_Pos (24U)
3794#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
3795#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
3796#define CAN_F2R1_FB25_Pos (25U)
3797#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
3798#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
3799#define CAN_F2R1_FB26_Pos (26U)
3800#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
3801#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
3802#define CAN_F2R1_FB27_Pos (27U)
3803#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
3804#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
3805#define CAN_F2R1_FB28_Pos (28U)
3806#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
3807#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
3808#define CAN_F2R1_FB29_Pos (29U)
3809#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
3810#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
3811#define CAN_F2R1_FB30_Pos (30U)
3812#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
3813#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
3814#define CAN_F2R1_FB31_Pos (31U)
3815#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
3816#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
3818/******************* Bit definition for CAN_F3R1 register *******************/
3819#define CAN_F3R1_FB0_Pos (0U)
3820#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
3821#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
3822#define CAN_F3R1_FB1_Pos (1U)
3823#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
3824#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
3825#define CAN_F3R1_FB2_Pos (2U)
3826#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
3827#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
3828#define CAN_F3R1_FB3_Pos (3U)
3829#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
3830#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
3831#define CAN_F3R1_FB4_Pos (4U)
3832#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
3833#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
3834#define CAN_F3R1_FB5_Pos (5U)
3835#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
3836#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
3837#define CAN_F3R1_FB6_Pos (6U)
3838#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
3839#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
3840#define CAN_F3R1_FB7_Pos (7U)
3841#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
3842#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
3843#define CAN_F3R1_FB8_Pos (8U)
3844#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
3845#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
3846#define CAN_F3R1_FB9_Pos (9U)
3847#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
3848#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
3849#define CAN_F3R1_FB10_Pos (10U)
3850#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
3851#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
3852#define CAN_F3R1_FB11_Pos (11U)
3853#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3854#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3855#define CAN_F3R1_FB12_Pos (12U)
3856#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3857#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3858#define CAN_F3R1_FB13_Pos (13U)
3859#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3860#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3861#define CAN_F3R1_FB14_Pos (14U)
3862#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3863#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3864#define CAN_F3R1_FB15_Pos (15U)
3865#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3866#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3867#define CAN_F3R1_FB16_Pos (16U)
3868#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3869#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3870#define CAN_F3R1_FB17_Pos (17U)
3871#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3872#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3873#define CAN_F3R1_FB18_Pos (18U)
3874#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3875#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3876#define CAN_F3R1_FB19_Pos (19U)
3877#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3878#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3879#define CAN_F3R1_FB20_Pos (20U)
3880#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3881#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3882#define CAN_F3R1_FB21_Pos (21U)
3883#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3884#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3885#define CAN_F3R1_FB22_Pos (22U)
3886#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3887#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3888#define CAN_F3R1_FB23_Pos (23U)
3889#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3890#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3891#define CAN_F3R1_FB24_Pos (24U)
3892#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3893#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3894#define CAN_F3R1_FB25_Pos (25U)
3895#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3896#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3897#define CAN_F3R1_FB26_Pos (26U)
3898#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3899#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3900#define CAN_F3R1_FB27_Pos (27U)
3901#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3902#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3903#define CAN_F3R1_FB28_Pos (28U)
3904#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3905#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3906#define CAN_F3R1_FB29_Pos (29U)
3907#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3908#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3909#define CAN_F3R1_FB30_Pos (30U)
3910#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3911#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3912#define CAN_F3R1_FB31_Pos (31U)
3913#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3914#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3916/******************* Bit definition for CAN_F4R1 register *******************/
3917#define CAN_F4R1_FB0_Pos (0U)
3918#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3919#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3920#define CAN_F4R1_FB1_Pos (1U)
3921#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3922#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3923#define CAN_F4R1_FB2_Pos (2U)
3924#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3925#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3926#define CAN_F4R1_FB3_Pos (3U)
3927#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3928#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3929#define CAN_F4R1_FB4_Pos (4U)
3930#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3931#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3932#define CAN_F4R1_FB5_Pos (5U)
3933#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3934#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3935#define CAN_F4R1_FB6_Pos (6U)
3936#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3937#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3938#define CAN_F4R1_FB7_Pos (7U)
3939#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3940#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3941#define CAN_F4R1_FB8_Pos (8U)
3942#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3943#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3944#define CAN_F4R1_FB9_Pos (9U)
3945#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3946#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3947#define CAN_F4R1_FB10_Pos (10U)
3948#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3949#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3950#define CAN_F4R1_FB11_Pos (11U)
3951#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3952#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3953#define CAN_F4R1_FB12_Pos (12U)
3954#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3955#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3956#define CAN_F4R1_FB13_Pos (13U)
3957#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3958#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3959#define CAN_F4R1_FB14_Pos (14U)
3960#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3961#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3962#define CAN_F4R1_FB15_Pos (15U)
3963#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3964#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3965#define CAN_F4R1_FB16_Pos (16U)
3966#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3967#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3968#define CAN_F4R1_FB17_Pos (17U)
3969#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3970#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3971#define CAN_F4R1_FB18_Pos (18U)
3972#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3973#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3974#define CAN_F4R1_FB19_Pos (19U)
3975#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3976#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3977#define CAN_F4R1_FB20_Pos (20U)
3978#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3979#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3980#define CAN_F4R1_FB21_Pos (21U)
3981#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3982#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3983#define CAN_F4R1_FB22_Pos (22U)
3984#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3985#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3986#define CAN_F4R1_FB23_Pos (23U)
3987#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3988#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3989#define CAN_F4R1_FB24_Pos (24U)
3990#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3991#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3992#define CAN_F4R1_FB25_Pos (25U)
3993#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3994#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3995#define CAN_F4R1_FB26_Pos (26U)
3996#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3997#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3998#define CAN_F4R1_FB27_Pos (27U)
3999#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
4000#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
4001#define CAN_F4R1_FB28_Pos (28U)
4002#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
4003#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
4004#define CAN_F4R1_FB29_Pos (29U)
4005#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
4006#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
4007#define CAN_F4R1_FB30_Pos (30U)
4008#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
4009#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
4010#define CAN_F4R1_FB31_Pos (31U)
4011#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
4012#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
4014/******************* Bit definition for CAN_F5R1 register *******************/
4015#define CAN_F5R1_FB0_Pos (0U)
4016#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
4017#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
4018#define CAN_F5R1_FB1_Pos (1U)
4019#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
4020#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
4021#define CAN_F5R1_FB2_Pos (2U)
4022#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
4023#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
4024#define CAN_F5R1_FB3_Pos (3U)
4025#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
4026#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
4027#define CAN_F5R1_FB4_Pos (4U)
4028#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
4029#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
4030#define CAN_F5R1_FB5_Pos (5U)
4031#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
4032#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
4033#define CAN_F5R1_FB6_Pos (6U)
4034#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
4035#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
4036#define CAN_F5R1_FB7_Pos (7U)
4037#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
4038#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
4039#define CAN_F5R1_FB8_Pos (8U)
4040#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
4041#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
4042#define CAN_F5R1_FB9_Pos (9U)
4043#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
4044#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
4045#define CAN_F5R1_FB10_Pos (10U)
4046#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
4047#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
4048#define CAN_F5R1_FB11_Pos (11U)
4049#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
4050#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
4051#define CAN_F5R1_FB12_Pos (12U)
4052#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
4053#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
4054#define CAN_F5R1_FB13_Pos (13U)
4055#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
4056#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
4057#define CAN_F5R1_FB14_Pos (14U)
4058#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
4059#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
4060#define CAN_F5R1_FB15_Pos (15U)
4061#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
4062#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
4063#define CAN_F5R1_FB16_Pos (16U)
4064#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
4065#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
4066#define CAN_F5R1_FB17_Pos (17U)
4067#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
4068#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
4069#define CAN_F5R1_FB18_Pos (18U)
4070#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
4071#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
4072#define CAN_F5R1_FB19_Pos (19U)
4073#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
4074#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
4075#define CAN_F5R1_FB20_Pos (20U)
4076#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
4077#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
4078#define CAN_F5R1_FB21_Pos (21U)
4079#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
4080#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
4081#define CAN_F5R1_FB22_Pos (22U)
4082#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
4083#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
4084#define CAN_F5R1_FB23_Pos (23U)
4085#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
4086#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
4087#define CAN_F5R1_FB24_Pos (24U)
4088#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
4089#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
4090#define CAN_F5R1_FB25_Pos (25U)
4091#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
4092#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
4093#define CAN_F5R1_FB26_Pos (26U)
4094#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
4095#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
4096#define CAN_F5R1_FB27_Pos (27U)
4097#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
4098#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
4099#define CAN_F5R1_FB28_Pos (28U)
4100#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
4101#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
4102#define CAN_F5R1_FB29_Pos (29U)
4103#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
4104#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
4105#define CAN_F5R1_FB30_Pos (30U)
4106#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
4107#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
4108#define CAN_F5R1_FB31_Pos (31U)
4109#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
4110#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
4112/******************* Bit definition for CAN_F6R1 register *******************/
4113#define CAN_F6R1_FB0_Pos (0U)
4114#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
4115#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
4116#define CAN_F6R1_FB1_Pos (1U)
4117#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
4118#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
4119#define CAN_F6R1_FB2_Pos (2U)
4120#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
4121#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
4122#define CAN_F6R1_FB3_Pos (3U)
4123#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
4124#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
4125#define CAN_F6R1_FB4_Pos (4U)
4126#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
4127#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
4128#define CAN_F6R1_FB5_Pos (5U)
4129#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
4130#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
4131#define CAN_F6R1_FB6_Pos (6U)
4132#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
4133#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
4134#define CAN_F6R1_FB7_Pos (7U)
4135#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
4136#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
4137#define CAN_F6R1_FB8_Pos (8U)
4138#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
4139#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
4140#define CAN_F6R1_FB9_Pos (9U)
4141#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
4142#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
4143#define CAN_F6R1_FB10_Pos (10U)
4144#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
4145#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
4146#define CAN_F6R1_FB11_Pos (11U)
4147#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
4148#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
4149#define CAN_F6R1_FB12_Pos (12U)
4150#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
4151#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
4152#define CAN_F6R1_FB13_Pos (13U)
4153#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
4154#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
4155#define CAN_F6R1_FB14_Pos (14U)
4156#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
4157#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
4158#define CAN_F6R1_FB15_Pos (15U)
4159#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
4160#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
4161#define CAN_F6R1_FB16_Pos (16U)
4162#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
4163#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
4164#define CAN_F6R1_FB17_Pos (17U)
4165#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
4166#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
4167#define CAN_F6R1_FB18_Pos (18U)
4168#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
4169#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
4170#define CAN_F6R1_FB19_Pos (19U)
4171#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
4172#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
4173#define CAN_F6R1_FB20_Pos (20U)
4174#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
4175#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
4176#define CAN_F6R1_FB21_Pos (21U)
4177#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
4178#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
4179#define CAN_F6R1_FB22_Pos (22U)
4180#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
4181#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
4182#define CAN_F6R1_FB23_Pos (23U)
4183#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
4184#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
4185#define CAN_F6R1_FB24_Pos (24U)
4186#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
4187#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
4188#define CAN_F6R1_FB25_Pos (25U)
4189#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
4190#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
4191#define CAN_F6R1_FB26_Pos (26U)
4192#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
4193#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
4194#define CAN_F6R1_FB27_Pos (27U)
4195#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
4196#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
4197#define CAN_F6R1_FB28_Pos (28U)
4198#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
4199#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
4200#define CAN_F6R1_FB29_Pos (29U)
4201#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
4202#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
4203#define CAN_F6R1_FB30_Pos (30U)
4204#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
4205#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
4206#define CAN_F6R1_FB31_Pos (31U)
4207#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
4208#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
4210/******************* Bit definition for CAN_F7R1 register *******************/
4211#define CAN_F7R1_FB0_Pos (0U)
4212#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
4213#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
4214#define CAN_F7R1_FB1_Pos (1U)
4215#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
4216#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
4217#define CAN_F7R1_FB2_Pos (2U)
4218#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
4219#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
4220#define CAN_F7R1_FB3_Pos (3U)
4221#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
4222#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
4223#define CAN_F7R1_FB4_Pos (4U)
4224#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
4225#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
4226#define CAN_F7R1_FB5_Pos (5U)
4227#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
4228#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
4229#define CAN_F7R1_FB6_Pos (6U)
4230#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
4231#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
4232#define CAN_F7R1_FB7_Pos (7U)
4233#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
4234#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
4235#define CAN_F7R1_FB8_Pos (8U)
4236#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
4237#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
4238#define CAN_F7R1_FB9_Pos (9U)
4239#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
4240#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
4241#define CAN_F7R1_FB10_Pos (10U)
4242#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
4243#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
4244#define CAN_F7R1_FB11_Pos (11U)
4245#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
4246#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
4247#define CAN_F7R1_FB12_Pos (12U)
4248#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
4249#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
4250#define CAN_F7R1_FB13_Pos (13U)
4251#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
4252#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
4253#define CAN_F7R1_FB14_Pos (14U)
4254#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
4255#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
4256#define CAN_F7R1_FB15_Pos (15U)
4257#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
4258#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
4259#define CAN_F7R1_FB16_Pos (16U)
4260#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
4261#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
4262#define CAN_F7R1_FB17_Pos (17U)
4263#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
4264#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
4265#define CAN_F7R1_FB18_Pos (18U)
4266#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
4267#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
4268#define CAN_F7R1_FB19_Pos (19U)
4269#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
4270#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
4271#define CAN_F7R1_FB20_Pos (20U)
4272#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
4273#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
4274#define CAN_F7R1_FB21_Pos (21U)
4275#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
4276#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
4277#define CAN_F7R1_FB22_Pos (22U)
4278#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
4279#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
4280#define CAN_F7R1_FB23_Pos (23U)
4281#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
4282#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
4283#define CAN_F7R1_FB24_Pos (24U)
4284#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
4285#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
4286#define CAN_F7R1_FB25_Pos (25U)
4287#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
4288#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
4289#define CAN_F7R1_FB26_Pos (26U)
4290#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
4291#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
4292#define CAN_F7R1_FB27_Pos (27U)
4293#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
4294#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
4295#define CAN_F7R1_FB28_Pos (28U)
4296#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
4297#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
4298#define CAN_F7R1_FB29_Pos (29U)
4299#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
4300#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
4301#define CAN_F7R1_FB30_Pos (30U)
4302#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
4303#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
4304#define CAN_F7R1_FB31_Pos (31U)
4305#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
4306#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
4308/******************* Bit definition for CAN_F8R1 register *******************/
4309#define CAN_F8R1_FB0_Pos (0U)
4310#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
4311#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
4312#define CAN_F8R1_FB1_Pos (1U)
4313#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
4314#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
4315#define CAN_F8R1_FB2_Pos (2U)
4316#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
4317#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
4318#define CAN_F8R1_FB3_Pos (3U)
4319#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
4320#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
4321#define CAN_F8R1_FB4_Pos (4U)
4322#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
4323#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
4324#define CAN_F8R1_FB5_Pos (5U)
4325#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
4326#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
4327#define CAN_F8R1_FB6_Pos (6U)
4328#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
4329#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
4330#define CAN_F8R1_FB7_Pos (7U)
4331#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
4332#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
4333#define CAN_F8R1_FB8_Pos (8U)
4334#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
4335#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
4336#define CAN_F8R1_FB9_Pos (9U)
4337#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
4338#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
4339#define CAN_F8R1_FB10_Pos (10U)
4340#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
4341#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
4342#define CAN_F8R1_FB11_Pos (11U)
4343#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
4344#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
4345#define CAN_F8R1_FB12_Pos (12U)
4346#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
4347#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
4348#define CAN_F8R1_FB13_Pos (13U)
4349#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
4350#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
4351#define CAN_F8R1_FB14_Pos (14U)
4352#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
4353#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
4354#define CAN_F8R1_FB15_Pos (15U)
4355#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
4356#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
4357#define CAN_F8R1_FB16_Pos (16U)
4358#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
4359#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
4360#define CAN_F8R1_FB17_Pos (17U)
4361#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
4362#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
4363#define CAN_F8R1_FB18_Pos (18U)
4364#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
4365#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
4366#define CAN_F8R1_FB19_Pos (19U)
4367#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
4368#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
4369#define CAN_F8R1_FB20_Pos (20U)
4370#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
4371#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
4372#define CAN_F8R1_FB21_Pos (21U)
4373#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
4374#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
4375#define CAN_F8R1_FB22_Pos (22U)
4376#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
4377#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
4378#define CAN_F8R1_FB23_Pos (23U)
4379#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
4380#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
4381#define CAN_F8R1_FB24_Pos (24U)
4382#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
4383#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
4384#define CAN_F8R1_FB25_Pos (25U)
4385#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
4386#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
4387#define CAN_F8R1_FB26_Pos (26U)
4388#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
4389#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
4390#define CAN_F8R1_FB27_Pos (27U)
4391#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
4392#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
4393#define CAN_F8R1_FB28_Pos (28U)
4394#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
4395#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
4396#define CAN_F8R1_FB29_Pos (29U)
4397#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
4398#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
4399#define CAN_F8R1_FB30_Pos (30U)
4400#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
4401#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
4402#define CAN_F8R1_FB31_Pos (31U)
4403#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
4404#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
4406/******************* Bit definition for CAN_F9R1 register *******************/
4407#define CAN_F9R1_FB0_Pos (0U)
4408#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
4409#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
4410#define CAN_F9R1_FB1_Pos (1U)
4411#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
4412#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
4413#define CAN_F9R1_FB2_Pos (2U)
4414#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
4415#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
4416#define CAN_F9R1_FB3_Pos (3U)
4417#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
4418#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
4419#define CAN_F9R1_FB4_Pos (4U)
4420#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
4421#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
4422#define CAN_F9R1_FB5_Pos (5U)
4423#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
4424#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
4425#define CAN_F9R1_FB6_Pos (6U)
4426#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
4427#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
4428#define CAN_F9R1_FB7_Pos (7U)
4429#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
4430#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
4431#define CAN_F9R1_FB8_Pos (8U)
4432#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
4433#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
4434#define CAN_F9R1_FB9_Pos (9U)
4435#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
4436#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
4437#define CAN_F9R1_FB10_Pos (10U)
4438#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
4439#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
4440#define CAN_F9R1_FB11_Pos (11U)
4441#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
4442#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
4443#define CAN_F9R1_FB12_Pos (12U)
4444#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
4445#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
4446#define CAN_F9R1_FB13_Pos (13U)
4447#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
4448#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
4449#define CAN_F9R1_FB14_Pos (14U)
4450#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
4451#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
4452#define CAN_F9R1_FB15_Pos (15U)
4453#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
4454#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
4455#define CAN_F9R1_FB16_Pos (16U)
4456#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
4457#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
4458#define CAN_F9R1_FB17_Pos (17U)
4459#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
4460#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
4461#define CAN_F9R1_FB18_Pos (18U)
4462#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
4463#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
4464#define CAN_F9R1_FB19_Pos (19U)
4465#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
4466#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
4467#define CAN_F9R1_FB20_Pos (20U)
4468#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
4469#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
4470#define CAN_F9R1_FB21_Pos (21U)
4471#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
4472#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
4473#define CAN_F9R1_FB22_Pos (22U)
4474#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
4475#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
4476#define CAN_F9R1_FB23_Pos (23U)
4477#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
4478#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
4479#define CAN_F9R1_FB24_Pos (24U)
4480#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
4481#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
4482#define CAN_F9R1_FB25_Pos (25U)
4483#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
4484#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
4485#define CAN_F9R1_FB26_Pos (26U)
4486#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
4487#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
4488#define CAN_F9R1_FB27_Pos (27U)
4489#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
4490#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
4491#define CAN_F9R1_FB28_Pos (28U)
4492#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
4493#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
4494#define CAN_F9R1_FB29_Pos (29U)
4495#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
4496#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
4497#define CAN_F9R1_FB30_Pos (30U)
4498#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
4499#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
4500#define CAN_F9R1_FB31_Pos (31U)
4501#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
4502#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
4504/******************* Bit definition for CAN_F10R1 register ******************/
4505#define CAN_F10R1_FB0_Pos (0U)
4506#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
4507#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
4508#define CAN_F10R1_FB1_Pos (1U)
4509#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
4510#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
4511#define CAN_F10R1_FB2_Pos (2U)
4512#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
4513#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
4514#define CAN_F10R1_FB3_Pos (3U)
4515#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
4516#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
4517#define CAN_F10R1_FB4_Pos (4U)
4518#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
4519#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
4520#define CAN_F10R1_FB5_Pos (5U)
4521#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
4522#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
4523#define CAN_F10R1_FB6_Pos (6U)
4524#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
4525#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
4526#define CAN_F10R1_FB7_Pos (7U)
4527#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
4528#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
4529#define CAN_F10R1_FB8_Pos (8U)
4530#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
4531#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
4532#define CAN_F10R1_FB9_Pos (9U)
4533#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
4534#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
4535#define CAN_F10R1_FB10_Pos (10U)
4536#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
4537#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
4538#define CAN_F10R1_FB11_Pos (11U)
4539#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
4540#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
4541#define CAN_F10R1_FB12_Pos (12U)
4542#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
4543#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
4544#define CAN_F10R1_FB13_Pos (13U)
4545#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
4546#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
4547#define CAN_F10R1_FB14_Pos (14U)
4548#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
4549#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
4550#define CAN_F10R1_FB15_Pos (15U)
4551#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
4552#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
4553#define CAN_F10R1_FB16_Pos (16U)
4554#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
4555#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
4556#define CAN_F10R1_FB17_Pos (17U)
4557#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
4558#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
4559#define CAN_F10R1_FB18_Pos (18U)
4560#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
4561#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
4562#define CAN_F10R1_FB19_Pos (19U)
4563#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
4564#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
4565#define CAN_F10R1_FB20_Pos (20U)
4566#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
4567#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
4568#define CAN_F10R1_FB21_Pos (21U)
4569#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
4570#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
4571#define CAN_F10R1_FB22_Pos (22U)
4572#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
4573#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
4574#define CAN_F10R1_FB23_Pos (23U)
4575#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
4576#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
4577#define CAN_F10R1_FB24_Pos (24U)
4578#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
4579#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
4580#define CAN_F10R1_FB25_Pos (25U)
4581#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
4582#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
4583#define CAN_F10R1_FB26_Pos (26U)
4584#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
4585#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
4586#define CAN_F10R1_FB27_Pos (27U)
4587#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
4588#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
4589#define CAN_F10R1_FB28_Pos (28U)
4590#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
4591#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
4592#define CAN_F10R1_FB29_Pos (29U)
4593#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
4594#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
4595#define CAN_F10R1_FB30_Pos (30U)
4596#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
4597#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
4598#define CAN_F10R1_FB31_Pos (31U)
4599#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
4600#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
4602/******************* Bit definition for CAN_F11R1 register ******************/
4603#define CAN_F11R1_FB0_Pos (0U)
4604#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
4605#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
4606#define CAN_F11R1_FB1_Pos (1U)
4607#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
4608#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
4609#define CAN_F11R1_FB2_Pos (2U)
4610#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
4611#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
4612#define CAN_F11R1_FB3_Pos (3U)
4613#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
4614#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
4615#define CAN_F11R1_FB4_Pos (4U)
4616#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
4617#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
4618#define CAN_F11R1_FB5_Pos (5U)
4619#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
4620#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
4621#define CAN_F11R1_FB6_Pos (6U)
4622#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
4623#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
4624#define CAN_F11R1_FB7_Pos (7U)
4625#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
4626#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
4627#define CAN_F11R1_FB8_Pos (8U)
4628#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
4629#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
4630#define CAN_F11R1_FB9_Pos (9U)
4631#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
4632#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
4633#define CAN_F11R1_FB10_Pos (10U)
4634#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
4635#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
4636#define CAN_F11R1_FB11_Pos (11U)
4637#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
4638#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
4639#define CAN_F11R1_FB12_Pos (12U)
4640#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
4641#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
4642#define CAN_F11R1_FB13_Pos (13U)
4643#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
4644#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
4645#define CAN_F11R1_FB14_Pos (14U)
4646#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
4647#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
4648#define CAN_F11R1_FB15_Pos (15U)
4649#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
4650#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
4651#define CAN_F11R1_FB16_Pos (16U)
4652#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
4653#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
4654#define CAN_F11R1_FB17_Pos (17U)
4655#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
4656#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
4657#define CAN_F11R1_FB18_Pos (18U)
4658#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
4659#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
4660#define CAN_F11R1_FB19_Pos (19U)
4661#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
4662#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
4663#define CAN_F11R1_FB20_Pos (20U)
4664#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
4665#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
4666#define CAN_F11R1_FB21_Pos (21U)
4667#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
4668#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
4669#define CAN_F11R1_FB22_Pos (22U)
4670#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
4671#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
4672#define CAN_F11R1_FB23_Pos (23U)
4673#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
4674#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
4675#define CAN_F11R1_FB24_Pos (24U)
4676#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
4677#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
4678#define CAN_F11R1_FB25_Pos (25U)
4679#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
4680#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
4681#define CAN_F11R1_FB26_Pos (26U)
4682#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
4683#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
4684#define CAN_F11R1_FB27_Pos (27U)
4685#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
4686#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
4687#define CAN_F11R1_FB28_Pos (28U)
4688#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
4689#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
4690#define CAN_F11R1_FB29_Pos (29U)
4691#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
4692#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
4693#define CAN_F11R1_FB30_Pos (30U)
4694#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
4695#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
4696#define CAN_F11R1_FB31_Pos (31U)
4697#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
4698#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
4700/******************* Bit definition for CAN_F12R1 register ******************/
4701#define CAN_F12R1_FB0_Pos (0U)
4702#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
4703#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
4704#define CAN_F12R1_FB1_Pos (1U)
4705#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
4706#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
4707#define CAN_F12R1_FB2_Pos (2U)
4708#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
4709#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
4710#define CAN_F12R1_FB3_Pos (3U)
4711#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
4712#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
4713#define CAN_F12R1_FB4_Pos (4U)
4714#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
4715#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
4716#define CAN_F12R1_FB5_Pos (5U)
4717#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
4718#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
4719#define CAN_F12R1_FB6_Pos (6U)
4720#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
4721#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
4722#define CAN_F12R1_FB7_Pos (7U)
4723#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
4724#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
4725#define CAN_F12R1_FB8_Pos (8U)
4726#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
4727#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
4728#define CAN_F12R1_FB9_Pos (9U)
4729#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
4730#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
4731#define CAN_F12R1_FB10_Pos (10U)
4732#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
4733#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
4734#define CAN_F12R1_FB11_Pos (11U)
4735#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
4736#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
4737#define CAN_F12R1_FB12_Pos (12U)
4738#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
4739#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
4740#define CAN_F12R1_FB13_Pos (13U)
4741#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
4742#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
4743#define CAN_F12R1_FB14_Pos (14U)
4744#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
4745#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
4746#define CAN_F12R1_FB15_Pos (15U)
4747#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
4748#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
4749#define CAN_F12R1_FB16_Pos (16U)
4750#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
4751#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
4752#define CAN_F12R1_FB17_Pos (17U)
4753#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
4754#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
4755#define CAN_F12R1_FB18_Pos (18U)
4756#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
4757#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
4758#define CAN_F12R1_FB19_Pos (19U)
4759#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
4760#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
4761#define CAN_F12R1_FB20_Pos (20U)
4762#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
4763#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
4764#define CAN_F12R1_FB21_Pos (21U)
4765#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
4766#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
4767#define CAN_F12R1_FB22_Pos (22U)
4768#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
4769#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
4770#define CAN_F12R1_FB23_Pos (23U)
4771#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
4772#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
4773#define CAN_F12R1_FB24_Pos (24U)
4774#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
4775#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
4776#define CAN_F12R1_FB25_Pos (25U)
4777#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
4778#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
4779#define CAN_F12R1_FB26_Pos (26U)
4780#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
4781#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
4782#define CAN_F12R1_FB27_Pos (27U)
4783#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
4784#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
4785#define CAN_F12R1_FB28_Pos (28U)
4786#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
4787#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
4788#define CAN_F12R1_FB29_Pos (29U)
4789#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
4790#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
4791#define CAN_F12R1_FB30_Pos (30U)
4792#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
4793#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
4794#define CAN_F12R1_FB31_Pos (31U)
4795#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
4796#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
4798/******************* Bit definition for CAN_F13R1 register ******************/
4799#define CAN_F13R1_FB0_Pos (0U)
4800#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
4801#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
4802#define CAN_F13R1_FB1_Pos (1U)
4803#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
4804#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
4805#define CAN_F13R1_FB2_Pos (2U)
4806#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
4807#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
4808#define CAN_F13R1_FB3_Pos (3U)
4809#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
4810#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
4811#define CAN_F13R1_FB4_Pos (4U)
4812#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
4813#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
4814#define CAN_F13R1_FB5_Pos (5U)
4815#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
4816#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
4817#define CAN_F13R1_FB6_Pos (6U)
4818#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
4819#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
4820#define CAN_F13R1_FB7_Pos (7U)
4821#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
4822#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
4823#define CAN_F13R1_FB8_Pos (8U)
4824#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
4825#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
4826#define CAN_F13R1_FB9_Pos (9U)
4827#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
4828#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
4829#define CAN_F13R1_FB10_Pos (10U)
4830#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
4831#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
4832#define CAN_F13R1_FB11_Pos (11U)
4833#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
4834#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
4835#define CAN_F13R1_FB12_Pos (12U)
4836#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
4837#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
4838#define CAN_F13R1_FB13_Pos (13U)
4839#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
4840#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
4841#define CAN_F13R1_FB14_Pos (14U)
4842#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
4843#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
4844#define CAN_F13R1_FB15_Pos (15U)
4845#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
4846#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
4847#define CAN_F13R1_FB16_Pos (16U)
4848#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
4849#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
4850#define CAN_F13R1_FB17_Pos (17U)
4851#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
4852#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
4853#define CAN_F13R1_FB18_Pos (18U)
4854#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4855#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4856#define CAN_F13R1_FB19_Pos (19U)
4857#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4858#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4859#define CAN_F13R1_FB20_Pos (20U)
4860#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4861#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4862#define CAN_F13R1_FB21_Pos (21U)
4863#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4864#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4865#define CAN_F13R1_FB22_Pos (22U)
4866#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4867#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4868#define CAN_F13R1_FB23_Pos (23U)
4869#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4870#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4871#define CAN_F13R1_FB24_Pos (24U)
4872#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4873#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4874#define CAN_F13R1_FB25_Pos (25U)
4875#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4876#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4877#define CAN_F13R1_FB26_Pos (26U)
4878#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4879#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4880#define CAN_F13R1_FB27_Pos (27U)
4881#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4882#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4883#define CAN_F13R1_FB28_Pos (28U)
4884#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4885#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4886#define CAN_F13R1_FB29_Pos (29U)
4887#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4888#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4889#define CAN_F13R1_FB30_Pos (30U)
4890#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4891#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4892#define CAN_F13R1_FB31_Pos (31U)
4893#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4894#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4896/******************* Bit definition for CAN_F0R2 register *******************/
4897#define CAN_F0R2_FB0_Pos (0U)
4898#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4899#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4900#define CAN_F0R2_FB1_Pos (1U)
4901#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4902#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4903#define CAN_F0R2_FB2_Pos (2U)
4904#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4905#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4906#define CAN_F0R2_FB3_Pos (3U)
4907#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4908#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4909#define CAN_F0R2_FB4_Pos (4U)
4910#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4911#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4912#define CAN_F0R2_FB5_Pos (5U)
4913#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4914#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4915#define CAN_F0R2_FB6_Pos (6U)
4916#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4917#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4918#define CAN_F0R2_FB7_Pos (7U)
4919#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4920#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4921#define CAN_F0R2_FB8_Pos (8U)
4922#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4923#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4924#define CAN_F0R2_FB9_Pos (9U)
4925#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4926#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4927#define CAN_F0R2_FB10_Pos (10U)
4928#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4929#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4930#define CAN_F0R2_FB11_Pos (11U)
4931#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4932#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4933#define CAN_F0R2_FB12_Pos (12U)
4934#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4935#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4936#define CAN_F0R2_FB13_Pos (13U)
4937#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4938#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4939#define CAN_F0R2_FB14_Pos (14U)
4940#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4941#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4942#define CAN_F0R2_FB15_Pos (15U)
4943#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4944#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4945#define CAN_F0R2_FB16_Pos (16U)
4946#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4947#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4948#define CAN_F0R2_FB17_Pos (17U)
4949#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4950#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4951#define CAN_F0R2_FB18_Pos (18U)
4952#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4953#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4954#define CAN_F0R2_FB19_Pos (19U)
4955#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4956#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4957#define CAN_F0R2_FB20_Pos (20U)
4958#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4959#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4960#define CAN_F0R2_FB21_Pos (21U)
4961#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4962#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4963#define CAN_F0R2_FB22_Pos (22U)
4964#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4965#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4966#define CAN_F0R2_FB23_Pos (23U)
4967#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4968#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4969#define CAN_F0R2_FB24_Pos (24U)
4970#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4971#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4972#define CAN_F0R2_FB25_Pos (25U)
4973#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4974#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4975#define CAN_F0R2_FB26_Pos (26U)
4976#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4977#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4978#define CAN_F0R2_FB27_Pos (27U)
4979#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4980#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4981#define CAN_F0R2_FB28_Pos (28U)
4982#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4983#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4984#define CAN_F0R2_FB29_Pos (29U)
4985#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4986#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4987#define CAN_F0R2_FB30_Pos (30U)
4988#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4989#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4990#define CAN_F0R2_FB31_Pos (31U)
4991#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4992#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4994/******************* Bit definition for CAN_F1R2 register *******************/
4995#define CAN_F1R2_FB0_Pos (0U)
4996#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4997#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4998#define CAN_F1R2_FB1_Pos (1U)
4999#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
5000#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
5001#define CAN_F1R2_FB2_Pos (2U)
5002#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
5003#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
5004#define CAN_F1R2_FB3_Pos (3U)
5005#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
5006#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
5007#define CAN_F1R2_FB4_Pos (4U)
5008#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
5009#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
5010#define CAN_F1R2_FB5_Pos (5U)
5011#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
5012#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
5013#define CAN_F1R2_FB6_Pos (6U)
5014#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
5015#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
5016#define CAN_F1R2_FB7_Pos (7U)
5017#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
5018#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
5019#define CAN_F1R2_FB8_Pos (8U)
5020#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
5021#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
5022#define CAN_F1R2_FB9_Pos (9U)
5023#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
5024#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
5025#define CAN_F1R2_FB10_Pos (10U)
5026#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
5027#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
5028#define CAN_F1R2_FB11_Pos (11U)
5029#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
5030#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
5031#define CAN_F1R2_FB12_Pos (12U)
5032#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
5033#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
5034#define CAN_F1R2_FB13_Pos (13U)
5035#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
5036#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
5037#define CAN_F1R2_FB14_Pos (14U)
5038#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
5039#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
5040#define CAN_F1R2_FB15_Pos (15U)
5041#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
5042#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
5043#define CAN_F1R2_FB16_Pos (16U)
5044#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
5045#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
5046#define CAN_F1R2_FB17_Pos (17U)
5047#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
5048#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
5049#define CAN_F1R2_FB18_Pos (18U)
5050#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
5051#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
5052#define CAN_F1R2_FB19_Pos (19U)
5053#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
5054#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
5055#define CAN_F1R2_FB20_Pos (20U)
5056#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
5057#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
5058#define CAN_F1R2_FB21_Pos (21U)
5059#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
5060#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
5061#define CAN_F1R2_FB22_Pos (22U)
5062#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
5063#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
5064#define CAN_F1R2_FB23_Pos (23U)
5065#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
5066#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
5067#define CAN_F1R2_FB24_Pos (24U)
5068#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
5069#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
5070#define CAN_F1R2_FB25_Pos (25U)
5071#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
5072#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
5073#define CAN_F1R2_FB26_Pos (26U)
5074#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
5075#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
5076#define CAN_F1R2_FB27_Pos (27U)
5077#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
5078#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
5079#define CAN_F1R2_FB28_Pos (28U)
5080#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
5081#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
5082#define CAN_F1R2_FB29_Pos (29U)
5083#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
5084#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
5085#define CAN_F1R2_FB30_Pos (30U)
5086#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
5087#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
5088#define CAN_F1R2_FB31_Pos (31U)
5089#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
5090#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
5092/******************* Bit definition for CAN_F2R2 register *******************/
5093#define CAN_F2R2_FB0_Pos (0U)
5094#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
5095#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
5096#define CAN_F2R2_FB1_Pos (1U)
5097#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
5098#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
5099#define CAN_F2R2_FB2_Pos (2U)
5100#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
5101#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
5102#define CAN_F2R2_FB3_Pos (3U)
5103#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
5104#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
5105#define CAN_F2R2_FB4_Pos (4U)
5106#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
5107#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
5108#define CAN_F2R2_FB5_Pos (5U)
5109#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
5110#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
5111#define CAN_F2R2_FB6_Pos (6U)
5112#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
5113#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
5114#define CAN_F2R2_FB7_Pos (7U)
5115#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
5116#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
5117#define CAN_F2R2_FB8_Pos (8U)
5118#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
5119#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
5120#define CAN_F2R2_FB9_Pos (9U)
5121#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
5122#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
5123#define CAN_F2R2_FB10_Pos (10U)
5124#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
5125#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
5126#define CAN_F2R2_FB11_Pos (11U)
5127#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
5128#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
5129#define CAN_F2R2_FB12_Pos (12U)
5130#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
5131#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
5132#define CAN_F2R2_FB13_Pos (13U)
5133#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
5134#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
5135#define CAN_F2R2_FB14_Pos (14U)
5136#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
5137#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
5138#define CAN_F2R2_FB15_Pos (15U)
5139#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
5140#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
5141#define CAN_F2R2_FB16_Pos (16U)
5142#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
5143#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
5144#define CAN_F2R2_FB17_Pos (17U)
5145#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
5146#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
5147#define CAN_F2R2_FB18_Pos (18U)
5148#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
5149#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
5150#define CAN_F2R2_FB19_Pos (19U)
5151#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
5152#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
5153#define CAN_F2R2_FB20_Pos (20U)
5154#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
5155#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
5156#define CAN_F2R2_FB21_Pos (21U)
5157#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
5158#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
5159#define CAN_F2R2_FB22_Pos (22U)
5160#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
5161#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
5162#define CAN_F2R2_FB23_Pos (23U)
5163#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
5164#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
5165#define CAN_F2R2_FB24_Pos (24U)
5166#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
5167#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
5168#define CAN_F2R2_FB25_Pos (25U)
5169#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
5170#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
5171#define CAN_F2R2_FB26_Pos (26U)
5172#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
5173#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
5174#define CAN_F2R2_FB27_Pos (27U)
5175#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
5176#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
5177#define CAN_F2R2_FB28_Pos (28U)
5178#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
5179#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
5180#define CAN_F2R2_FB29_Pos (29U)
5181#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
5182#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
5183#define CAN_F2R2_FB30_Pos (30U)
5184#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
5185#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
5186#define CAN_F2R2_FB31_Pos (31U)
5187#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
5188#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
5190/******************* Bit definition for CAN_F3R2 register *******************/
5191#define CAN_F3R2_FB0_Pos (0U)
5192#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
5193#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
5194#define CAN_F3R2_FB1_Pos (1U)
5195#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
5196#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
5197#define CAN_F3R2_FB2_Pos (2U)
5198#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
5199#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
5200#define CAN_F3R2_FB3_Pos (3U)
5201#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
5202#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
5203#define CAN_F3R2_FB4_Pos (4U)
5204#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
5205#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
5206#define CAN_F3R2_FB5_Pos (5U)
5207#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
5208#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
5209#define CAN_F3R2_FB6_Pos (6U)
5210#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
5211#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
5212#define CAN_F3R2_FB7_Pos (7U)
5213#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
5214#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
5215#define CAN_F3R2_FB8_Pos (8U)
5216#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
5217#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
5218#define CAN_F3R2_FB9_Pos (9U)
5219#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
5220#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
5221#define CAN_F3R2_FB10_Pos (10U)
5222#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
5223#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
5224#define CAN_F3R2_FB11_Pos (11U)
5225#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
5226#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
5227#define CAN_F3R2_FB12_Pos (12U)
5228#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
5229#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
5230#define CAN_F3R2_FB13_Pos (13U)
5231#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
5232#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
5233#define CAN_F3R2_FB14_Pos (14U)
5234#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
5235#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
5236#define CAN_F3R2_FB15_Pos (15U)
5237#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
5238#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
5239#define CAN_F3R2_FB16_Pos (16U)
5240#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
5241#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
5242#define CAN_F3R2_FB17_Pos (17U)
5243#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
5244#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
5245#define CAN_F3R2_FB18_Pos (18U)
5246#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
5247#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
5248#define CAN_F3R2_FB19_Pos (19U)
5249#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
5250#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
5251#define CAN_F3R2_FB20_Pos (20U)
5252#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
5253#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
5254#define CAN_F3R2_FB21_Pos (21U)
5255#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
5256#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
5257#define CAN_F3R2_FB22_Pos (22U)
5258#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
5259#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
5260#define CAN_F3R2_FB23_Pos (23U)
5261#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
5262#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
5263#define CAN_F3R2_FB24_Pos (24U)
5264#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
5265#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
5266#define CAN_F3R2_FB25_Pos (25U)
5267#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
5268#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
5269#define CAN_F3R2_FB26_Pos (26U)
5270#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
5271#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
5272#define CAN_F3R2_FB27_Pos (27U)
5273#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
5274#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
5275#define CAN_F3R2_FB28_Pos (28U)
5276#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
5277#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
5278#define CAN_F3R2_FB29_Pos (29U)
5279#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
5280#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
5281#define CAN_F3R2_FB30_Pos (30U)
5282#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
5283#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
5284#define CAN_F3R2_FB31_Pos (31U)
5285#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
5286#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
5288/******************* Bit definition for CAN_F4R2 register *******************/
5289#define CAN_F4R2_FB0_Pos (0U)
5290#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
5291#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
5292#define CAN_F4R2_FB1_Pos (1U)
5293#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
5294#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
5295#define CAN_F4R2_FB2_Pos (2U)
5296#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
5297#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
5298#define CAN_F4R2_FB3_Pos (3U)
5299#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
5300#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
5301#define CAN_F4R2_FB4_Pos (4U)
5302#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
5303#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
5304#define CAN_F4R2_FB5_Pos (5U)
5305#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
5306#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
5307#define CAN_F4R2_FB6_Pos (6U)
5308#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
5309#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
5310#define CAN_F4R2_FB7_Pos (7U)
5311#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
5312#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
5313#define CAN_F4R2_FB8_Pos (8U)
5314#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
5315#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
5316#define CAN_F4R2_FB9_Pos (9U)
5317#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
5318#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
5319#define CAN_F4R2_FB10_Pos (10U)
5320#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
5321#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
5322#define CAN_F4R2_FB11_Pos (11U)
5323#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
5324#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
5325#define CAN_F4R2_FB12_Pos (12U)
5326#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
5327#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
5328#define CAN_F4R2_FB13_Pos (13U)
5329#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
5330#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
5331#define CAN_F4R2_FB14_Pos (14U)
5332#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
5333#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
5334#define CAN_F4R2_FB15_Pos (15U)
5335#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
5336#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
5337#define CAN_F4R2_FB16_Pos (16U)
5338#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
5339#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
5340#define CAN_F4R2_FB17_Pos (17U)
5341#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
5342#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
5343#define CAN_F4R2_FB18_Pos (18U)
5344#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
5345#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
5346#define CAN_F4R2_FB19_Pos (19U)
5347#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
5348#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
5349#define CAN_F4R2_FB20_Pos (20U)
5350#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
5351#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
5352#define CAN_F4R2_FB21_Pos (21U)
5353#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
5354#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
5355#define CAN_F4R2_FB22_Pos (22U)
5356#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
5357#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
5358#define CAN_F4R2_FB23_Pos (23U)
5359#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
5360#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
5361#define CAN_F4R2_FB24_Pos (24U)
5362#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
5363#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
5364#define CAN_F4R2_FB25_Pos (25U)
5365#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
5366#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
5367#define CAN_F4R2_FB26_Pos (26U)
5368#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
5369#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
5370#define CAN_F4R2_FB27_Pos (27U)
5371#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
5372#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
5373#define CAN_F4R2_FB28_Pos (28U)
5374#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
5375#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
5376#define CAN_F4R2_FB29_Pos (29U)
5377#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
5378#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
5379#define CAN_F4R2_FB30_Pos (30U)
5380#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
5381#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
5382#define CAN_F4R2_FB31_Pos (31U)
5383#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
5384#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
5386/******************* Bit definition for CAN_F5R2 register *******************/
5387#define CAN_F5R2_FB0_Pos (0U)
5388#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
5389#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
5390#define CAN_F5R2_FB1_Pos (1U)
5391#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
5392#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
5393#define CAN_F5R2_FB2_Pos (2U)
5394#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
5395#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
5396#define CAN_F5R2_FB3_Pos (3U)
5397#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
5398#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
5399#define CAN_F5R2_FB4_Pos (4U)
5400#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
5401#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
5402#define CAN_F5R2_FB5_Pos (5U)
5403#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
5404#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
5405#define CAN_F5R2_FB6_Pos (6U)
5406#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
5407#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
5408#define CAN_F5R2_FB7_Pos (7U)
5409#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
5410#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
5411#define CAN_F5R2_FB8_Pos (8U)
5412#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
5413#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
5414#define CAN_F5R2_FB9_Pos (9U)
5415#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
5416#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
5417#define CAN_F5R2_FB10_Pos (10U)
5418#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
5419#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
5420#define CAN_F5R2_FB11_Pos (11U)
5421#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
5422#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
5423#define CAN_F5R2_FB12_Pos (12U)
5424#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
5425#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
5426#define CAN_F5R2_FB13_Pos (13U)
5427#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
5428#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
5429#define CAN_F5R2_FB14_Pos (14U)
5430#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
5431#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
5432#define CAN_F5R2_FB15_Pos (15U)
5433#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
5434#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
5435#define CAN_F5R2_FB16_Pos (16U)
5436#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
5437#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
5438#define CAN_F5R2_FB17_Pos (17U)
5439#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
5440#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
5441#define CAN_F5R2_FB18_Pos (18U)
5442#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
5443#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
5444#define CAN_F5R2_FB19_Pos (19U)
5445#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
5446#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
5447#define CAN_F5R2_FB20_Pos (20U)
5448#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
5449#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
5450#define CAN_F5R2_FB21_Pos (21U)
5451#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
5452#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
5453#define CAN_F5R2_FB22_Pos (22U)
5454#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
5455#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
5456#define CAN_F5R2_FB23_Pos (23U)
5457#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
5458#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
5459#define CAN_F5R2_FB24_Pos (24U)
5460#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
5461#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
5462#define CAN_F5R2_FB25_Pos (25U)
5463#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
5464#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
5465#define CAN_F5R2_FB26_Pos (26U)
5466#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
5467#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
5468#define CAN_F5R2_FB27_Pos (27U)
5469#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
5470#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
5471#define CAN_F5R2_FB28_Pos (28U)
5472#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
5473#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
5474#define CAN_F5R2_FB29_Pos (29U)
5475#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
5476#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
5477#define CAN_F5R2_FB30_Pos (30U)
5478#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
5479#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
5480#define CAN_F5R2_FB31_Pos (31U)
5481#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
5482#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
5484/******************* Bit definition for CAN_F6R2 register *******************/
5485#define CAN_F6R2_FB0_Pos (0U)
5486#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
5487#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
5488#define CAN_F6R2_FB1_Pos (1U)
5489#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
5490#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
5491#define CAN_F6R2_FB2_Pos (2U)
5492#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
5493#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
5494#define CAN_F6R2_FB3_Pos (3U)
5495#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
5496#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
5497#define CAN_F6R2_FB4_Pos (4U)
5498#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
5499#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
5500#define CAN_F6R2_FB5_Pos (5U)
5501#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
5502#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
5503#define CAN_F6R2_FB6_Pos (6U)
5504#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
5505#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
5506#define CAN_F6R2_FB7_Pos (7U)
5507#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
5508#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
5509#define CAN_F6R2_FB8_Pos (8U)
5510#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
5511#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
5512#define CAN_F6R2_FB9_Pos (9U)
5513#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
5514#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
5515#define CAN_F6R2_FB10_Pos (10U)
5516#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
5517#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
5518#define CAN_F6R2_FB11_Pos (11U)
5519#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
5520#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
5521#define CAN_F6R2_FB12_Pos (12U)
5522#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
5523#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
5524#define CAN_F6R2_FB13_Pos (13U)
5525#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
5526#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
5527#define CAN_F6R2_FB14_Pos (14U)
5528#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
5529#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
5530#define CAN_F6R2_FB15_Pos (15U)
5531#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
5532#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
5533#define CAN_F6R2_FB16_Pos (16U)
5534#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
5535#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
5536#define CAN_F6R2_FB17_Pos (17U)
5537#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
5538#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
5539#define CAN_F6R2_FB18_Pos (18U)
5540#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
5541#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
5542#define CAN_F6R2_FB19_Pos (19U)
5543#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
5544#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
5545#define CAN_F6R2_FB20_Pos (20U)
5546#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
5547#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
5548#define CAN_F6R2_FB21_Pos (21U)
5549#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
5550#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
5551#define CAN_F6R2_FB22_Pos (22U)
5552#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
5553#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
5554#define CAN_F6R2_FB23_Pos (23U)
5555#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
5556#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
5557#define CAN_F6R2_FB24_Pos (24U)
5558#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
5559#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
5560#define CAN_F6R2_FB25_Pos (25U)
5561#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
5562#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
5563#define CAN_F6R2_FB26_Pos (26U)
5564#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
5565#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
5566#define CAN_F6R2_FB27_Pos (27U)
5567#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
5568#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
5569#define CAN_F6R2_FB28_Pos (28U)
5570#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
5571#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
5572#define CAN_F6R2_FB29_Pos (29U)
5573#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
5574#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
5575#define CAN_F6R2_FB30_Pos (30U)
5576#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
5577#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
5578#define CAN_F6R2_FB31_Pos (31U)
5579#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
5580#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
5582/******************* Bit definition for CAN_F7R2 register *******************/
5583#define CAN_F7R2_FB0_Pos (0U)
5584#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
5585#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
5586#define CAN_F7R2_FB1_Pos (1U)
5587#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
5588#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
5589#define CAN_F7R2_FB2_Pos (2U)
5590#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
5591#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
5592#define CAN_F7R2_FB3_Pos (3U)
5593#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
5594#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
5595#define CAN_F7R2_FB4_Pos (4U)
5596#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
5597#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
5598#define CAN_F7R2_FB5_Pos (5U)
5599#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
5600#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
5601#define CAN_F7R2_FB6_Pos (6U)
5602#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
5603#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
5604#define CAN_F7R2_FB7_Pos (7U)
5605#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
5606#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
5607#define CAN_F7R2_FB8_Pos (8U)
5608#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
5609#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
5610#define CAN_F7R2_FB9_Pos (9U)
5611#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
5612#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
5613#define CAN_F7R2_FB10_Pos (10U)
5614#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
5615#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
5616#define CAN_F7R2_FB11_Pos (11U)
5617#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
5618#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
5619#define CAN_F7R2_FB12_Pos (12U)
5620#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
5621#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
5622#define CAN_F7R2_FB13_Pos (13U)
5623#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
5624#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
5625#define CAN_F7R2_FB14_Pos (14U)
5626#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
5627#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
5628#define CAN_F7R2_FB15_Pos (15U)
5629#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
5630#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
5631#define CAN_F7R2_FB16_Pos (16U)
5632#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
5633#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
5634#define CAN_F7R2_FB17_Pos (17U)
5635#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
5636#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
5637#define CAN_F7R2_FB18_Pos (18U)
5638#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
5639#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
5640#define CAN_F7R2_FB19_Pos (19U)
5641#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
5642#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
5643#define CAN_F7R2_FB20_Pos (20U)
5644#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
5645#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
5646#define CAN_F7R2_FB21_Pos (21U)
5647#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
5648#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
5649#define CAN_F7R2_FB22_Pos (22U)
5650#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
5651#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
5652#define CAN_F7R2_FB23_Pos (23U)
5653#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
5654#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
5655#define CAN_F7R2_FB24_Pos (24U)
5656#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
5657#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
5658#define CAN_F7R2_FB25_Pos (25U)
5659#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
5660#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
5661#define CAN_F7R2_FB26_Pos (26U)
5662#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
5663#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
5664#define CAN_F7R2_FB27_Pos (27U)
5665#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
5666#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
5667#define CAN_F7R2_FB28_Pos (28U)
5668#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
5669#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
5670#define CAN_F7R2_FB29_Pos (29U)
5671#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
5672#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
5673#define CAN_F7R2_FB30_Pos (30U)
5674#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
5675#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
5676#define CAN_F7R2_FB31_Pos (31U)
5677#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
5678#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
5680/******************* Bit definition for CAN_F8R2 register *******************/
5681#define CAN_F8R2_FB0_Pos (0U)
5682#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
5683#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
5684#define CAN_F8R2_FB1_Pos (1U)
5685#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
5686#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
5687#define CAN_F8R2_FB2_Pos (2U)
5688#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
5689#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
5690#define CAN_F8R2_FB3_Pos (3U)
5691#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
5692#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
5693#define CAN_F8R2_FB4_Pos (4U)
5694#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
5695#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
5696#define CAN_F8R2_FB5_Pos (5U)
5697#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
5698#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
5699#define CAN_F8R2_FB6_Pos (6U)
5700#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
5701#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
5702#define CAN_F8R2_FB7_Pos (7U)
5703#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
5704#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
5705#define CAN_F8R2_FB8_Pos (8U)
5706#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
5707#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
5708#define CAN_F8R2_FB9_Pos (9U)
5709#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
5710#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
5711#define CAN_F8R2_FB10_Pos (10U)
5712#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
5713#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
5714#define CAN_F8R2_FB11_Pos (11U)
5715#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
5716#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
5717#define CAN_F8R2_FB12_Pos (12U)
5718#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
5719#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
5720#define CAN_F8R2_FB13_Pos (13U)
5721#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
5722#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
5723#define CAN_F8R2_FB14_Pos (14U)
5724#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
5725#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
5726#define CAN_F8R2_FB15_Pos (15U)
5727#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
5728#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
5729#define CAN_F8R2_FB16_Pos (16U)
5730#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
5731#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
5732#define CAN_F8R2_FB17_Pos (17U)
5733#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
5734#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
5735#define CAN_F8R2_FB18_Pos (18U)
5736#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
5737#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
5738#define CAN_F8R2_FB19_Pos (19U)
5739#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
5740#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
5741#define CAN_F8R2_FB20_Pos (20U)
5742#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
5743#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
5744#define CAN_F8R2_FB21_Pos (21U)
5745#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
5746#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
5747#define CAN_F8R2_FB22_Pos (22U)
5748#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
5749#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
5750#define CAN_F8R2_FB23_Pos (23U)
5751#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
5752#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
5753#define CAN_F8R2_FB24_Pos (24U)
5754#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
5755#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
5756#define CAN_F8R2_FB25_Pos (25U)
5757#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
5758#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
5759#define CAN_F8R2_FB26_Pos (26U)
5760#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
5761#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
5762#define CAN_F8R2_FB27_Pos (27U)
5763#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
5764#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
5765#define CAN_F8R2_FB28_Pos (28U)
5766#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
5767#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
5768#define CAN_F8R2_FB29_Pos (29U)
5769#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
5770#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
5771#define CAN_F8R2_FB30_Pos (30U)
5772#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
5773#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
5774#define CAN_F8R2_FB31_Pos (31U)
5775#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
5776#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
5778/******************* Bit definition for CAN_F9R2 register *******************/
5779#define CAN_F9R2_FB0_Pos (0U)
5780#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
5781#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
5782#define CAN_F9R2_FB1_Pos (1U)
5783#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
5784#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
5785#define CAN_F9R2_FB2_Pos (2U)
5786#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
5787#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
5788#define CAN_F9R2_FB3_Pos (3U)
5789#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
5790#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
5791#define CAN_F9R2_FB4_Pos (4U)
5792#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
5793#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
5794#define CAN_F9R2_FB5_Pos (5U)
5795#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
5796#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
5797#define CAN_F9R2_FB6_Pos (6U)
5798#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
5799#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
5800#define CAN_F9R2_FB7_Pos (7U)
5801#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
5802#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
5803#define CAN_F9R2_FB8_Pos (8U)
5804#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
5805#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
5806#define CAN_F9R2_FB9_Pos (9U)
5807#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
5808#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
5809#define CAN_F9R2_FB10_Pos (10U)
5810#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
5811#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
5812#define CAN_F9R2_FB11_Pos (11U)
5813#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
5814#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
5815#define CAN_F9R2_FB12_Pos (12U)
5816#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
5817#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
5818#define CAN_F9R2_FB13_Pos (13U)
5819#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
5820#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
5821#define CAN_F9R2_FB14_Pos (14U)
5822#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
5823#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
5824#define CAN_F9R2_FB15_Pos (15U)
5825#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
5826#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
5827#define CAN_F9R2_FB16_Pos (16U)
5828#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
5829#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
5830#define CAN_F9R2_FB17_Pos (17U)
5831#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
5832#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
5833#define CAN_F9R2_FB18_Pos (18U)
5834#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
5835#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
5836#define CAN_F9R2_FB19_Pos (19U)
5837#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
5838#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
5839#define CAN_F9R2_FB20_Pos (20U)
5840#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
5841#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
5842#define CAN_F9R2_FB21_Pos (21U)
5843#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
5844#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
5845#define CAN_F9R2_FB22_Pos (22U)
5846#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
5847#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
5848#define CAN_F9R2_FB23_Pos (23U)
5849#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
5850#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
5851#define CAN_F9R2_FB24_Pos (24U)
5852#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
5853#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5854#define CAN_F9R2_FB25_Pos (25U)
5855#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5856#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5857#define CAN_F9R2_FB26_Pos (26U)
5858#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5859#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5860#define CAN_F9R2_FB27_Pos (27U)
5861#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5862#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5863#define CAN_F9R2_FB28_Pos (28U)
5864#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5865#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5866#define CAN_F9R2_FB29_Pos (29U)
5867#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5868#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5869#define CAN_F9R2_FB30_Pos (30U)
5870#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5871#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5872#define CAN_F9R2_FB31_Pos (31U)
5873#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5874#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5876/******************* Bit definition for CAN_F10R2 register ******************/
5877#define CAN_F10R2_FB0_Pos (0U)
5878#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5879#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5880#define CAN_F10R2_FB1_Pos (1U)
5881#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5882#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5883#define CAN_F10R2_FB2_Pos (2U)
5884#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5885#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5886#define CAN_F10R2_FB3_Pos (3U)
5887#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5888#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5889#define CAN_F10R2_FB4_Pos (4U)
5890#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5891#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5892#define CAN_F10R2_FB5_Pos (5U)
5893#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5894#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5895#define CAN_F10R2_FB6_Pos (6U)
5896#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5897#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5898#define CAN_F10R2_FB7_Pos (7U)
5899#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5900#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5901#define CAN_F10R2_FB8_Pos (8U)
5902#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5903#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5904#define CAN_F10R2_FB9_Pos (9U)
5905#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5906#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5907#define CAN_F10R2_FB10_Pos (10U)
5908#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5909#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5910#define CAN_F10R2_FB11_Pos (11U)
5911#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5912#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5913#define CAN_F10R2_FB12_Pos (12U)
5914#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5915#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5916#define CAN_F10R2_FB13_Pos (13U)
5917#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5918#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5919#define CAN_F10R2_FB14_Pos (14U)
5920#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5921#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5922#define CAN_F10R2_FB15_Pos (15U)
5923#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5924#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5925#define CAN_F10R2_FB16_Pos (16U)
5926#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5927#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5928#define CAN_F10R2_FB17_Pos (17U)
5929#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5930#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5931#define CAN_F10R2_FB18_Pos (18U)
5932#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5933#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5934#define CAN_F10R2_FB19_Pos (19U)
5935#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5936#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5937#define CAN_F10R2_FB20_Pos (20U)
5938#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5939#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5940#define CAN_F10R2_FB21_Pos (21U)
5941#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5942#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5943#define CAN_F10R2_FB22_Pos (22U)
5944#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5945#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5946#define CAN_F10R2_FB23_Pos (23U)
5947#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5948#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5949#define CAN_F10R2_FB24_Pos (24U)
5950#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5951#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5952#define CAN_F10R2_FB25_Pos (25U)
5953#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5954#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5955#define CAN_F10R2_FB26_Pos (26U)
5956#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5957#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5958#define CAN_F10R2_FB27_Pos (27U)
5959#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5960#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5961#define CAN_F10R2_FB28_Pos (28U)
5962#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5963#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5964#define CAN_F10R2_FB29_Pos (29U)
5965#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5966#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5967#define CAN_F10R2_FB30_Pos (30U)
5968#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5969#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5970#define CAN_F10R2_FB31_Pos (31U)
5971#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5972#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5974/******************* Bit definition for CAN_F11R2 register ******************/
5975#define CAN_F11R2_FB0_Pos (0U)
5976#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5977#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5978#define CAN_F11R2_FB1_Pos (1U)
5979#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5980#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5981#define CAN_F11R2_FB2_Pos (2U)
5982#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5983#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5984#define CAN_F11R2_FB3_Pos (3U)
5985#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5986#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5987#define CAN_F11R2_FB4_Pos (4U)
5988#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5989#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5990#define CAN_F11R2_FB5_Pos (5U)
5991#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5992#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5993#define CAN_F11R2_FB6_Pos (6U)
5994#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5995#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5996#define CAN_F11R2_FB7_Pos (7U)
5997#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5998#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5999#define CAN_F11R2_FB8_Pos (8U)
6000#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
6001#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
6002#define CAN_F11R2_FB9_Pos (9U)
6003#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
6004#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
6005#define CAN_F11R2_FB10_Pos (10U)
6006#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
6007#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
6008#define CAN_F11R2_FB11_Pos (11U)
6009#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
6010#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
6011#define CAN_F11R2_FB12_Pos (12U)
6012#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
6013#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
6014#define CAN_F11R2_FB13_Pos (13U)
6015#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
6016#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
6017#define CAN_F11R2_FB14_Pos (14U)
6018#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
6019#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
6020#define CAN_F11R2_FB15_Pos (15U)
6021#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
6022#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
6023#define CAN_F11R2_FB16_Pos (16U)
6024#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
6025#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
6026#define CAN_F11R2_FB17_Pos (17U)
6027#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
6028#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
6029#define CAN_F11R2_FB18_Pos (18U)
6030#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
6031#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
6032#define CAN_F11R2_FB19_Pos (19U)
6033#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
6034#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
6035#define CAN_F11R2_FB20_Pos (20U)
6036#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
6037#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
6038#define CAN_F11R2_FB21_Pos (21U)
6039#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
6040#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
6041#define CAN_F11R2_FB22_Pos (22U)
6042#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
6043#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
6044#define CAN_F11R2_FB23_Pos (23U)
6045#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
6046#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
6047#define CAN_F11R2_FB24_Pos (24U)
6048#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
6049#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
6050#define CAN_F11R2_FB25_Pos (25U)
6051#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
6052#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
6053#define CAN_F11R2_FB26_Pos (26U)
6054#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
6055#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
6056#define CAN_F11R2_FB27_Pos (27U)
6057#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
6058#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
6059#define CAN_F11R2_FB28_Pos (28U)
6060#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
6061#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
6062#define CAN_F11R2_FB29_Pos (29U)
6063#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
6064#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
6065#define CAN_F11R2_FB30_Pos (30U)
6066#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
6067#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
6068#define CAN_F11R2_FB31_Pos (31U)
6069#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
6070#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
6072/******************* Bit definition for CAN_F12R2 register ******************/
6073#define CAN_F12R2_FB0_Pos (0U)
6074#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
6075#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
6076#define CAN_F12R2_FB1_Pos (1U)
6077#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
6078#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
6079#define CAN_F12R2_FB2_Pos (2U)
6080#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
6081#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
6082#define CAN_F12R2_FB3_Pos (3U)
6083#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
6084#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
6085#define CAN_F12R2_FB4_Pos (4U)
6086#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
6087#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
6088#define CAN_F12R2_FB5_Pos (5U)
6089#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
6090#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
6091#define CAN_F12R2_FB6_Pos (6U)
6092#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
6093#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
6094#define CAN_F12R2_FB7_Pos (7U)
6095#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
6096#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
6097#define CAN_F12R2_FB8_Pos (8U)
6098#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
6099#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
6100#define CAN_F12R2_FB9_Pos (9U)
6101#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
6102#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
6103#define CAN_F12R2_FB10_Pos (10U)
6104#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
6105#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
6106#define CAN_F12R2_FB11_Pos (11U)
6107#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
6108#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
6109#define CAN_F12R2_FB12_Pos (12U)
6110#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
6111#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
6112#define CAN_F12R2_FB13_Pos (13U)
6113#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
6114#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
6115#define CAN_F12R2_FB14_Pos (14U)
6116#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
6117#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
6118#define CAN_F12R2_FB15_Pos (15U)
6119#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
6120#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
6121#define CAN_F12R2_FB16_Pos (16U)
6122#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
6123#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
6124#define CAN_F12R2_FB17_Pos (17U)
6125#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
6126#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
6127#define CAN_F12R2_FB18_Pos (18U)
6128#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
6129#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
6130#define CAN_F12R2_FB19_Pos (19U)
6131#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
6132#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
6133#define CAN_F12R2_FB20_Pos (20U)
6134#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
6135#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
6136#define CAN_F12R2_FB21_Pos (21U)
6137#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
6138#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
6139#define CAN_F12R2_FB22_Pos (22U)
6140#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
6141#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
6142#define CAN_F12R2_FB23_Pos (23U)
6143#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
6144#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
6145#define CAN_F12R2_FB24_Pos (24U)
6146#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
6147#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
6148#define CAN_F12R2_FB25_Pos (25U)
6149#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
6150#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
6151#define CAN_F12R2_FB26_Pos (26U)
6152#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
6153#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
6154#define CAN_F12R2_FB27_Pos (27U)
6155#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
6156#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
6157#define CAN_F12R2_FB28_Pos (28U)
6158#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
6159#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
6160#define CAN_F12R2_FB29_Pos (29U)
6161#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
6162#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
6163#define CAN_F12R2_FB30_Pos (30U)
6164#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
6165#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
6166#define CAN_F12R2_FB31_Pos (31U)
6167#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
6168#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
6170/******************* Bit definition for CAN_F13R2 register ******************/
6171#define CAN_F13R2_FB0_Pos (0U)
6172#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
6173#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
6174#define CAN_F13R2_FB1_Pos (1U)
6175#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
6176#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
6177#define CAN_F13R2_FB2_Pos (2U)
6178#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
6179#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
6180#define CAN_F13R2_FB3_Pos (3U)
6181#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
6182#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
6183#define CAN_F13R2_FB4_Pos (4U)
6184#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
6185#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
6186#define CAN_F13R2_FB5_Pos (5U)
6187#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
6188#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
6189#define CAN_F13R2_FB6_Pos (6U)
6190#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
6191#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
6192#define CAN_F13R2_FB7_Pos (7U)
6193#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
6194#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
6195#define CAN_F13R2_FB8_Pos (8U)
6196#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
6197#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
6198#define CAN_F13R2_FB9_Pos (9U)
6199#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
6200#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
6201#define CAN_F13R2_FB10_Pos (10U)
6202#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
6203#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
6204#define CAN_F13R2_FB11_Pos (11U)
6205#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
6206#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
6207#define CAN_F13R2_FB12_Pos (12U)
6208#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
6209#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
6210#define CAN_F13R2_FB13_Pos (13U)
6211#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
6212#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
6213#define CAN_F13R2_FB14_Pos (14U)
6214#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
6215#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
6216#define CAN_F13R2_FB15_Pos (15U)
6217#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
6218#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
6219#define CAN_F13R2_FB16_Pos (16U)
6220#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
6221#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
6222#define CAN_F13R2_FB17_Pos (17U)
6223#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
6224#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
6225#define CAN_F13R2_FB18_Pos (18U)
6226#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
6227#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
6228#define CAN_F13R2_FB19_Pos (19U)
6229#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
6230#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
6231#define CAN_F13R2_FB20_Pos (20U)
6232#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
6233#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
6234#define CAN_F13R2_FB21_Pos (21U)
6235#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
6236#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
6237#define CAN_F13R2_FB22_Pos (22U)
6238#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
6239#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
6240#define CAN_F13R2_FB23_Pos (23U)
6241#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
6242#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
6243#define CAN_F13R2_FB24_Pos (24U)
6244#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
6245#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
6246#define CAN_F13R2_FB25_Pos (25U)
6247#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
6248#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
6249#define CAN_F13R2_FB26_Pos (26U)
6250#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
6251#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
6252#define CAN_F13R2_FB27_Pos (27U)
6253#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
6254#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
6255#define CAN_F13R2_FB28_Pos (28U)
6256#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
6257#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
6258#define CAN_F13R2_FB29_Pos (29U)
6259#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
6260#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
6261#define CAN_F13R2_FB30_Pos (30U)
6262#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
6263#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
6264#define CAN_F13R2_FB31_Pos (31U)
6265#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
6266#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
6268/******************************************************************************/
6269/* */
6270/* CRC calculation unit */
6271/* */
6272/******************************************************************************/
6273/******************* Bit definition for CRC_DR register *********************/
6274#define CRC_DR_DR_Pos (0U)
6275#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
6276#define CRC_DR_DR CRC_DR_DR_Msk
6278/******************* Bit definition for CRC_IDR register ********************/
6279#define CRC_IDR_IDR_Pos (0U)
6280#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos)
6281#define CRC_IDR_IDR CRC_IDR_IDR_Msk
6283/******************** Bit definition for CRC_CR register ********************/
6284#define CRC_CR_RESET_Pos (0U)
6285#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
6286#define CRC_CR_RESET CRC_CR_RESET_Msk
6287#define CRC_CR_POLYSIZE_Pos (3U)
6288#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
6289#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
6290#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
6291#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
6292#define CRC_CR_REV_IN_Pos (5U)
6293#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
6294#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
6295#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
6296#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
6297#define CRC_CR_REV_OUT_Pos (7U)
6298#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
6299#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
6301/******************* Bit definition for CRC_INIT register *******************/
6302#define CRC_INIT_INIT_Pos (0U)
6303#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
6304#define CRC_INIT_INIT CRC_INIT_INIT_Msk
6306/******************* Bit definition for CRC_POL register ********************/
6307#define CRC_POL_POL_Pos (0U)
6308#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
6309#define CRC_POL_POL CRC_POL_POL_Msk
6311/******************************************************************************/
6312/* */
6313/* CRS Clock Recovery System */
6314/******************************************************************************/
6315
6316/******************* Bit definition for CRS_CR register *********************/
6317#define CRS_CR_SYNCOKIE_Pos (0U)
6318#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos)
6319#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk
6320#define CRS_CR_SYNCWARNIE_Pos (1U)
6321#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos)
6322#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk
6323#define CRS_CR_ERRIE_Pos (2U)
6324#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos)
6325#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk
6326#define CRS_CR_ESYNCIE_Pos (3U)
6327#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos)
6328#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk
6329#define CRS_CR_CEN_Pos (5U)
6330#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos)
6331#define CRS_CR_CEN CRS_CR_CEN_Msk
6332#define CRS_CR_AUTOTRIMEN_Pos (6U)
6333#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos)
6334#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk
6335#define CRS_CR_SWSYNC_Pos (7U)
6336#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos)
6337#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk
6338#define CRS_CR_TRIM_Pos (8U)
6339#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos)
6340#define CRS_CR_TRIM CRS_CR_TRIM_Msk
6341#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos)
6342#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos)
6343#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos)
6344#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos)
6345#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos)
6346#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos)
6348/******************* Bit definition for CRS_CFGR register *********************/
6349#define CRS_CFGR_RELOAD_Pos (0U)
6350#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos)
6351#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk
6352#define CRS_CFGR_FELIM_Pos (16U)
6353#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos)
6354#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk
6356#define CRS_CFGR_SYNCDIV_Pos (24U)
6357#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos)
6358#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk
6359#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos)
6360#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos)
6361#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos)
6363#define CRS_CFGR_SYNCSRC_Pos (28U)
6364#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos)
6365#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk
6366#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos)
6367#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos)
6369#define CRS_CFGR_SYNCPOL_Pos (31U)
6370#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos)
6371#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk
6373/******************* Bit definition for CRS_ISR register *********************/
6374#define CRS_ISR_SYNCOKF_Pos (0U)
6375#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos)
6376#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk
6377#define CRS_ISR_SYNCWARNF_Pos (1U)
6378#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos)
6379#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk
6380#define CRS_ISR_ERRF_Pos (2U)
6381#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos)
6382#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk
6383#define CRS_ISR_ESYNCF_Pos (3U)
6384#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos)
6385#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk
6386#define CRS_ISR_SYNCERR_Pos (8U)
6387#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos)
6388#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk
6389#define CRS_ISR_SYNCMISS_Pos (9U)
6390#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos)
6391#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk
6392#define CRS_ISR_TRIMOVF_Pos (10U)
6393#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos)
6394#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk
6395#define CRS_ISR_FEDIR_Pos (15U)
6396#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos)
6397#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk
6398#define CRS_ISR_FECAP_Pos (16U)
6399#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos)
6400#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk
6402/******************* Bit definition for CRS_ICR register *********************/
6403#define CRS_ICR_SYNCOKC_Pos (0U)
6404#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos)
6405#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk
6406#define CRS_ICR_SYNCWARNC_Pos (1U)
6407#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos)
6408#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk
6409#define CRS_ICR_ERRC_Pos (2U)
6410#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos)
6411#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk
6412#define CRS_ICR_ESYNCC_Pos (3U)
6413#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos)
6414#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk
6416/******************************************************************************/
6417/* */
6418/* Advanced Encryption Standard (AES) */
6419/* */
6420/******************************************************************************/
6421/******************* Bit definition for AES_CR register *********************/
6422#define AES_CR_EN_Pos (0U)
6423#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos)
6424#define AES_CR_EN AES_CR_EN_Msk
6425#define AES_CR_DATATYPE_Pos (1U)
6426#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos)
6427#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk
6428#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos)
6429#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos)
6431#define AES_CR_MODE_Pos (3U)
6432#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos)
6433#define AES_CR_MODE AES_CR_MODE_Msk
6434#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos)
6435#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos)
6437#define AES_CR_CHMOD_Pos (5U)
6438#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos)
6439#define AES_CR_CHMOD AES_CR_CHMOD_Msk
6440#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos)
6441#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos)
6442#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos)
6444#define AES_CR_CCFC_Pos (7U)
6445#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos)
6446#define AES_CR_CCFC AES_CR_CCFC_Msk
6447#define AES_CR_ERRC_Pos (8U)
6448#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos)
6449#define AES_CR_ERRC AES_CR_ERRC_Msk
6450#define AES_CR_CCFIE_Pos (9U)
6451#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos)
6452#define AES_CR_CCFIE AES_CR_CCFIE_Msk
6453#define AES_CR_ERRIE_Pos (10U)
6454#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos)
6455#define AES_CR_ERRIE AES_CR_ERRIE_Msk
6456#define AES_CR_DMAINEN_Pos (11U)
6457#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos)
6458#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk
6459#define AES_CR_DMAOUTEN_Pos (12U)
6460#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos)
6461#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk
6463#define AES_CR_GCMPH_Pos (13U)
6464#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos)
6465#define AES_CR_GCMPH AES_CR_GCMPH_Msk
6466#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos)
6467#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos)
6469#define AES_CR_KEYSIZE_Pos (18U)
6470#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos)
6471#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk
6473/******************* Bit definition for AES_SR register *********************/
6474#define AES_SR_CCF_Pos (0U)
6475#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos)
6476#define AES_SR_CCF AES_SR_CCF_Msk
6477#define AES_SR_RDERR_Pos (1U)
6478#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos)
6479#define AES_SR_RDERR AES_SR_RDERR_Msk
6480#define AES_SR_WRERR_Pos (2U)
6481#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos)
6482#define AES_SR_WRERR AES_SR_WRERR_Msk
6483#define AES_SR_BUSY_Pos (3U)
6484#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos)
6485#define AES_SR_BUSY AES_SR_BUSY_Msk
6487/******************* Bit definition for AES_DINR register *******************/
6488#define AES_DINR_Pos (0U)
6489#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos)
6490#define AES_DINR AES_DINR_Msk
6492/******************* Bit definition for AES_DOUTR register ******************/
6493#define AES_DOUTR_Pos (0U)
6494#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos)
6495#define AES_DOUTR AES_DOUTR_Msk
6497/******************* Bit definition for AES_KEYR0 register ******************/
6498#define AES_KEYR0_Pos (0U)
6499#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos)
6500#define AES_KEYR0 AES_KEYR0_Msk
6502/******************* Bit definition for AES_KEYR1 register ******************/
6503#define AES_KEYR1_Pos (0U)
6504#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos)
6505#define AES_KEYR1 AES_KEYR1_Msk
6507/******************* Bit definition for AES_KEYR2 register ******************/
6508#define AES_KEYR2_Pos (0U)
6509#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos)
6510#define AES_KEYR2 AES_KEYR2_Msk
6512/******************* Bit definition for AES_KEYR3 register ******************/
6513#define AES_KEYR3_Pos (0U)
6514#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos)
6515#define AES_KEYR3 AES_KEYR3_Msk
6517/******************* Bit definition for AES_KEYR4 register ******************/
6518#define AES_KEYR4_Pos (0U)
6519#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos)
6520#define AES_KEYR4 AES_KEYR4_Msk
6522/******************* Bit definition for AES_KEYR5 register ******************/
6523#define AES_KEYR5_Pos (0U)
6524#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos)
6525#define AES_KEYR5 AES_KEYR5_Msk
6527/******************* Bit definition for AES_KEYR6 register ******************/
6528#define AES_KEYR6_Pos (0U)
6529#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos)
6530#define AES_KEYR6 AES_KEYR6_Msk
6532/******************* Bit definition for AES_KEYR7 register ******************/
6533#define AES_KEYR7_Pos (0U)
6534#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos)
6535#define AES_KEYR7 AES_KEYR7_Msk
6537/******************* Bit definition for AES_IVR0 register ******************/
6538#define AES_IVR0_Pos (0U)
6539#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos)
6540#define AES_IVR0 AES_IVR0_Msk
6542/******************* Bit definition for AES_IVR1 register ******************/
6543#define AES_IVR1_Pos (0U)
6544#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos)
6545#define AES_IVR1 AES_IVR1_Msk
6547/******************* Bit definition for AES_IVR2 register ******************/
6548#define AES_IVR2_Pos (0U)
6549#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos)
6550#define AES_IVR2 AES_IVR2_Msk
6552/******************* Bit definition for AES_IVR3 register ******************/
6553#define AES_IVR3_Pos (0U)
6554#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos)
6555#define AES_IVR3 AES_IVR3_Msk
6557/******************* Bit definition for AES_SUSP0R register ******************/
6558#define AES_SUSP0R_Pos (0U)
6559#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos)
6560#define AES_SUSP0R AES_SUSP0R_Msk
6562/******************* Bit definition for AES_SUSP1R register ******************/
6563#define AES_SUSP1R_Pos (0U)
6564#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos)
6565#define AES_SUSP1R AES_SUSP1R_Msk
6567/******************* Bit definition for AES_SUSP2R register ******************/
6568#define AES_SUSP2R_Pos (0U)
6569#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos)
6570#define AES_SUSP2R AES_SUSP2R_Msk
6572/******************* Bit definition for AES_SUSP3R register ******************/
6573#define AES_SUSP3R_Pos (0U)
6574#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos)
6575#define AES_SUSP3R AES_SUSP3R_Msk
6577/******************* Bit definition for AES_SUSP4R register ******************/
6578#define AES_SUSP4R_Pos (0U)
6579#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos)
6580#define AES_SUSP4R AES_SUSP4R_Msk
6582/******************* Bit definition for AES_SUSP5R register ******************/
6583#define AES_SUSP5R_Pos (0U)
6584#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos)
6585#define AES_SUSP5R AES_SUSP5R_Msk
6587/******************* Bit definition for AES_SUSP6R register ******************/
6588#define AES_SUSP6R_Pos (0U)
6589#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos)
6590#define AES_SUSP6R AES_SUSP6R_Msk
6592/******************* Bit definition for AES_SUSP7R register ******************/
6593#define AES_SUSP7R_Pos (0U)
6594#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos)
6595#define AES_SUSP7R AES_SUSP7R_Msk
6597/******************************************************************************/
6598/* */
6599/* Digital to Analog Converter */
6600/* */
6601/******************************************************************************/
6602/*
6603 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
6604 */
6605#define DAC_CHANNEL2_SUPPORT
6607/******************** Bit definition for DAC_CR register ********************/
6608#define DAC_CR_EN1_Pos (0U)
6609#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
6610#define DAC_CR_EN1 DAC_CR_EN1_Msk
6611#define DAC_CR_TEN1_Pos (2U)
6612#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
6613#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
6615#define DAC_CR_TSEL1_Pos (3U)
6616#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
6617#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
6618#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
6619#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
6620#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
6622#define DAC_CR_WAVE1_Pos (6U)
6623#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
6624#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
6625#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
6626#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
6628#define DAC_CR_MAMP1_Pos (8U)
6629#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
6630#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
6631#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
6632#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
6633#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
6634#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
6636#define DAC_CR_DMAEN1_Pos (12U)
6637#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
6638#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
6639#define DAC_CR_DMAUDRIE1_Pos (13U)
6640#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
6641#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
6642#define DAC_CR_CEN1_Pos (14U)
6643#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos)
6644#define DAC_CR_CEN1 DAC_CR_CEN1_Msk
6646#define DAC_CR_EN2_Pos (16U)
6647#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
6648#define DAC_CR_EN2 DAC_CR_EN2_Msk
6649#define DAC_CR_TEN2_Pos (18U)
6650#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
6651#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
6653#define DAC_CR_TSEL2_Pos (19U)
6654#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
6655#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
6656#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
6657#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
6658#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
6660#define DAC_CR_WAVE2_Pos (22U)
6661#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
6662#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
6663#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
6664#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
6666#define DAC_CR_MAMP2_Pos (24U)
6667#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
6668#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
6669#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
6670#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
6671#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
6672#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
6674#define DAC_CR_DMAEN2_Pos (28U)
6675#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
6676#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
6677#define DAC_CR_DMAUDRIE2_Pos (29U)
6678#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
6679#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
6680#define DAC_CR_CEN2_Pos (30U)
6681#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos)
6682#define DAC_CR_CEN2 DAC_CR_CEN2_Msk
6684/***************** Bit definition for DAC_SWTRIGR register ******************/
6685#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
6686#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
6687#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
6688#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
6689#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
6690#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
6692/***************** Bit definition for DAC_DHR12R1 register ******************/
6693#define DAC_DHR12R1_DACC1DHR_Pos (0U)
6694#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
6695#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
6697/***************** Bit definition for DAC_DHR12L1 register ******************/
6698#define DAC_DHR12L1_DACC1DHR_Pos (4U)
6699#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
6700#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
6702/****************** Bit definition for DAC_DHR8R1 register ******************/
6703#define DAC_DHR8R1_DACC1DHR_Pos (0U)
6704#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
6705#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
6707/***************** Bit definition for DAC_DHR12R2 register ******************/
6708#define DAC_DHR12R2_DACC2DHR_Pos (0U)
6709#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
6710#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
6712/***************** Bit definition for DAC_DHR12L2 register ******************/
6713#define DAC_DHR12L2_DACC2DHR_Pos (4U)
6714#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
6715#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
6717/****************** Bit definition for DAC_DHR8R2 register ******************/
6718#define DAC_DHR8R2_DACC2DHR_Pos (0U)
6719#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
6720#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
6722/***************** Bit definition for DAC_DHR12RD register ******************/
6723#define DAC_DHR12RD_DACC1DHR_Pos (0U)
6724#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
6725#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
6726#define DAC_DHR12RD_DACC2DHR_Pos (16U)
6727#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
6728#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
6730/***************** Bit definition for DAC_DHR12LD register ******************/
6731#define DAC_DHR12LD_DACC1DHR_Pos (4U)
6732#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
6733#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
6734#define DAC_DHR12LD_DACC2DHR_Pos (20U)
6735#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
6736#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
6738/****************** Bit definition for DAC_DHR8RD register ******************/
6739#define DAC_DHR8RD_DACC1DHR_Pos (0U)
6740#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
6741#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
6742#define DAC_DHR8RD_DACC2DHR_Pos (8U)
6743#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
6744#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
6746/******************* Bit definition for DAC_DOR1 register *******************/
6747#define DAC_DOR1_DACC1DOR_Pos (0U)
6748#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
6749#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
6751/******************* Bit definition for DAC_DOR2 register *******************/
6752#define DAC_DOR2_DACC2DOR_Pos (0U)
6753#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
6754#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
6756/******************** Bit definition for DAC_SR register ********************/
6757#define DAC_SR_DMAUDR1_Pos (13U)
6758#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
6759#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
6760#define DAC_SR_CAL_FLAG1_Pos (14U)
6761#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos)
6762#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk
6763#define DAC_SR_BWST1_Pos (15U)
6764#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos)
6765#define DAC_SR_BWST1 DAC_SR_BWST1_Msk
6767#define DAC_SR_DMAUDR2_Pos (29U)
6768#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
6769#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
6770#define DAC_SR_CAL_FLAG2_Pos (30U)
6771#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos)
6772#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk
6773#define DAC_SR_BWST2_Pos (31U)
6774#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos)
6775#define DAC_SR_BWST2 DAC_SR_BWST2_Msk
6777/******************* Bit definition for DAC_CCR register ********************/
6778#define DAC_CCR_OTRIM1_Pos (0U)
6779#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos)
6780#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk
6781#define DAC_CCR_OTRIM2_Pos (16U)
6782#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos)
6783#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk
6785/******************* Bit definition for DAC_MCR register *******************/
6786#define DAC_MCR_MODE1_Pos (0U)
6787#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos)
6788#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk
6789#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos)
6790#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos)
6791#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos)
6793#define DAC_MCR_MODE2_Pos (16U)
6794#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos)
6795#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk
6796#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos)
6797#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos)
6798#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos)
6800/****************** Bit definition for DAC_SHSR1 register ******************/
6801#define DAC_SHSR1_TSAMPLE1_Pos (0U)
6802#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)
6803#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk
6805/****************** Bit definition for DAC_SHSR2 register ******************/
6806#define DAC_SHSR2_TSAMPLE2_Pos (0U)
6807#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)
6808#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk
6810/****************** Bit definition for DAC_SHHR register ******************/
6811#define DAC_SHHR_THOLD1_Pos (0U)
6812#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos)
6813#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk
6814#define DAC_SHHR_THOLD2_Pos (16U)
6815#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos)
6816#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk
6818/****************** Bit definition for DAC_SHRR register ******************/
6819#define DAC_SHRR_TREFRESH1_Pos (0U)
6820#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos)
6821#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk
6822#define DAC_SHRR_TREFRESH2_Pos (16U)
6823#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos)
6824#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk
6826/******************************************************************************/
6827/* */
6828/* DCMI */
6829/* */
6830/******************************************************************************/
6831/******************** Bits definition for DCMI_CR register ******************/
6832#define DCMI_CR_CAPTURE_Pos (0U)
6833#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
6834#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
6835#define DCMI_CR_CM_Pos (1U)
6836#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
6837#define DCMI_CR_CM DCMI_CR_CM_Msk
6838#define DCMI_CR_CROP_Pos (2U)
6839#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
6840#define DCMI_CR_CROP DCMI_CR_CROP_Msk
6841#define DCMI_CR_JPEG_Pos (3U)
6842#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
6843#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
6844#define DCMI_CR_ESS_Pos (4U)
6845#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
6846#define DCMI_CR_ESS DCMI_CR_ESS_Msk
6847#define DCMI_CR_PCKPOL_Pos (5U)
6848#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
6849#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
6850#define DCMI_CR_HSPOL_Pos (6U)
6851#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
6852#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
6853#define DCMI_CR_VSPOL_Pos (7U)
6854#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
6855#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
6856#define DCMI_CR_FCRC_Pos (8U)
6857#define DCMI_CR_FCRC_Msk (0x3UL << DCMI_CR_FCRC_Pos)
6858#define DCMI_CR_FCRC DCMI_CR_FCRC_Msk
6859#define DCMI_CR_FCRC_0 (0x1UL << DCMI_CR_FCRC_Pos)
6860#define DCMI_CR_FCRC_1 (0x2UL << DCMI_CR_FCRC_Pos)
6861#define DCMI_CR_EDM_Pos (10U)
6862#define DCMI_CR_EDM_Msk (0x3UL << DCMI_CR_EDM_Pos)
6863#define DCMI_CR_EDM DCMI_CR_EDM_Msk
6864#define DCMI_CR_EDM_0 (0x1UL << DCMI_CR_EDM_Pos)
6865#define DCMI_CR_EDM_1 (0x2UL << DCMI_CR_EDM_Pos)
6866#define DCMI_CR_ENABLE_Pos (14U)
6867#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
6868#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
6869#define DCMI_CR_BSM_Pos (16U)
6870#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos)
6871#define DCMI_CR_BSM DCMI_CR_BSM_Msk
6872#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos)
6873#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos)
6874#define DCMI_CR_OEBS_Pos (18U)
6875#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos)
6876#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6877#define DCMI_CR_LSM_Pos (19U)
6878#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos)
6879#define DCMI_CR_LSM DCMI_CR_LSM_Msk
6880#define DCMI_CR_OELS_Pos (20U)
6881#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos)
6882#define DCMI_CR_OELS DCMI_CR_OELS_Msk
6884/******************** Bits definition for DCMI_SR register ******************/
6885#define DCMI_SR_HSYNC_Pos (0U)
6886#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
6887#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6888#define DCMI_SR_VSYNC_Pos (1U)
6889#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
6890#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6891#define DCMI_SR_FNE_Pos (2U)
6892#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
6893#define DCMI_SR_FNE DCMI_SR_FNE_Msk
6895/******************** Bits definition for DCMI_RISR register ****************/
6896#define DCMI_RIS_FRAME_RIS_Pos (0U)
6897#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
6898#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6899#define DCMI_RIS_OVR_RIS_Pos (1U)
6900#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
6901#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6902#define DCMI_RIS_ERR_RIS_Pos (2U)
6903#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
6904#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6905#define DCMI_RIS_VSYNC_RIS_Pos (3U)
6906#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
6907#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6908#define DCMI_RIS_LINE_RIS_Pos (4U)
6909#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
6910#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6912/******************** Bits definition for DCMI_IER register *****************/
6913#define DCMI_IER_FRAME_IE_Pos (0U)
6914#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
6915#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6916#define DCMI_IER_OVR_IE_Pos (1U)
6917#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
6918#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6919#define DCMI_IER_ERR_IE_Pos (2U)
6920#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
6921#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6922#define DCMI_IER_VSYNC_IE_Pos (3U)
6923#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
6924#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6925#define DCMI_IER_LINE_IE_Pos (4U)
6926#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
6927#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6928#define DCMI_IER_INT_IE_Pos (0U)
6929#define DCMI_IER_INT_IE_Msk (0x1FUL << DCMI_IER_INT_IE_Pos)
6930#define DCMI_IER_INT_IE DCMI_IER_INT_IE_Msk
6931
6932/******************** Bits definition for DCMI_MIS register *****************/
6933#define DCMI_MIS_FRAME_MIS_Pos (0U)
6934#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
6935#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6936#define DCMI_MIS_OVR_MIS_Pos (1U)
6937#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
6938#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6939#define DCMI_MIS_ERR_MIS_Pos (2U)
6940#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
6941#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6942#define DCMI_MIS_VSYNC_MIS_Pos (3U)
6943#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
6944#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6945#define DCMI_MIS_LINE_MIS_Pos (4U)
6946#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
6947#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6949/******************** Bits definition for DCMI_ICR register *****************/
6950#define DCMI_ICR_FRAME_ISC_Pos (0U)
6951#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
6952#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6953#define DCMI_ICR_OVR_ISC_Pos (1U)
6954#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
6955#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6956#define DCMI_ICR_ERR_ISC_Pos (2U)
6957#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
6958#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6959#define DCMI_ICR_VSYNC_ISC_Pos (3U)
6960#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
6961#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6962#define DCMI_ICR_LINE_ISC_Pos (4U)
6963#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
6964#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6966/******************** Bits definition for DCMI_ESCR register ****************/
6967#define DCMI_ESCR_FSC_Pos (0U)
6968#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
6969#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6970#define DCMI_ESCR_FSC_0 (0x01UL << DCMI_ESCR_FSC_Pos)
6971#define DCMI_ESCR_FSC_1 (0x02UL << DCMI_ESCR_FSC_Pos)
6972#define DCMI_ESCR_FSC_2 (0x04UL << DCMI_ESCR_FSC_Pos)
6973#define DCMI_ESCR_FSC_3 (0x08UL << DCMI_ESCR_FSC_Pos)
6974#define DCMI_ESCR_FSC_4 (0x10UL << DCMI_ESCR_FSC_Pos)
6975#define DCMI_ESCR_FSC_5 (0x20UL << DCMI_ESCR_FSC_Pos)
6976#define DCMI_ESCR_FSC_6 (0x40UL << DCMI_ESCR_FSC_Pos)
6977#define DCMI_ESCR_FSC_7 (0x80UL << DCMI_ESCR_FSC_Pos)
6978#define DCMI_ESCR_LSC_Pos (8U)
6979#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
6980#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6981#define DCMI_ESCR_LSC_0 (0x01UL << DCMI_ESCR_LSC_Pos)
6982#define DCMI_ESCR_LSC_1 (0x02UL << DCMI_ESCR_LSC_Pos)
6983#define DCMI_ESCR_LSC_2 (0x04UL << DCMI_ESCR_LSC_Pos)
6984#define DCMI_ESCR_LSC_3 (0x08UL << DCMI_ESCR_LSC_Pos)
6985#define DCMI_ESCR_LSC_4 (0x10UL << DCMI_ESCR_LSC_Pos)
6986#define DCMI_ESCR_LSC_5 (0x20UL << DCMI_ESCR_LSC_Pos)
6987#define DCMI_ESCR_LSC_6 (0x40UL << DCMI_ESCR_LSC_Pos)
6988#define DCMI_ESCR_LSC_7 (0x80UL << DCMI_ESCR_LSC_Pos)
6989#define DCMI_ESCR_LEC_Pos (16U)
6990#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
6991#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6992#define DCMI_ESCR_LEC_0 (0x01UL << DCMI_ESCR_LEC_Pos)
6993#define DCMI_ESCR_LEC_1 (0x02UL << DCMI_ESCR_LEC_Pos)
6994#define DCMI_ESCR_LEC_2 (0x04UL << DCMI_ESCR_LEC_Pos)
6995#define DCMI_ESCR_LEC_3 (0x08UL << DCMI_ESCR_LEC_Pos)
6996#define DCMI_ESCR_LEC_4 (0x10UL << DCMI_ESCR_LEC_Pos)
6997#define DCMI_ESCR_LEC_5 (0x20UL << DCMI_ESCR_LEC_Pos)
6998#define DCMI_ESCR_LEC_6 (0x40UL << DCMI_ESCR_LEC_Pos)
6999#define DCMI_ESCR_LEC_7 (0x80UL << DCMI_ESCR_LEC_Pos)
7000#define DCMI_ESCR_FEC_Pos (24U)
7001#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
7002#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
7003#define DCMI_ESCR_FEC_0 (0x01UL << DCMI_ESCR_FEC_Pos)
7004#define DCMI_ESCR_FEC_1 (0x02UL << DCMI_ESCR_FEC_Pos)
7005#define DCMI_ESCR_FEC_2 (0x04UL << DCMI_ESCR_FEC_Pos)
7006#define DCMI_ESCR_FEC_3 (0x08UL << DCMI_ESCR_FEC_Pos)
7007#define DCMI_ESCR_FEC_4 (0x10UL << DCMI_ESCR_FEC_Pos)
7008#define DCMI_ESCR_FEC_5 (0x20UL << DCMI_ESCR_FEC_Pos)
7009#define DCMI_ESCR_FEC_6 (0x40UL << DCMI_ESCR_FEC_Pos)
7010#define DCMI_ESCR_FEC_7 (0x80UL << DCMI_ESCR_FEC_Pos)
7012/******************** Bits definition for DCMI_ESUR register ****************/
7013#define DCMI_ESUR_FSU_Pos (0U)
7014#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
7015#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
7016#define DCMI_ESUR_FSU_0 (0x01UL << DCMI_ESUR_FSU_Pos)
7017#define DCMI_ESUR_FSU_1 (0x02UL << DCMI_ESUR_FSU_Pos)
7018#define DCMI_ESUR_FSU_2 (0x04UL << DCMI_ESUR_FSU_Pos)
7019#define DCMI_ESUR_FSU_3 (0x08UL << DCMI_ESUR_FSU_Pos)
7020#define DCMI_ESUR_FSU_4 (0x10UL << DCMI_ESUR_FSU_Pos)
7021#define DCMI_ESUR_FSU_5 (0x20UL << DCMI_ESUR_FSU_Pos)
7022#define DCMI_ESUR_FSU_6 (0x40UL << DCMI_ESUR_FSU_Pos)
7023#define DCMI_ESUR_FSU_7 (0x80UL << DCMI_ESUR_FSU_Pos)
7024#define DCMI_ESUR_LSU_Pos (8U)
7025#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
7026#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
7027#define DCMI_ESUR_LSU_0 (0x01UL << DCMI_ESUR_LSU_Pos)
7028#define DCMI_ESUR_LSU_1 (0x02UL << DCMI_ESUR_LSU_Pos)
7029#define DCMI_ESUR_LSU_2 (0x04UL << DCMI_ESUR_LSU_Pos)
7030#define DCMI_ESUR_LSU_3 (0x08UL << DCMI_ESUR_LSU_Pos)
7031#define DCMI_ESUR_LSU_4 (0x10UL << DCMI_ESUR_LSU_Pos)
7032#define DCMI_ESUR_LSU_5 (0x20UL << DCMI_ESUR_LSU_Pos)
7033#define DCMI_ESUR_LSU_6 (0x40UL << DCMI_ESUR_LSU_Pos)
7034#define DCMI_ESUR_LSU_7 (0x80UL << DCMI_ESUR_LSU_Pos)
7035#define DCMI_ESUR_LEU_Pos (16U)
7036#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
7037#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
7038#define DCMI_ESUR_LEU_0 (0x01UL << DCMI_ESUR_LEU_Pos)
7039#define DCMI_ESUR_LEU_1 (0x02UL << DCMI_ESUR_LEU_Pos)
7040#define DCMI_ESUR_LEU_2 (0x04UL << DCMI_ESUR_LEU_Pos)
7041#define DCMI_ESUR_LEU_3 (0x08UL << DCMI_ESUR_LEU_Pos)
7042#define DCMI_ESUR_LEU_4 (0x10UL << DCMI_ESUR_LEU_Pos)
7043#define DCMI_ESUR_LEU_5 (0x20UL << DCMI_ESUR_LEU_Pos)
7044#define DCMI_ESUR_LEU_6 (0x40UL << DCMI_ESUR_LEU_Pos)
7045#define DCMI_ESUR_LEU_7 (0x80UL << DCMI_ESUR_LEU_Pos)
7046#define DCMI_ESUR_FEU_Pos (24U)
7047#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
7048#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
7049#define DCMI_ESUR_FEU_0 (0x01UL << DCMI_ESUR_FEU_Pos)
7050#define DCMI_ESUR_FEU_1 (0x02UL << DCMI_ESUR_FEU_Pos)
7051#define DCMI_ESUR_FEU_2 (0x04UL << DCMI_ESUR_FEU_Pos)
7052#define DCMI_ESUR_FEU_3 (0x08UL << DCMI_ESUR_FEU_Pos)
7053#define DCMI_ESUR_FEU_4 (0x10UL << DCMI_ESUR_FEU_Pos)
7054#define DCMI_ESUR_FEU_5 (0x20UL << DCMI_ESUR_FEU_Pos)
7055#define DCMI_ESUR_FEU_6 (0x40UL << DCMI_ESUR_FEU_Pos)
7056#define DCMI_ESUR_FEU_7 (0x80UL << DCMI_ESUR_FEU_Pos)
7058/******************** Bits definition for DCMI_CWSTRT register **************/
7059#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
7060#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
7061#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
7062#define DCMI_CWSTRT_HOFFCNT_0 (0x0001UL << DCMI_CWSTRT_HOFFCNT_Pos)
7063#define DCMI_CWSTRT_HOFFCNT_1 (0x0002UL << DCMI_CWSTRT_HOFFCNT_Pos)
7064#define DCMI_CWSTRT_HOFFCNT_2 (0x0004UL << DCMI_CWSTRT_HOFFCNT_Pos)
7065#define DCMI_CWSTRT_HOFFCNT_3 (0x0008UL << DCMI_CWSTRT_HOFFCNT_Pos)
7066#define DCMI_CWSTRT_HOFFCNT_4 (0x0010UL << DCMI_CWSTRT_HOFFCNT_Pos)
7067#define DCMI_CWSTRT_HOFFCNT_5 (0x0020UL << DCMI_CWSTRT_HOFFCNT_Pos)
7068#define DCMI_CWSTRT_HOFFCNT_6 (0x0040UL << DCMI_CWSTRT_HOFFCNT_Pos)
7069#define DCMI_CWSTRT_HOFFCNT_7 (0x0080UL << DCMI_CWSTRT_HOFFCNT_Pos)
7070#define DCMI_CWSTRT_HOFFCNT_8 (0x0100UL << DCMI_CWSTRT_HOFFCNT_Pos)
7071#define DCMI_CWSTRT_HOFFCNT_9 (0x0200UL << DCMI_CWSTRT_HOFFCNT_Pos)
7072#define DCMI_CWSTRT_HOFFCNT_10 (0x0400UL << DCMI_CWSTRT_HOFFCNT_Pos)
7073#define DCMI_CWSTRT_HOFFCNT_11 (0x0800UL << DCMI_CWSTRT_HOFFCNT_Pos)
7074#define DCMI_CWSTRT_HOFFCNT_12 (0x1000UL << DCMI_CWSTRT_HOFFCNT_Pos)
7075#define DCMI_CWSTRT_HOFFCNT_13 (0x2000UL << DCMI_CWSTRT_HOFFCNT_Pos)
7076#define DCMI_CWSTRT_VST_Pos (16U)
7077#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
7078#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
7079#define DCMI_CWSTRT_VST_0 (0x0001UL << DCMI_CWSTRT_VST_Pos)
7080#define DCMI_CWSTRT_VST_1 (0x0002UL << DCMI_CWSTRT_VST_Pos)
7081#define DCMI_CWSTRT_VST_2 (0x0004UL << DCMI_CWSTRT_VST_Pos)
7082#define DCMI_CWSTRT_VST_3 (0x0008UL << DCMI_CWSTRT_VST_Pos)
7083#define DCMI_CWSTRT_VST_4 (0x0010UL << DCMI_CWSTRT_VST_Pos)
7084#define DCMI_CWSTRT_VST_5 (0x0020UL << DCMI_CWSTRT_VST_Pos)
7085#define DCMI_CWSTRT_VST_6 (0x0040UL << DCMI_CWSTRT_VST_Pos)
7086#define DCMI_CWSTRT_VST_7 (0x0080UL << DCMI_CWSTRT_VST_Pos)
7087#define DCMI_CWSTRT_VST_8 (0x0100UL << DCMI_CWSTRT_VST_Pos)
7088#define DCMI_CWSTRT_VST_9 (0x0200UL << DCMI_CWSTRT_VST_Pos)
7089#define DCMI_CWSTRT_VST_10 (0x0400UL << DCMI_CWSTRT_VST_Pos)
7090#define DCMI_CWSTRT_VST_11 (0x0800UL << DCMI_CWSTRT_VST_Pos)
7091#define DCMI_CWSTRT_VST_12 (0x1000UL << DCMI_CWSTRT_VST_Pos)
7093/******************** Bits definition for DCMI_CWSIZE register **************/
7094#define DCMI_CWSIZE_CAPCNT_Pos (0U)
7095#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
7096#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
7097#define DCMI_CWSIZE_CAPCNT_0 (0x0001UL << DCMI_CWSIZE_CAPCNT_Pos)
7098#define DCMI_CWSIZE_CAPCNT_1 (0x0002UL << DCMI_CWSIZE_CAPCNT_Pos)
7099#define DCMI_CWSIZE_CAPCNT_2 (0x0004UL << DCMI_CWSIZE_CAPCNT_Pos)
7100#define DCMI_CWSIZE_CAPCNT_3 (0x0008UL << DCMI_CWSIZE_CAPCNT_Pos)
7101#define DCMI_CWSIZE_CAPCNT_4 (0x0010UL << DCMI_CWSIZE_CAPCNT_Pos)
7102#define DCMI_CWSIZE_CAPCNT_5 (0x0020UL << DCMI_CWSIZE_CAPCNT_Pos)
7103#define DCMI_CWSIZE_CAPCNT_6 (0x0040UL << DCMI_CWSIZE_CAPCNT_Pos)
7104#define DCMI_CWSIZE_CAPCNT_7 (0x0080UL << DCMI_CWSIZE_CAPCNT_Pos)
7105#define DCMI_CWSIZE_CAPCNT_8 (0x0100UL << DCMI_CWSIZE_CAPCNT_Pos)
7106#define DCMI_CWSIZE_CAPCNT_9 (0x0200UL << DCMI_CWSIZE_CAPCNT_Pos)
7107#define DCMI_CWSIZE_CAPCNT_10 (0x0400UL << DCMI_CWSIZE_CAPCNT_Pos)
7108#define DCMI_CWSIZE_CAPCNT_11 (0x0800UL << DCMI_CWSIZE_CAPCNT_Pos)
7109#define DCMI_CWSIZE_CAPCNT_12 (0x1000UL << DCMI_CWSIZE_CAPCNT_Pos)
7110#define DCMI_CWSIZE_CAPCNT_13 (0x2000UL << DCMI_CWSIZE_CAPCNT_Pos)
7111#define DCMI_CWSIZE_VLINE_Pos (16U)
7112#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
7113#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
7114#define DCMI_CWSIZE_VLINE_0 (0x0001UL << DCMI_CWSIZE_VLINE_Pos)
7115#define DCMI_CWSIZE_VLINE_1 (0x0002UL << DCMI_CWSIZE_VLINE_Pos)
7116#define DCMI_CWSIZE_VLINE_2 (0x0004UL << DCMI_CWSIZE_VLINE_Pos)
7117#define DCMI_CWSIZE_VLINE_3 (0x0008UL << DCMI_CWSIZE_VLINE_Pos)
7118#define DCMI_CWSIZE_VLINE_4 (0x0010UL << DCMI_CWSIZE_VLINE_Pos)
7119#define DCMI_CWSIZE_VLINE_5 (0x0020UL << DCMI_CWSIZE_VLINE_Pos)
7120#define DCMI_CWSIZE_VLINE_6 (0x0040UL << DCMI_CWSIZE_VLINE_Pos)
7121#define DCMI_CWSIZE_VLINE_7 (0x0080UL << DCMI_CWSIZE_VLINE_Pos)
7122#define DCMI_CWSIZE_VLINE_8 (0x0100UL << DCMI_CWSIZE_VLINE_Pos)
7123#define DCMI_CWSIZE_VLINE_9 (0x0200UL << DCMI_CWSIZE_VLINE_Pos)
7124#define DCMI_CWSIZE_VLINE_10 (0x0400UL << DCMI_CWSIZE_VLINE_Pos)
7125#define DCMI_CWSIZE_VLINE_11 (0x0800UL << DCMI_CWSIZE_VLINE_Pos)
7126#define DCMI_CWSIZE_VLINE_12 (0x1000UL << DCMI_CWSIZE_VLINE_Pos)
7127#define DCMI_CWSIZE_VLINE_13 (0x2000UL << DCMI_CWSIZE_VLINE_Pos)
7129/******************** Bits definition for DCMI_DR register **************/
7130#define DCMI_DR_BYTE0_Pos (0U)
7131#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
7132#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
7133#define DCMI_DR_BYTE0_0 (0x01UL << DCMI_DR_BYTE0_Pos)
7134#define DCMI_DR_BYTE0_1 (0x02UL << DCMI_DR_BYTE0_Pos)
7135#define DCMI_DR_BYTE0_2 (0x04UL << DCMI_DR_BYTE0_Pos)
7136#define DCMI_DR_BYTE0_3 (0x08UL << DCMI_DR_BYTE0_Pos)
7137#define DCMI_DR_BYTE0_4 (0x10UL << DCMI_DR_BYTE0_Pos)
7138#define DCMI_DR_BYTE0_5 (0x20UL << DCMI_DR_BYTE0_Pos)
7139#define DCMI_DR_BYTE0_6 (0x40UL << DCMI_DR_BYTE0_Pos)
7140#define DCMI_DR_BYTE0_7 (0x80UL << DCMI_DR_BYTE0_Pos)
7141#define DCMI_DR_BYTE1_Pos (8U)
7142#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
7143#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
7144#define DCMI_DR_BYTE1_0 (0x01UL << DCMI_DR_BYTE1_Pos)
7145#define DCMI_DR_BYTE1_1 (0x02UL << DCMI_DR_BYTE1_Pos)
7146#define DCMI_DR_BYTE1_2 (0x04UL << DCMI_DR_BYTE1_Pos)
7147#define DCMI_DR_BYTE1_3 (0x08UL << DCMI_DR_BYTE1_Pos)
7148#define DCMI_DR_BYTE1_4 (0x10UL << DCMI_DR_BYTE1_Pos)
7149#define DCMI_DR_BYTE1_5 (0x20UL << DCMI_DR_BYTE1_Pos)
7150#define DCMI_DR_BYTE1_6 (0x40UL << DCMI_DR_BYTE1_Pos)
7151#define DCMI_DR_BYTE1_7 (0x80UL << DCMI_DR_BYTE1_Pos)
7152#define DCMI_DR_BYTE2_Pos (16U)
7153#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
7154#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
7155#define DCMI_DR_BYTE2_0 (0x01UL << DCMI_DR_BYTE2_Pos)
7156#define DCMI_DR_BYTE2_1 (0x02UL << DCMI_DR_BYTE2_Pos)
7157#define DCMI_DR_BYTE2_2 (0x04UL << DCMI_DR_BYTE2_Pos)
7158#define DCMI_DR_BYTE2_3 (0x08UL << DCMI_DR_BYTE2_Pos)
7159#define DCMI_DR_BYTE2_4 (0x10UL << DCMI_DR_BYTE2_Pos)
7160#define DCMI_DR_BYTE2_5 (0x20UL << DCMI_DR_BYTE2_Pos)
7161#define DCMI_DR_BYTE2_6 (0x40UL << DCMI_DR_BYTE2_Pos)
7162#define DCMI_DR_BYTE2_7 (0x80UL << DCMI_DR_BYTE2_Pos)
7163#define DCMI_DR_BYTE3_Pos (24U)
7164#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
7165#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
7166#define DCMI_DR_BYTE3_0 (0x01UL << DCMI_DR_BYTE3_Pos)
7167#define DCMI_DR_BYTE3_1 (0x02UL << DCMI_DR_BYTE3_Pos)
7168#define DCMI_DR_BYTE3_2 (0x04UL << DCMI_DR_BYTE3_Pos)
7169#define DCMI_DR_BYTE3_3 (0x08UL << DCMI_DR_BYTE3_Pos)
7170#define DCMI_DR_BYTE3_4 (0x10UL << DCMI_DR_BYTE3_Pos)
7171#define DCMI_DR_BYTE3_5 (0x20UL << DCMI_DR_BYTE3_Pos)
7172#define DCMI_DR_BYTE3_6 (0x40UL << DCMI_DR_BYTE3_Pos)
7173#define DCMI_DR_BYTE3_7 (0x80UL << DCMI_DR_BYTE3_Pos)
7175/******************************************************************************/
7176/* */
7177/* Digital Filter for Sigma Delta Modulators */
7178/* */
7179/******************************************************************************/
7180
7181/**************** DFSDM channel configuration registers ********************/
7182
7183/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
7184#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
7185#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)
7186#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk
7187#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
7188#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)
7189#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk
7190#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
7191#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)
7192#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk
7193#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
7194#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)
7195#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk
7196#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)
7197#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)
7198#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
7199#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)
7200#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk
7201#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)
7202#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)
7203#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
7204#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)
7205#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk
7206#define DFSDM_CHCFGR1_CHEN_Pos (7U)
7207#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)
7208#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk
7209#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
7210#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)
7211#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk
7212#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
7213#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)
7214#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk
7215#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
7216#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
7217#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk
7218#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
7219#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
7220#define DFSDM_CHCFGR1_SITP_Pos (0U)
7221#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos)
7222#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk
7223#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos)
7224#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos)
7226/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
7227#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
7228#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)
7229#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk
7230#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
7231#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)
7232#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk
7234/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
7235#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
7236#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)
7237#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk
7238#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)
7239#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)
7240#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
7241#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)
7242#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk
7243#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
7244#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)
7245#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk
7246#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
7247#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)
7248#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk
7250/**************** Bit definition for DFSDM_CHWDATR register *******************/
7251#define DFSDM_CHWDATR_WDATA_Pos (0U)
7252#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)
7253#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk
7255/**************** Bit definition for DFSDM_CHDATINR register *****************/
7256#define DFSDM_CHDATINR_INDAT0_Pos (0U)
7257#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)
7258#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk
7259#define DFSDM_CHDATINR_INDAT1_Pos (16U)
7260#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)
7261#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk
7263/************************ DFSDM module registers ****************************/
7264
7265/***************** Bit definition for DFSDM_FLTCR1 register *******************/
7266#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
7267#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)
7268#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk
7269#define DFSDM_FLTCR1_FAST_Pos (29U)
7270#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos)
7271#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk
7272#define DFSDM_FLTCR1_RCH_Pos (24U)
7273#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos)
7274#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk
7275#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
7276#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)
7277#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk
7278#define DFSDM_FLTCR1_RSYNC_Pos (19U)
7279#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)
7280#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk
7281#define DFSDM_FLTCR1_RCONT_Pos (18U)
7282#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos)
7283#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk
7284#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
7285#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)
7286#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk
7287#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
7288#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)
7289#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk
7290#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)
7291#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)
7292#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
7293#define DFSDM_FLTCR1_JEXTSEL_Msk (0x7UL << DFSDM_FLTCR1_JEXTSEL_Pos)
7294#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk
7295#define DFSDM_FLTCR1_JEXTSEL_2 (0x4UL << DFSDM_FLTCR1_JEXTSEL_Pos)
7296#define DFSDM_FLTCR1_JEXTSEL_1 (0x2UL << DFSDM_FLTCR1_JEXTSEL_Pos)
7297#define DFSDM_FLTCR1_JEXTSEL_0 (0x1UL << DFSDM_FLTCR1_JEXTSEL_Pos)
7298#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
7299#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)
7300#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk
7301#define DFSDM_FLTCR1_JSCAN_Pos (4U)
7302#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)
7303#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk
7304#define DFSDM_FLTCR1_JSYNC_Pos (3U)
7305#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)
7306#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk
7307#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
7308#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)
7309#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk
7310#define DFSDM_FLTCR1_DFEN_Pos (0U)
7311#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos)
7312#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk
7314/***************** Bit definition for DFSDM_FLTCR2 register *******************/
7315#define DFSDM_FLTCR2_AWDCH_Pos (16U)
7316#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)
7317#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk
7318#define DFSDM_FLTCR2_EXCH_Pos (8U)
7319#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)
7320#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk
7321#define DFSDM_FLTCR2_CKABIE_Pos (6U)
7322#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)
7323#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk
7324#define DFSDM_FLTCR2_SCDIE_Pos (5U)
7325#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)
7326#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk
7327#define DFSDM_FLTCR2_AWDIE_Pos (4U)
7328#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)
7329#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk
7330#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
7331#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)
7332#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk
7333#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
7334#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)
7335#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk
7336#define DFSDM_FLTCR2_REOCIE_Pos (1U)
7337#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)
7338#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk
7339#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
7340#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)
7341#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk
7343/***************** Bit definition for DFSDM_FLTISR register *******************/
7344#define DFSDM_FLTISR_SCDF_Pos (24U)
7345#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos)
7346#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk
7347#define DFSDM_FLTISR_CKABF_Pos (16U)
7348#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos)
7349#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk
7350#define DFSDM_FLTISR_RCIP_Pos (14U)
7351#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos)
7352#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk
7353#define DFSDM_FLTISR_JCIP_Pos (13U)
7354#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos)
7355#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk
7356#define DFSDM_FLTISR_AWDF_Pos (4U)
7357#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos)
7358#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk
7359#define DFSDM_FLTISR_ROVRF_Pos (3U)
7360#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos)
7361#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk
7362#define DFSDM_FLTISR_JOVRF_Pos (2U)
7363#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos)
7364#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk
7365#define DFSDM_FLTISR_REOCF_Pos (1U)
7366#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos)
7367#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk
7368#define DFSDM_FLTISR_JEOCF_Pos (0U)
7369#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos)
7370#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk
7372/***************** Bit definition for DFSDM_FLTICR register *******************/
7373#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
7374#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)
7375#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk
7376#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
7377#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)
7378#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk
7379#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
7380#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)
7381#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk
7382#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
7383#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)
7384#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk
7386/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
7387#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
7388#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)
7389#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk
7391/***************** Bit definition for DFSDM_FLTFCR register *******************/
7392#define DFSDM_FLTFCR_FORD_Pos (29U)
7393#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos)
7394#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk
7395#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos)
7396#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos)
7397#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos)
7398#define DFSDM_FLTFCR_FOSR_Pos (16U)
7399#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)
7400#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk
7401#define DFSDM_FLTFCR_IOSR_Pos (0U)
7402#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)
7403#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk
7405/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
7406#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
7407#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)
7408#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk
7409#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
7410#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)
7411#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk
7413/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
7414#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
7415#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)
7416#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk
7417#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
7418#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)
7419#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk
7420#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
7421#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)
7422#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk
7424/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
7425#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
7426#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)
7427#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk
7428#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
7429#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)
7430#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk
7432/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
7433#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
7434#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)
7435#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk
7436#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
7437#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)
7438#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk
7440/*************** Bit definition for DFSDM_FLTAWSR register *******************/
7441#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
7442#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)
7443#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk
7444#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
7445#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)
7446#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk
7448/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
7449#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
7450#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)
7451#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk
7452#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
7453#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)
7454#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk
7456/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
7457#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
7458#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)
7459#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk
7460#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
7461#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)
7462#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk
7464/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
7465#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
7466#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)
7467#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk
7468#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
7469#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)
7470#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk
7472/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
7473#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
7474#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)
7475#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk
7477/******************************************************************************/
7478/* */
7479/* DMA Controller (DMA) */
7480/* */
7481/******************************************************************************/
7482
7483/******************* Bit definition for DMA_ISR register ********************/
7484#define DMA_ISR_GIF1_Pos (0U)
7485#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)
7486#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk
7487#define DMA_ISR_TCIF1_Pos (1U)
7488#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)
7489#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk
7490#define DMA_ISR_HTIF1_Pos (2U)
7491#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)
7492#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk
7493#define DMA_ISR_TEIF1_Pos (3U)
7494#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)
7495#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk
7496#define DMA_ISR_GIF2_Pos (4U)
7497#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)
7498#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk
7499#define DMA_ISR_TCIF2_Pos (5U)
7500#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)
7501#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk
7502#define DMA_ISR_HTIF2_Pos (6U)
7503#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)
7504#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk
7505#define DMA_ISR_TEIF2_Pos (7U)
7506#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)
7507#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk
7508#define DMA_ISR_GIF3_Pos (8U)
7509#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)
7510#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk
7511#define DMA_ISR_TCIF3_Pos (9U)
7512#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)
7513#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk
7514#define DMA_ISR_HTIF3_Pos (10U)
7515#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)
7516#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk
7517#define DMA_ISR_TEIF3_Pos (11U)
7518#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)
7519#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk
7520#define DMA_ISR_GIF4_Pos (12U)
7521#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)
7522#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk
7523#define DMA_ISR_TCIF4_Pos (13U)
7524#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)
7525#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk
7526#define DMA_ISR_HTIF4_Pos (14U)
7527#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)
7528#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk
7529#define DMA_ISR_TEIF4_Pos (15U)
7530#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)
7531#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk
7532#define DMA_ISR_GIF5_Pos (16U)
7533#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)
7534#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk
7535#define DMA_ISR_TCIF5_Pos (17U)
7536#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)
7537#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk
7538#define DMA_ISR_HTIF5_Pos (18U)
7539#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)
7540#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk
7541#define DMA_ISR_TEIF5_Pos (19U)
7542#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)
7543#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk
7544#define DMA_ISR_GIF6_Pos (20U)
7545#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)
7546#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk
7547#define DMA_ISR_TCIF6_Pos (21U)
7548#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)
7549#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk
7550#define DMA_ISR_HTIF6_Pos (22U)
7551#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)
7552#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk
7553#define DMA_ISR_TEIF6_Pos (23U)
7554#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)
7555#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk
7556#define DMA_ISR_GIF7_Pos (24U)
7557#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)
7558#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk
7559#define DMA_ISR_TCIF7_Pos (25U)
7560#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)
7561#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk
7562#define DMA_ISR_HTIF7_Pos (26U)
7563#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)
7564#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk
7565#define DMA_ISR_TEIF7_Pos (27U)
7566#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)
7567#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk
7569/******************* Bit definition for DMA_IFCR register *******************/
7570#define DMA_IFCR_CGIF1_Pos (0U)
7571#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)
7572#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk
7573#define DMA_IFCR_CTCIF1_Pos (1U)
7574#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)
7575#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk
7576#define DMA_IFCR_CHTIF1_Pos (2U)
7577#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)
7578#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk
7579#define DMA_IFCR_CTEIF1_Pos (3U)
7580#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)
7581#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk
7582#define DMA_IFCR_CGIF2_Pos (4U)
7583#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)
7584#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk
7585#define DMA_IFCR_CTCIF2_Pos (5U)
7586#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)
7587#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk
7588#define DMA_IFCR_CHTIF2_Pos (6U)
7589#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)
7590#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk
7591#define DMA_IFCR_CTEIF2_Pos (7U)
7592#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)
7593#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk
7594#define DMA_IFCR_CGIF3_Pos (8U)
7595#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)
7596#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk
7597#define DMA_IFCR_CTCIF3_Pos (9U)
7598#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)
7599#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk
7600#define DMA_IFCR_CHTIF3_Pos (10U)
7601#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)
7602#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk
7603#define DMA_IFCR_CTEIF3_Pos (11U)
7604#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)
7605#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk
7606#define DMA_IFCR_CGIF4_Pos (12U)
7607#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)
7608#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk
7609#define DMA_IFCR_CTCIF4_Pos (13U)
7610#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)
7611#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk
7612#define DMA_IFCR_CHTIF4_Pos (14U)
7613#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)
7614#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk
7615#define DMA_IFCR_CTEIF4_Pos (15U)
7616#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)
7617#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk
7618#define DMA_IFCR_CGIF5_Pos (16U)
7619#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)
7620#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk
7621#define DMA_IFCR_CTCIF5_Pos (17U)
7622#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)
7623#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk
7624#define DMA_IFCR_CHTIF5_Pos (18U)
7625#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)
7626#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk
7627#define DMA_IFCR_CTEIF5_Pos (19U)
7628#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)
7629#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk
7630#define DMA_IFCR_CGIF6_Pos (20U)
7631#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)
7632#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk
7633#define DMA_IFCR_CTCIF6_Pos (21U)
7634#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)
7635#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk
7636#define DMA_IFCR_CHTIF6_Pos (22U)
7637#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)
7638#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk
7639#define DMA_IFCR_CTEIF6_Pos (23U)
7640#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)
7641#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk
7642#define DMA_IFCR_CGIF7_Pos (24U)
7643#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)
7644#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk
7645#define DMA_IFCR_CTCIF7_Pos (25U)
7646#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)
7647#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk
7648#define DMA_IFCR_CHTIF7_Pos (26U)
7649#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)
7650#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk
7651#define DMA_IFCR_CTEIF7_Pos (27U)
7652#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)
7653#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk
7655/******************* Bit definition for DMA_CCR register ********************/
7656#define DMA_CCR_EN_Pos (0U)
7657#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)
7658#define DMA_CCR_EN DMA_CCR_EN_Msk
7659#define DMA_CCR_TCIE_Pos (1U)
7660#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)
7661#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk
7662#define DMA_CCR_HTIE_Pos (2U)
7663#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)
7664#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk
7665#define DMA_CCR_TEIE_Pos (3U)
7666#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)
7667#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk
7668#define DMA_CCR_DIR_Pos (4U)
7669#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)
7670#define DMA_CCR_DIR DMA_CCR_DIR_Msk
7671#define DMA_CCR_CIRC_Pos (5U)
7672#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)
7673#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk
7674#define DMA_CCR_PINC_Pos (6U)
7675#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)
7676#define DMA_CCR_PINC DMA_CCR_PINC_Msk
7677#define DMA_CCR_MINC_Pos (7U)
7678#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)
7679#define DMA_CCR_MINC DMA_CCR_MINC_Msk
7681#define DMA_CCR_PSIZE_Pos (8U)
7682#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)
7683#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk
7684#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)
7685#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)
7687#define DMA_CCR_MSIZE_Pos (10U)
7688#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)
7689#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk
7690#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)
7691#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)
7693#define DMA_CCR_PL_Pos (12U)
7694#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)
7695#define DMA_CCR_PL DMA_CCR_PL_Msk
7696#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)
7697#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)
7699#define DMA_CCR_MEM2MEM_Pos (14U)
7700#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)
7701#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk
7703/****************** Bit definition for DMA_CNDTR register *******************/
7704#define DMA_CNDTR_NDT_Pos (0U)
7705#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)
7706#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk
7708/****************** Bit definition for DMA_CPAR register ********************/
7709#define DMA_CPAR_PA_Pos (0U)
7710#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)
7711#define DMA_CPAR_PA DMA_CPAR_PA_Msk
7713/****************** Bit definition for DMA_CMAR register ********************/
7714#define DMA_CMAR_MA_Pos (0U)
7715#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)
7716#define DMA_CMAR_MA DMA_CMAR_MA_Msk
7719/******************* Bit definition for DMA_CSELR register *******************/
7720#define DMA_CSELR_C1S_Pos (0U)
7721#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos)
7722#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk
7723#define DMA_CSELR_C2S_Pos (4U)
7724#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos)
7725#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk
7726#define DMA_CSELR_C3S_Pos (8U)
7727#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos)
7728#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk
7729#define DMA_CSELR_C4S_Pos (12U)
7730#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos)
7731#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk
7732#define DMA_CSELR_C5S_Pos (16U)
7733#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos)
7734#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk
7735#define DMA_CSELR_C6S_Pos (20U)
7736#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos)
7737#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk
7738#define DMA_CSELR_C7S_Pos (24U)
7739#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos)
7740#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk
7742/******************************************************************************/
7743/* */
7744/* AHB Master DMA2D Controller (DMA2D) */
7745/* */
7746/******************************************************************************/
7747
7748/******************** Bit definition for DMA2D_CR register ******************/
7749
7750#define DMA2D_CR_START_Pos (0U)
7751#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos)
7752#define DMA2D_CR_START DMA2D_CR_START_Msk
7753#define DMA2D_CR_SUSP_Pos (1U)
7754#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos)
7755#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk
7756#define DMA2D_CR_ABORT_Pos (2U)
7757#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos)
7758#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk
7759#define DMA2D_CR_TEIE_Pos (8U)
7760#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos)
7761#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk
7762#define DMA2D_CR_TCIE_Pos (9U)
7763#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos)
7764#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk
7765#define DMA2D_CR_TWIE_Pos (10U)
7766#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos)
7767#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk
7768#define DMA2D_CR_CAEIE_Pos (11U)
7769#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos)
7770#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk
7771#define DMA2D_CR_CTCIE_Pos (12U)
7772#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos)
7773#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk
7774#define DMA2D_CR_CEIE_Pos (13U)
7775#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos)
7776#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk
7777#define DMA2D_CR_MODE_Pos (16U)
7778#define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos)
7779#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk
7780#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos)
7781#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos)
7783/******************** Bit definition for DMA2D_ISR register *****************/
7784
7785#define DMA2D_ISR_TEIF_Pos (0U)
7786#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos)
7787#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk
7788#define DMA2D_ISR_TCIF_Pos (1U)
7789#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos)
7790#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk
7791#define DMA2D_ISR_TWIF_Pos (2U)
7792#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos)
7793#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk
7794#define DMA2D_ISR_CAEIF_Pos (3U)
7795#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos)
7796#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk
7797#define DMA2D_ISR_CTCIF_Pos (4U)
7798#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos)
7799#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk
7800#define DMA2D_ISR_CEIF_Pos (5U)
7801#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos)
7802#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk
7804/******************** Bit definition for DMA2D_IFCR register ****************/
7805
7806#define DMA2D_IFCR_CTEIF_Pos (0U)
7807#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos)
7808#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk
7809#define DMA2D_IFCR_CTCIF_Pos (1U)
7810#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos)
7811#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk
7812#define DMA2D_IFCR_CTWIF_Pos (2U)
7813#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos)
7814#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk
7815#define DMA2D_IFCR_CAECIF_Pos (3U)
7816#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos)
7817#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk
7818#define DMA2D_IFCR_CCTCIF_Pos (4U)
7819#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos)
7820#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk
7821#define DMA2D_IFCR_CCEIF_Pos (5U)
7822#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos)
7823#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk
7825/******************** Bit definition for DMA2D_FGMAR register ***************/
7826
7827#define DMA2D_FGMAR_MA_Pos (0U)
7828#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)
7829#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk
7831/******************** Bit definition for DMA2D_FGOR register ****************/
7832
7833#define DMA2D_FGOR_LO_Pos (0U)
7834#define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos)
7835#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk
7837/******************** Bit definition for DMA2D_BGMAR register ***************/
7838
7839#define DMA2D_BGMAR_MA_Pos (0U)
7840#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)
7841#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk
7843/******************** Bit definition for DMA2D_BGOR register ****************/
7844
7845#define DMA2D_BGOR_LO_Pos (0U)
7846#define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos)
7847#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk
7849/******************** Bit definition for DMA2D_FGPFCCR register *************/
7850
7851#define DMA2D_FGPFCCR_CM_Pos (0U)
7852#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos)
7853#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk
7854#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos)
7855#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos)
7856#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos)
7857#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos)
7858#define DMA2D_FGPFCCR_CCM_Pos (4U)
7859#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos)
7860#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk
7861#define DMA2D_FGPFCCR_START_Pos (5U)
7862#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos)
7863#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk
7864#define DMA2D_FGPFCCR_CS_Pos (8U)
7865#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos)
7866#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk
7867#define DMA2D_FGPFCCR_AM_Pos (16U)
7868#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos)
7869#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk
7870#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos)
7871#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos)
7872#define DMA2D_FGPFCCR_AI_Pos (20U)
7873#define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos)
7874#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk
7875#define DMA2D_FGPFCCR_RBS_Pos (21U)
7876#define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos)
7877#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk
7878#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
7879#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)
7880#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk
7882/******************** Bit definition for DMA2D_FGCOLR register **************/
7883
7884#define DMA2D_FGCOLR_BLUE_Pos (0U)
7885#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)
7886#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk
7887#define DMA2D_FGCOLR_GREEN_Pos (8U)
7888#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)
7889#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk
7890#define DMA2D_FGCOLR_RED_Pos (16U)
7891#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos)
7892#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk
7894/******************** Bit definition for DMA2D_BGPFCCR register *************/
7895
7896#define DMA2D_BGPFCCR_CM_Pos (0U)
7897#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos)
7898#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk
7899#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos)
7900#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos)
7901#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos)
7902#define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos)
7903#define DMA2D_BGPFCCR_CCM_Pos (4U)
7904#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos)
7905#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk
7906#define DMA2D_BGPFCCR_START_Pos (5U)
7907#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos)
7908#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk
7909#define DMA2D_BGPFCCR_CS_Pos (8U)
7910#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos)
7911#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk
7912#define DMA2D_BGPFCCR_AM_Pos (16U)
7913#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos)
7914#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk
7915#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos)
7916#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos)
7917#define DMA2D_BGPFCCR_AI_Pos (20U)
7918#define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos)
7919#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk
7920#define DMA2D_BGPFCCR_RBS_Pos (21U)
7921#define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos)
7922#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk
7923#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
7924#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)
7925#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk
7927/******************** Bit definition for DMA2D_BGCOLR register **************/
7928
7929#define DMA2D_BGCOLR_BLUE_Pos (0U)
7930#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)
7931#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk
7932#define DMA2D_BGCOLR_GREEN_Pos (8U)
7933#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)
7934#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk
7935#define DMA2D_BGCOLR_RED_Pos (16U)
7936#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos)
7937#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk
7939/******************** Bit definition for DMA2D_FGCMAR register **************/
7940
7941#define DMA2D_FGCMAR_MA_Pos (0U)
7942#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)
7943#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk
7945/******************** Bit definition for DMA2D_BGCMAR register **************/
7946
7947#define DMA2D_BGCMAR_MA_Pos (0U)
7948#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)
7949#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk
7951/******************** Bit definition for DMA2D_OPFCCR register **************/
7952
7953#define DMA2D_OPFCCR_CM_Pos (0U)
7954#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos)
7955#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk
7956#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos)
7957#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos)
7958#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos)
7959#define DMA2D_OPFCCR_AI_Pos (20U)
7960#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos)
7961#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk
7962#define DMA2D_OPFCCR_RBS_Pos (21U)
7963#define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos)
7964#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk
7966/******************** Bit definition for DMA2D_OCOLR register ***************/
7967
7970#define DMA2D_OCOLR_BLUE_1 (0x000000FFUL)
7971#define DMA2D_OCOLR_GREEN_1 (0x0000FF00UL)
7972#define DMA2D_OCOLR_RED_1 (0x00FF0000UL)
7973#define DMA2D_OCOLR_ALPHA_1 (0xFF000000UL)
7976#define DMA2D_OCOLR_BLUE_2 (0x0000001FUL)
7977#define DMA2D_OCOLR_GREEN_2 (0x000007E0UL)
7978#define DMA2D_OCOLR_RED_2 (0x0000F800UL)
7981#define DMA2D_OCOLR_BLUE_3 (0x0000001FUL)
7982#define DMA2D_OCOLR_GREEN_3 (0x000003E0UL)
7983#define DMA2D_OCOLR_RED_3 (0x00007C00UL)
7984#define DMA2D_OCOLR_ALPHA_3 (0x00008000UL)
7987#define DMA2D_OCOLR_BLUE_4 (0x0000000FUL)
7988#define DMA2D_OCOLR_GREEN_4 (0x000000F0UL)
7989#define DMA2D_OCOLR_RED_4 (0x00000F00UL)
7990#define DMA2D_OCOLR_ALPHA_4 (0x0000F000UL)
7992/******************** Bit definition for DMA2D_OMAR register ****************/
7993
7994#define DMA2D_OMAR_MA_Pos (0U)
7995#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)
7996#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk
7998/******************** Bit definition for DMA2D_OOR register *****************/
7999
8000#define DMA2D_OOR_LO_Pos (0U)
8001#define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos)
8002#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk
8004/******************** Bit definition for DMA2D_NLR register *****************/
8005
8006#define DMA2D_NLR_NL_Pos (0U)
8007#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos)
8008#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk
8009#define DMA2D_NLR_PL_Pos (16U)
8010#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos)
8011#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk
8013/******************** Bit definition for DMA2D_LWR register *****************/
8014
8015#define DMA2D_LWR_LW_Pos (0U)
8016#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos)
8017#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk
8019/******************** Bit definition for DMA2D_AMTCR register ***************/
8020
8021#define DMA2D_AMTCR_EN_Pos (0U)
8022#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos)
8023#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk
8024#define DMA2D_AMTCR_DT_Pos (8U)
8025#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos)
8026#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk
8028/******************** Bit definition for DMA2D_FGCLUT register **************/
8029
8030/******************** Bit definition for DMA2D_BGCLUT register **************/
8031
8032/******************************************************************************/
8033/* */
8034/* External Interrupt/Event Controller */
8035/* */
8036/******************************************************************************/
8037/******************* Bit definition for EXTI_IMR1 register ******************/
8038#define EXTI_IMR1_IM0_Pos (0U)
8039#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos)
8040#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk
8041#define EXTI_IMR1_IM1_Pos (1U)
8042#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos)
8043#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk
8044#define EXTI_IMR1_IM2_Pos (2U)
8045#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos)
8046#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk
8047#define EXTI_IMR1_IM3_Pos (3U)
8048#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos)
8049#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk
8050#define EXTI_IMR1_IM4_Pos (4U)
8051#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos)
8052#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk
8053#define EXTI_IMR1_IM5_Pos (5U)
8054#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos)
8055#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk
8056#define EXTI_IMR1_IM6_Pos (6U)
8057#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos)
8058#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk
8059#define EXTI_IMR1_IM7_Pos (7U)
8060#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos)
8061#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk
8062#define EXTI_IMR1_IM8_Pos (8U)
8063#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos)
8064#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk
8065#define EXTI_IMR1_IM9_Pos (9U)
8066#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos)
8067#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk
8068#define EXTI_IMR1_IM10_Pos (10U)
8069#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos)
8070#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk
8071#define EXTI_IMR1_IM11_Pos (11U)
8072#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos)
8073#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk
8074#define EXTI_IMR1_IM12_Pos (12U)
8075#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos)
8076#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk
8077#define EXTI_IMR1_IM13_Pos (13U)
8078#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos)
8079#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk
8080#define EXTI_IMR1_IM14_Pos (14U)
8081#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos)
8082#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk
8083#define EXTI_IMR1_IM15_Pos (15U)
8084#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos)
8085#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk
8086#define EXTI_IMR1_IM16_Pos (16U)
8087#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos)
8088#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk
8089#define EXTI_IMR1_IM17_Pos (17U)
8090#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos)
8091#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk
8092#define EXTI_IMR1_IM18_Pos (18U)
8093#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos)
8094#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk
8095#define EXTI_IMR1_IM19_Pos (19U)
8096#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos)
8097#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk
8098#define EXTI_IMR1_IM20_Pos (20U)
8099#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos)
8100#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk
8101#define EXTI_IMR1_IM21_Pos (21U)
8102#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos)
8103#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk
8104#define EXTI_IMR1_IM22_Pos (22U)
8105#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos)
8106#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk
8107#define EXTI_IMR1_IM23_Pos (23U)
8108#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos)
8109#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk
8110#define EXTI_IMR1_IM24_Pos (24U)
8111#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos)
8112#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk
8113#define EXTI_IMR1_IM25_Pos (25U)
8114#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos)
8115#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk
8116#define EXTI_IMR1_IM26_Pos (26U)
8117#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos)
8118#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk
8119#define EXTI_IMR1_IM27_Pos (27U)
8120#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos)
8121#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk
8122#define EXTI_IMR1_IM28_Pos (28U)
8123#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos)
8124#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk
8125#define EXTI_IMR1_IM29_Pos (29U)
8126#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos)
8127#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk
8128#define EXTI_IMR1_IM30_Pos (30U)
8129#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos)
8130#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk
8131#define EXTI_IMR1_IM31_Pos (31U)
8132#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos)
8133#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk
8134#define EXTI_IMR1_IM_Pos (0U)
8135#define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)
8136#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk
8138/******************* Bit definition for EXTI_EMR1 register ******************/
8139#define EXTI_EMR1_EM0_Pos (0U)
8140#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos)
8141#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk
8142#define EXTI_EMR1_EM1_Pos (1U)
8143#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos)
8144#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk
8145#define EXTI_EMR1_EM2_Pos (2U)
8146#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos)
8147#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk
8148#define EXTI_EMR1_EM3_Pos (3U)
8149#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos)
8150#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk
8151#define EXTI_EMR1_EM4_Pos (4U)
8152#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos)
8153#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk
8154#define EXTI_EMR1_EM5_Pos (5U)
8155#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos)
8156#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk
8157#define EXTI_EMR1_EM6_Pos (6U)
8158#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos)
8159#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk
8160#define EXTI_EMR1_EM7_Pos (7U)
8161#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos)
8162#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk
8163#define EXTI_EMR1_EM8_Pos (8U)
8164#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos)
8165#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk
8166#define EXTI_EMR1_EM9_Pos (9U)
8167#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos)
8168#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk
8169#define EXTI_EMR1_EM10_Pos (10U)
8170#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos)
8171#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk
8172#define EXTI_EMR1_EM11_Pos (11U)
8173#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos)
8174#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk
8175#define EXTI_EMR1_EM12_Pos (12U)
8176#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos)
8177#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk
8178#define EXTI_EMR1_EM13_Pos (13U)
8179#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos)
8180#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk
8181#define EXTI_EMR1_EM14_Pos (14U)
8182#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos)
8183#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk
8184#define EXTI_EMR1_EM15_Pos (15U)
8185#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos)
8186#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk
8187#define EXTI_EMR1_EM16_Pos (16U)
8188#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos)
8189#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk
8190#define EXTI_EMR1_EM17_Pos (17U)
8191#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos)
8192#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk
8193#define EXTI_EMR1_EM18_Pos (18U)
8194#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos)
8195#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk
8196#define EXTI_EMR1_EM19_Pos (19U)
8197#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos)
8198#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk
8199#define EXTI_EMR1_EM20_Pos (20U)
8200#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos)
8201#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk
8202#define EXTI_EMR1_EM21_Pos (21U)
8203#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos)
8204#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk
8205#define EXTI_EMR1_EM22_Pos (22U)
8206#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos)
8207#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk
8208#define EXTI_EMR1_EM23_Pos (23U)
8209#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos)
8210#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk
8211#define EXTI_EMR1_EM24_Pos (24U)
8212#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos)
8213#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk
8214#define EXTI_EMR1_EM25_Pos (25U)
8215#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos)
8216#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk
8217#define EXTI_EMR1_EM26_Pos (26U)
8218#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos)
8219#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk
8220#define EXTI_EMR1_EM27_Pos (27U)
8221#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos)
8222#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk
8223#define EXTI_EMR1_EM28_Pos (28U)
8224#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos)
8225#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk
8226#define EXTI_EMR1_EM29_Pos (29U)
8227#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos)
8228#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk
8229#define EXTI_EMR1_EM30_Pos (30U)
8230#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos)
8231#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk
8232#define EXTI_EMR1_EM31_Pos (31U)
8233#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos)
8234#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk
8236/****************** Bit definition for EXTI_RTSR1 register ******************/
8237#define EXTI_RTSR1_RT0_Pos (0U)
8238#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos)
8239#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk
8240#define EXTI_RTSR1_RT1_Pos (1U)
8241#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos)
8242#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk
8243#define EXTI_RTSR1_RT2_Pos (2U)
8244#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos)
8245#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk
8246#define EXTI_RTSR1_RT3_Pos (3U)
8247#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos)
8248#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk
8249#define EXTI_RTSR1_RT4_Pos (4U)
8250#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos)
8251#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk
8252#define EXTI_RTSR1_RT5_Pos (5U)
8253#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos)
8254#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk
8255#define EXTI_RTSR1_RT6_Pos (6U)
8256#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos)
8257#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk
8258#define EXTI_RTSR1_RT7_Pos (7U)
8259#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos)
8260#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk
8261#define EXTI_RTSR1_RT8_Pos (8U)
8262#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos)
8263#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk
8264#define EXTI_RTSR1_RT9_Pos (9U)
8265#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos)
8266#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk
8267#define EXTI_RTSR1_RT10_Pos (10U)
8268#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos)
8269#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk
8270#define EXTI_RTSR1_RT11_Pos (11U)
8271#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos)
8272#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk
8273#define EXTI_RTSR1_RT12_Pos (12U)
8274#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos)
8275#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk
8276#define EXTI_RTSR1_RT13_Pos (13U)
8277#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos)
8278#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk
8279#define EXTI_RTSR1_RT14_Pos (14U)
8280#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos)
8281#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk
8282#define EXTI_RTSR1_RT15_Pos (15U)
8283#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos)
8284#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk
8285#define EXTI_RTSR1_RT16_Pos (16U)
8286#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos)
8287#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk
8288#define EXTI_RTSR1_RT18_Pos (18U)
8289#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos)
8290#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk
8291#define EXTI_RTSR1_RT19_Pos (19U)
8292#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos)
8293#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk
8294#define EXTI_RTSR1_RT20_Pos (20U)
8295#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos)
8296#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk
8297#define EXTI_RTSR1_RT21_Pos (21U)
8298#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos)
8299#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk
8300#define EXTI_RTSR1_RT22_Pos (22U)
8301#define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos)
8302#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk
8304/****************** Bit definition for EXTI_FTSR1 register ******************/
8305#define EXTI_FTSR1_FT0_Pos (0U)
8306#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos)
8307#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk
8308#define EXTI_FTSR1_FT1_Pos (1U)
8309#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos)
8310#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk
8311#define EXTI_FTSR1_FT2_Pos (2U)
8312#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos)
8313#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk
8314#define EXTI_FTSR1_FT3_Pos (3U)
8315#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos)
8316#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk
8317#define EXTI_FTSR1_FT4_Pos (4U)
8318#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos)
8319#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk
8320#define EXTI_FTSR1_FT5_Pos (5U)
8321#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos)
8322#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk
8323#define EXTI_FTSR1_FT6_Pos (6U)
8324#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos)
8325#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk
8326#define EXTI_FTSR1_FT7_Pos (7U)
8327#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos)
8328#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk
8329#define EXTI_FTSR1_FT8_Pos (8U)
8330#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos)
8331#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk
8332#define EXTI_FTSR1_FT9_Pos (9U)
8333#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos)
8334#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk
8335#define EXTI_FTSR1_FT10_Pos (10U)
8336#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos)
8337#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk
8338#define EXTI_FTSR1_FT11_Pos (11U)
8339#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos)
8340#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk
8341#define EXTI_FTSR1_FT12_Pos (12U)
8342#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos)
8343#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk
8344#define EXTI_FTSR1_FT13_Pos (13U)
8345#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos)
8346#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk
8347#define EXTI_FTSR1_FT14_Pos (14U)
8348#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos)
8349#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk
8350#define EXTI_FTSR1_FT15_Pos (15U)
8351#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos)
8352#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk
8353#define EXTI_FTSR1_FT16_Pos (16U)
8354#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos)
8355#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk
8356#define EXTI_FTSR1_FT18_Pos (18U)
8357#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos)
8358#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk
8359#define EXTI_FTSR1_FT19_Pos (19U)
8360#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos)
8361#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk
8362#define EXTI_FTSR1_FT20_Pos (20U)
8363#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos)
8364#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk
8365#define EXTI_FTSR1_FT21_Pos (21U)
8366#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos)
8367#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk
8368#define EXTI_FTSR1_FT22_Pos (22U)
8369#define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos)
8370#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk
8372/****************** Bit definition for EXTI_SWIER1 register *****************/
8373#define EXTI_SWIER1_SWI0_Pos (0U)
8374#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos)
8375#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk
8376#define EXTI_SWIER1_SWI1_Pos (1U)
8377#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos)
8378#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk
8379#define EXTI_SWIER1_SWI2_Pos (2U)
8380#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos)
8381#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk
8382#define EXTI_SWIER1_SWI3_Pos (3U)
8383#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos)
8384#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk
8385#define EXTI_SWIER1_SWI4_Pos (4U)
8386#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos)
8387#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk
8388#define EXTI_SWIER1_SWI5_Pos (5U)
8389#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos)
8390#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk
8391#define EXTI_SWIER1_SWI6_Pos (6U)
8392#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos)
8393#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk
8394#define EXTI_SWIER1_SWI7_Pos (7U)
8395#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos)
8396#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk
8397#define EXTI_SWIER1_SWI8_Pos (8U)
8398#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos)
8399#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk
8400#define EXTI_SWIER1_SWI9_Pos (9U)
8401#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos)
8402#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk
8403#define EXTI_SWIER1_SWI10_Pos (10U)
8404#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos)
8405#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk
8406#define EXTI_SWIER1_SWI11_Pos (11U)
8407#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos)
8408#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk
8409#define EXTI_SWIER1_SWI12_Pos (12U)
8410#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos)
8411#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk
8412#define EXTI_SWIER1_SWI13_Pos (13U)
8413#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos)
8414#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk
8415#define EXTI_SWIER1_SWI14_Pos (14U)
8416#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos)
8417#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk
8418#define EXTI_SWIER1_SWI15_Pos (15U)
8419#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos)
8420#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk
8421#define EXTI_SWIER1_SWI16_Pos (16U)
8422#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos)
8423#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk
8424#define EXTI_SWIER1_SWI18_Pos (18U)
8425#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos)
8426#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk
8427#define EXTI_SWIER1_SWI19_Pos (19U)
8428#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos)
8429#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk
8430#define EXTI_SWIER1_SWI20_Pos (20U)
8431#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos)
8432#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk
8433#define EXTI_SWIER1_SWI21_Pos (21U)
8434#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos)
8435#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk
8436#define EXTI_SWIER1_SWI22_Pos (22U)
8437#define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos)
8438#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk
8440/******************* Bit definition for EXTI_PR1 register *******************/
8441#define EXTI_PR1_PIF0_Pos (0U)
8442#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos)
8443#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk
8444#define EXTI_PR1_PIF1_Pos (1U)
8445#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos)
8446#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk
8447#define EXTI_PR1_PIF2_Pos (2U)
8448#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos)
8449#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk
8450#define EXTI_PR1_PIF3_Pos (3U)
8451#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos)
8452#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk
8453#define EXTI_PR1_PIF4_Pos (4U)
8454#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos)
8455#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk
8456#define EXTI_PR1_PIF5_Pos (5U)
8457#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos)
8458#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk
8459#define EXTI_PR1_PIF6_Pos (6U)
8460#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos)
8461#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk
8462#define EXTI_PR1_PIF7_Pos (7U)
8463#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos)
8464#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk
8465#define EXTI_PR1_PIF8_Pos (8U)
8466#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos)
8467#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk
8468#define EXTI_PR1_PIF9_Pos (9U)
8469#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos)
8470#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk
8471#define EXTI_PR1_PIF10_Pos (10U)
8472#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos)
8473#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk
8474#define EXTI_PR1_PIF11_Pos (11U)
8475#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos)
8476#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk
8477#define EXTI_PR1_PIF12_Pos (12U)
8478#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos)
8479#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk
8480#define EXTI_PR1_PIF13_Pos (13U)
8481#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos)
8482#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk
8483#define EXTI_PR1_PIF14_Pos (14U)
8484#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos)
8485#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk
8486#define EXTI_PR1_PIF15_Pos (15U)
8487#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos)
8488#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk
8489#define EXTI_PR1_PIF16_Pos (16U)
8490#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos)
8491#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk
8492#define EXTI_PR1_PIF18_Pos (18U)
8493#define EXTI_PR1_PIF18_Msk (0x1UL << EXTI_PR1_PIF18_Pos)
8494#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk
8495#define EXTI_PR1_PIF19_Pos (19U)
8496#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos)
8497#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk
8498#define EXTI_PR1_PIF20_Pos (20U)
8499#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos)
8500#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk
8501#define EXTI_PR1_PIF21_Pos (21U)
8502#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos)
8503#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk
8504#define EXTI_PR1_PIF22_Pos (22U)
8505#define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos)
8506#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk
8508/******************* Bit definition for EXTI_IMR2 register ******************/
8509#define EXTI_IMR2_IM32_Pos (0U)
8510#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos)
8511#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk
8512#define EXTI_IMR2_IM33_Pos (1U)
8513#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos)
8514#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk
8515#define EXTI_IMR2_IM34_Pos (2U)
8516#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos)
8517#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk
8518#define EXTI_IMR2_IM35_Pos (3U)
8519#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos)
8520#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk
8521#define EXTI_IMR2_IM36_Pos (4U)
8522#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos)
8523#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk
8524#define EXTI_IMR2_IM37_Pos (5U)
8525#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos)
8526#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk
8527#define EXTI_IMR2_IM38_Pos (6U)
8528#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos)
8529#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk
8530#define EXTI_IMR2_IM39_Pos (7U)
8531#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos)
8532#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk
8533#define EXTI_IMR2_IM40_Pos (8U)
8534#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos)
8535#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk
8536#define EXTI_IMR2_IM_Pos (0U)
8537#define EXTI_IMR2_IM_Msk (0x1FFUL << EXTI_IMR2_IM_Pos)
8538#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
8540/******************* Bit definition for EXTI_EMR2 register ******************/
8541#define EXTI_EMR2_EM32_Pos (0U)
8542#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos)
8543#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk
8544#define EXTI_EMR2_EM33_Pos (1U)
8545#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos)
8546#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk
8547#define EXTI_EMR2_EM34_Pos (2U)
8548#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos)
8549#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk
8550#define EXTI_EMR2_EM35_Pos (3U)
8551#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos)
8552#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk
8553#define EXTI_EMR2_EM36_Pos (4U)
8554#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos)
8555#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk
8556#define EXTI_EMR2_EM37_Pos (5U)
8557#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos)
8558#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk
8559#define EXTI_EMR2_EM38_Pos (6U)
8560#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos)
8561#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk
8562#define EXTI_EMR2_EM39_Pos (7U)
8563#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos)
8564#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk
8565#define EXTI_EMR2_EM40_Pos (8U)
8566#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos)
8567#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk
8568#define EXTI_EMR2_EM_Pos (0U)
8569#define EXTI_EMR2_EM_Msk (0x1FFUL << EXTI_EMR2_EM_Pos)
8570#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
8572/****************** Bit definition for EXTI_RTSR2 register ******************/
8573#define EXTI_RTSR2_RT35_Pos (3U)
8574#define EXTI_RTSR2_RT35_Msk (0x1UL << EXTI_RTSR2_RT35_Pos)
8575#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk
8576#define EXTI_RTSR2_RT36_Pos (4U)
8577#define EXTI_RTSR2_RT36_Msk (0x1UL << EXTI_RTSR2_RT36_Pos)
8578#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk
8579#define EXTI_RTSR2_RT37_Pos (5U)
8580#define EXTI_RTSR2_RT37_Msk (0x1UL << EXTI_RTSR2_RT37_Pos)
8581#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk
8582#define EXTI_RTSR2_RT38_Pos (6U)
8583#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos)
8584#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk
8586/****************** Bit definition for EXTI_FTSR2 register ******************/
8587#define EXTI_FTSR2_FT35_Pos (3U)
8588#define EXTI_FTSR2_FT35_Msk (0x1UL << EXTI_FTSR2_FT35_Pos)
8589#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk
8590#define EXTI_FTSR2_FT36_Pos (4U)
8591#define EXTI_FTSR2_FT36_Msk (0x1UL << EXTI_FTSR2_FT36_Pos)
8592#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk
8593#define EXTI_FTSR2_FT37_Pos (5U)
8594#define EXTI_FTSR2_FT37_Msk (0x1UL << EXTI_FTSR2_FT37_Pos)
8595#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk
8596#define EXTI_FTSR2_FT38_Pos (6U)
8597#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos)
8598#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk
8600/****************** Bit definition for EXTI_SWIER2 register *****************/
8601#define EXTI_SWIER2_SWI35_Pos (3U)
8602#define EXTI_SWIER2_SWI35_Msk (0x1UL << EXTI_SWIER2_SWI35_Pos)
8603#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk
8604#define EXTI_SWIER2_SWI36_Pos (4U)
8605#define EXTI_SWIER2_SWI36_Msk (0x1UL << EXTI_SWIER2_SWI36_Pos)
8606#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk
8607#define EXTI_SWIER2_SWI37_Pos (5U)
8608#define EXTI_SWIER2_SWI37_Msk (0x1UL << EXTI_SWIER2_SWI37_Pos)
8609#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk
8610#define EXTI_SWIER2_SWI38_Pos (6U)
8611#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos)
8612#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk
8614/******************* Bit definition for EXTI_PR2 register *******************/
8615#define EXTI_PR2_PIF35_Pos (3U)
8616#define EXTI_PR2_PIF35_Msk (0x1UL << EXTI_PR2_PIF35_Pos)
8617#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk
8618#define EXTI_PR2_PIF36_Pos (4U)
8619#define EXTI_PR2_PIF36_Msk (0x1UL << EXTI_PR2_PIF36_Pos)
8620#define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk
8621#define EXTI_PR2_PIF37_Pos (5U)
8622#define EXTI_PR2_PIF37_Msk (0x1UL << EXTI_PR2_PIF37_Pos)
8623#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk
8624#define EXTI_PR2_PIF38_Pos (6U)
8625#define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos)
8626#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk
8629/******************************************************************************/
8630/* */
8631/* FLASH */
8632/* */
8633/******************************************************************************/
8634/******************* Bits definition for FLASH_ACR register *****************/
8635#define FLASH_ACR_LATENCY_Pos (0U)
8636#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)
8637#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
8638#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
8639#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
8640#define FLASH_ACR_LATENCY_2WS (0x00000002UL)
8641#define FLASH_ACR_LATENCY_3WS (0x00000003UL)
8642#define FLASH_ACR_LATENCY_4WS (0x00000004UL)
8643#define FLASH_ACR_PRFTEN_Pos (8U)
8644#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
8645#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
8646#define FLASH_ACR_ICEN_Pos (9U)
8647#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
8648#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
8649#define FLASH_ACR_DCEN_Pos (10U)
8650#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
8651#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
8652#define FLASH_ACR_ICRST_Pos (11U)
8653#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
8654#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
8655#define FLASH_ACR_DCRST_Pos (12U)
8656#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
8657#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
8658#define FLASH_ACR_RUN_PD_Pos (13U)
8659#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos)
8660#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk
8661#define FLASH_ACR_SLEEP_PD_Pos (14U)
8662#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos)
8663#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk
8665/******************* Bits definition for FLASH_SR register ******************/
8666#define FLASH_SR_EOP_Pos (0U)
8667#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
8668#define FLASH_SR_EOP FLASH_SR_EOP_Msk
8669#define FLASH_SR_OPERR_Pos (1U)
8670#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
8671#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
8672#define FLASH_SR_PROGERR_Pos (3U)
8673#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos)
8674#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
8675#define FLASH_SR_WRPERR_Pos (4U)
8676#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
8677#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
8678#define FLASH_SR_PGAERR_Pos (5U)
8679#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
8680#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
8681#define FLASH_SR_SIZERR_Pos (6U)
8682#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos)
8683#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
8684#define FLASH_SR_PGSERR_Pos (7U)
8685#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
8686#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
8687#define FLASH_SR_MISERR_Pos (8U)
8688#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos)
8689#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
8690#define FLASH_SR_FASTERR_Pos (9U)
8691#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos)
8692#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
8693#define FLASH_SR_RDERR_Pos (14U)
8694#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)
8695#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
8696#define FLASH_SR_OPTVERR_Pos (15U)
8697#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos)
8698#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
8699#define FLASH_SR_BSY_Pos (16U)
8700#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
8701#define FLASH_SR_BSY FLASH_SR_BSY_Msk
8702
8703/******************* Bits definition for FLASH_CR register ******************/
8704#define FLASH_CR_PG_Pos (0U)
8705#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
8706#define FLASH_CR_PG FLASH_CR_PG_Msk
8707#define FLASH_CR_PER_Pos (1U)
8708#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)
8709#define FLASH_CR_PER FLASH_CR_PER_Msk
8710#define FLASH_CR_MER1_Pos (2U)
8711#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos)
8712#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
8713#define FLASH_CR_PNB_Pos (3U)
8714#define FLASH_CR_PNB_Msk (0xFFUL << FLASH_CR_PNB_Pos)
8715#define FLASH_CR_PNB FLASH_CR_PNB_Msk
8716#define FLASH_CR_BKER_Pos (11U)
8717#define FLASH_CR_BKER_Msk (0x1UL << FLASH_CR_BKER_Pos)
8718#define FLASH_CR_BKER FLASH_CR_BKER_Msk
8719#define FLASH_CR_MER2_Pos (15U)
8720#define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos)
8721#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
8722#define FLASH_CR_STRT_Pos (16U)
8723#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
8724#define FLASH_CR_STRT FLASH_CR_STRT_Msk
8725#define FLASH_CR_OPTSTRT_Pos (17U)
8726#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos)
8727#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
8728#define FLASH_CR_FSTPG_Pos (18U)
8729#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos)
8730#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
8731#define FLASH_CR_EOPIE_Pos (24U)
8732#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
8733#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
8734#define FLASH_CR_ERRIE_Pos (25U)
8735#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
8736#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
8737#define FLASH_CR_RDERRIE_Pos (26U)
8738#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos)
8739#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
8740#define FLASH_CR_OBL_LAUNCH_Pos (27U)
8741#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)
8742#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
8743#define FLASH_CR_OPTLOCK_Pos (30U)
8744#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos)
8745#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
8746#define FLASH_CR_LOCK_Pos (31U)
8747#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
8748#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
8749
8750/******************* Bits definition for FLASH_ECCR register ***************/
8751#define FLASH_ECCR_ADDR_ECC_Pos (0U)
8752#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)
8753#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
8754#define FLASH_ECCR_BK_ECC_Pos (19U)
8755#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos)
8756#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
8757#define FLASH_ECCR_SYSF_ECC_Pos (20U)
8758#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)
8759#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
8760#define FLASH_ECCR_ECCIE_Pos (24U)
8761#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos)
8762#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
8763#define FLASH_ECCR_ECCC_Pos (30U)
8764#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos)
8765#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
8766#define FLASH_ECCR_ECCD_Pos (31U)
8767#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos)
8768#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
8769
8770/******************* Bits definition for FLASH_OPTR register ***************/
8771#define FLASH_OPTR_RDP_Pos (0U)
8772#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos)
8773#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
8774#define FLASH_OPTR_BOR_LEV_Pos (8U)
8775#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos)
8776#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
8777#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos)
8778#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos)
8779#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos)
8780#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos)
8781#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos)
8782#define FLASH_OPTR_nRST_STOP_Pos (12U)
8783#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos)
8784#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
8785#define FLASH_OPTR_nRST_STDBY_Pos (13U)
8786#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)
8787#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
8788#define FLASH_OPTR_nRST_SHDW_Pos (14U)
8789#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)
8790#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
8791#define FLASH_OPTR_IWDG_SW_Pos (16U)
8792#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos)
8793#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
8794#define FLASH_OPTR_IWDG_STOP_Pos (17U)
8795#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)
8796#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
8797#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
8798#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)
8799#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
8800#define FLASH_OPTR_WWDG_SW_Pos (19U)
8801#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos)
8802#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
8803#define FLASH_OPTR_BFB2_Pos (20U)
8804#define FLASH_OPTR_BFB2_Msk (0x1UL << FLASH_OPTR_BFB2_Pos)
8805#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
8806#define FLASH_OPTR_DUALBANK_Pos (21U)
8807#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos)
8808#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk
8809#define FLASH_OPTR_nBOOT1_Pos (23U)
8810#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos)
8811#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
8812#define FLASH_OPTR_SRAM2_PE_Pos (24U)
8813#define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos)
8814#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
8815#define FLASH_OPTR_SRAM2_RST_Pos (25U)
8816#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos)
8817#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
8818#define FLASH_OPTR_nSWBOOT0_Pos (26U)
8819#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)
8820#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
8821#define FLASH_OPTR_nBOOT0_Pos (27U)
8822#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos)
8823#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
8824
8825/****************** Bits definition for FLASH_PCROP1SR register **********/
8826#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
8827#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0xFFFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)
8828#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
8829
8830/****************** Bits definition for FLASH_PCROP1ER register ***********/
8831#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
8832#define FLASH_PCROP1ER_PCROP1_END_Msk (0xFFFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)
8833#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
8834#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
8835#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)
8836#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
8837
8838/****************** Bits definition for FLASH_WRP1AR register ***************/
8839#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
8840#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos)
8841#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
8842#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
8843#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos)
8844#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
8845
8846/****************** Bits definition for FLASH_WRPB1R register ***************/
8847#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
8848#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos)
8849#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
8850#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
8851#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos)
8852#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
8853
8854/****************** Bits definition for FLASH_PCROP2SR register **********/
8855#define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U)
8856#define FLASH_PCROP2SR_PCROP2_STRT_Msk (0xFFFFUL << FLASH_PCROP2SR_PCROP2_STRT_Pos)
8857#define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk
8858
8859/****************** Bits definition for FLASH_PCROP2ER register ***********/
8860#define FLASH_PCROP2ER_PCROP2_END_Pos (0U)
8861#define FLASH_PCROP2ER_PCROP2_END_Msk (0xFFFFUL << FLASH_PCROP2ER_PCROP2_END_Pos)
8862#define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk
8863
8864/****************** Bits definition for FLASH_WRP2AR register ***************/
8865#define FLASH_WRP2AR_WRP2A_STRT_Pos (0U)
8866#define FLASH_WRP2AR_WRP2A_STRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_STRT_Pos)
8867#define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk
8868#define FLASH_WRP2AR_WRP2A_END_Pos (16U)
8869#define FLASH_WRP2AR_WRP2A_END_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_END_Pos)
8870#define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk
8871
8872/****************** Bits definition for FLASH_WRP2BR register ***************/
8873#define FLASH_WRP2BR_WRP2B_STRT_Pos (0U)
8874#define FLASH_WRP2BR_WRP2B_STRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_STRT_Pos)
8875#define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk
8876#define FLASH_WRP2BR_WRP2B_END_Pos (16U)
8877#define FLASH_WRP2BR_WRP2B_END_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_END_Pos)
8878#define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk
8879
8880
8881/******************************************************************************/
8882/* */
8883/* Flexible Memory Controller */
8884/* */
8885/******************************************************************************/
8886/****************** Bit definition for FMC_BCR1 register *******************/
8887#define FMC_BCR1_CCLKEN_Pos (20U)
8888#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
8889#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
8890#define FMC_BCR1_WFDIS_Pos (21U)
8891#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos)
8892#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk
8894/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
8895#define FMC_BCRx_MBKEN_Pos (0U)
8896#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos)
8897#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk
8898#define FMC_BCRx_MUXEN_Pos (1U)
8899#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos)
8900#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk
8902#define FMC_BCRx_MTYP_Pos (2U)
8903#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos)
8904#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk
8905#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos)
8906#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos)
8908#define FMC_BCRx_MWID_Pos (4U)
8909#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos)
8910#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk
8911#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos)
8912#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos)
8914#define FMC_BCRx_FACCEN_Pos (6U)
8915#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos)
8916#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk
8917#define FMC_BCRx_BURSTEN_Pos (8U)
8918#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos)
8919#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk
8920#define FMC_BCRx_WAITPOL_Pos (9U)
8921#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos)
8922#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk
8923#define FMC_BCRx_WAITCFG_Pos (11U)
8924#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos)
8925#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk
8926#define FMC_BCRx_WREN_Pos (12U)
8927#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos)
8928#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk
8929#define FMC_BCRx_WAITEN_Pos (13U)
8930#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos)
8931#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk
8932#define FMC_BCRx_EXTMOD_Pos (14U)
8933#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos)
8934#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk
8935#define FMC_BCRx_ASYNCWAIT_Pos (15U)
8936#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)
8937#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk
8939#define FMC_BCRx_CPSIZE_Pos (16U)
8940#define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos)
8941#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk
8942#define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos)
8943#define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos)
8944#define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos)
8946#define FMC_BCRx_CBURSTRW_Pos (19U)
8947#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos)
8948#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk
8950/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
8951#define FMC_BTRx_ADDSET_Pos (0U)
8952#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos)
8953#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk
8954#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos)
8955#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos)
8956#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos)
8957#define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos)
8959#define FMC_BTRx_ADDHLD_Pos (4U)
8960#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos)
8961#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk
8962#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos)
8963#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos)
8964#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos)
8965#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos)
8967#define FMC_BTRx_DATAST_Pos (8U)
8968#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos)
8969#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk
8970#define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos)
8971#define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos)
8972#define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos)
8973#define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos)
8974#define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos)
8975#define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos)
8976#define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos)
8977#define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos)
8979#define FMC_BTRx_BUSTURN_Pos (16U)
8980#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos)
8981#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk
8982#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos)
8983#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos)
8984#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos)
8985#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos)
8987#define FMC_BTRx_CLKDIV_Pos (20U)
8988#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos)
8989#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk
8990#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos)
8991#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos)
8992#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos)
8993#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos)
8995#define FMC_BTRx_DATLAT_Pos (24U)
8996#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos)
8997#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk
8998#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos)
8999#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos)
9000#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos)
9001#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos)
9003#define FMC_BTRx_ACCMOD_Pos (28U)
9004#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos)
9005#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk
9006#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos)
9007#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos)
9009/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
9010#define FMC_BWTRx_ADDSET_Pos (0U)
9011#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos)
9012#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk
9013#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos)
9014#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos)
9015#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos)
9016#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos)
9018#define FMC_BWTRx_ADDHLD_Pos (4U)
9019#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos)
9020#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk
9021#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos)
9022#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos)
9023#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos)
9024#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos)
9026#define FMC_BWTRx_DATAST_Pos (8U)
9027#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos)
9028#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk
9029#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos)
9030#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos)
9031#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos)
9032#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos)
9033#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos)
9034#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos)
9035#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos)
9036#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos)
9038#define FMC_BWTRx_BUSTURN_Pos (16U)
9039#define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos)
9040#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk
9041#define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos)
9042#define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos)
9043#define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos)
9044#define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos)
9046#define FMC_BWTRx_ACCMOD_Pos (28U)
9047#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos)
9048#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk
9049#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos)
9050#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos)
9052/****************** Bit definition for FMC_PCR register ********************/
9053#define FMC_PCR_PWAITEN_Pos (1U)
9054#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
9055#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
9056#define FMC_PCR_PBKEN_Pos (2U)
9057#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
9058#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
9059#define FMC_PCR_PTYP_Pos (3U)
9060#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos)
9061#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk
9063#define FMC_PCR_PWID_Pos (4U)
9064#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
9065#define FMC_PCR_PWID FMC_PCR_PWID_Msk
9066#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
9067#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
9069#define FMC_PCR_ECCEN_Pos (6U)
9070#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
9071#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
9073#define FMC_PCR_TCLR_Pos (9U)
9074#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
9075#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
9076#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
9077#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
9078#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
9079#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
9081#define FMC_PCR_TAR_Pos (13U)
9082#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
9083#define FMC_PCR_TAR FMC_PCR_TAR_Msk
9084#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
9085#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
9086#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
9087#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
9089#define FMC_PCR_ECCPS_Pos (17U)
9090#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
9091#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
9092#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
9093#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
9094#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
9096/******************* Bit definition for FMC_SR register ********************/
9097#define FMC_SR_IRS_Pos (0U)
9098#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
9099#define FMC_SR_IRS FMC_SR_IRS_Msk
9100#define FMC_SR_ILS_Pos (1U)
9101#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
9102#define FMC_SR_ILS FMC_SR_ILS_Msk
9103#define FMC_SR_IFS_Pos (2U)
9104#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
9105#define FMC_SR_IFS FMC_SR_IFS_Msk
9106#define FMC_SR_IREN_Pos (3U)
9107#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
9108#define FMC_SR_IREN FMC_SR_IREN_Msk
9109#define FMC_SR_ILEN_Pos (4U)
9110#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
9111#define FMC_SR_ILEN FMC_SR_ILEN_Msk
9112#define FMC_SR_IFEN_Pos (5U)
9113#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
9114#define FMC_SR_IFEN FMC_SR_IFEN_Msk
9115#define FMC_SR_FEMPT_Pos (6U)
9116#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
9117#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
9119/****************** Bit definition for FMC_PMEM register ******************/
9120#define FMC_PMEM_MEMSET_Pos (0U)
9121#define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos)
9122#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk
9123#define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos)
9124#define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos)
9125#define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos)
9126#define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos)
9127#define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos)
9128#define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos)
9129#define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos)
9130#define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos)
9132#define FMC_PMEM_MEMWAIT_Pos (8U)
9133#define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos)
9134#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk
9135#define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos)
9136#define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos)
9137#define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos)
9138#define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos)
9139#define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos)
9140#define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos)
9141#define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos)
9142#define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos)
9144#define FMC_PMEM_MEMHOLD_Pos (16U)
9145#define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos)
9146#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk
9147#define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos)
9148#define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos)
9149#define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos)
9150#define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos)
9151#define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos)
9152#define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos)
9153#define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos)
9154#define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos)
9156#define FMC_PMEM_MEMHIZ_Pos (24U)
9157#define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos)
9158#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk
9159#define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos)
9160#define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos)
9161#define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos)
9162#define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos)
9163#define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos)
9164#define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos)
9165#define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos)
9166#define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos)
9168/****************** Bit definition for FMC_PATT register *******************/
9169#define FMC_PATT_ATTSET_Pos (0U)
9170#define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos)
9171#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk
9172#define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos)
9173#define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos)
9174#define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos)
9175#define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos)
9176#define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos)
9177#define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos)
9178#define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos)
9179#define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos)
9181#define FMC_PATT_ATTWAIT_Pos (8U)
9182#define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos)
9183#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk
9184#define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos)
9185#define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos)
9186#define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos)
9187#define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos)
9188#define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos)
9189#define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos)
9190#define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos)
9191#define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos)
9193#define FMC_PATT_ATTHOLD_Pos (16U)
9194#define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos)
9195#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk
9196#define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos)
9197#define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos)
9198#define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos)
9199#define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos)
9200#define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos)
9201#define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos)
9202#define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos)
9203#define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos)
9205#define FMC_PATT_ATTHIZ_Pos (24U)
9206#define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos)
9207#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk
9208#define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos)
9209#define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos)
9210#define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos)
9211#define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos)
9212#define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos)
9213#define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos)
9214#define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos)
9215#define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos)
9217/****************** Bit definition for FMC_ECCR register *******************/
9218#define FMC_ECCR_ECC_Pos (0U)
9219#define FMC_ECCR_ECC_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC_Pos)
9220#define FMC_ECCR_ECC FMC_ECCR_ECC_Msk
9222/******************************************************************************/
9223/* */
9224/* General Purpose IOs (GPIO) */
9225/* */
9226/******************************************************************************/
9227/****************** Bits definition for GPIO_MODER register *****************/
9228#define GPIO_MODER_MODE0_Pos (0U)
9229#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)
9230#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
9231#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)
9232#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)
9233#define GPIO_MODER_MODE1_Pos (2U)
9234#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)
9235#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
9236#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)
9237#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)
9238#define GPIO_MODER_MODE2_Pos (4U)
9239#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)
9240#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
9241#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)
9242#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)
9243#define GPIO_MODER_MODE3_Pos (6U)
9244#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)
9245#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
9246#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)
9247#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)
9248#define GPIO_MODER_MODE4_Pos (8U)
9249#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)
9250#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
9251#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)
9252#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)
9253#define GPIO_MODER_MODE5_Pos (10U)
9254#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)
9255#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
9256#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)
9257#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)
9258#define GPIO_MODER_MODE6_Pos (12U)
9259#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)
9260#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
9261#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)
9262#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)
9263#define GPIO_MODER_MODE7_Pos (14U)
9264#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)
9265#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
9266#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)
9267#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)
9268#define GPIO_MODER_MODE8_Pos (16U)
9269#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)
9270#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
9271#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)
9272#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)
9273#define GPIO_MODER_MODE9_Pos (18U)
9274#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)
9275#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
9276#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)
9277#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)
9278#define GPIO_MODER_MODE10_Pos (20U)
9279#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)
9280#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
9281#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)
9282#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)
9283#define GPIO_MODER_MODE11_Pos (22U)
9284#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)
9285#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
9286#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)
9287#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)
9288#define GPIO_MODER_MODE12_Pos (24U)
9289#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)
9290#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
9291#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)
9292#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)
9293#define GPIO_MODER_MODE13_Pos (26U)
9294#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)
9295#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
9296#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)
9297#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)
9298#define GPIO_MODER_MODE14_Pos (28U)
9299#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)
9300#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
9301#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)
9302#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)
9303#define GPIO_MODER_MODE15_Pos (30U)
9304#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)
9305#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
9306#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)
9307#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)
9309/* Legacy defines */
9310#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
9311#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
9312#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
9313#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
9314#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
9315#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
9316#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
9317#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
9318#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
9319#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
9320#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
9321#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
9322#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
9323#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
9324#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
9325#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
9326#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
9327#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
9328#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
9329#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
9330#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
9331#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
9332#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
9333#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
9334#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
9335#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
9336#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
9337#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
9338#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
9339#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
9340#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
9341#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
9342#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
9343#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
9344#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
9345#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
9346#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
9347#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
9348#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
9349#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
9350#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
9351#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
9352#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
9353#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
9354#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
9355#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
9356#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
9357#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
9358
9359/****************** Bits definition for GPIO_OTYPER register ****************/
9360#define GPIO_OTYPER_OT0_Pos (0U)
9361#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
9362#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
9363#define GPIO_OTYPER_OT1_Pos (1U)
9364#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
9365#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
9366#define GPIO_OTYPER_OT2_Pos (2U)
9367#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
9368#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
9369#define GPIO_OTYPER_OT3_Pos (3U)
9370#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
9371#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
9372#define GPIO_OTYPER_OT4_Pos (4U)
9373#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
9374#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
9375#define GPIO_OTYPER_OT5_Pos (5U)
9376#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
9377#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
9378#define GPIO_OTYPER_OT6_Pos (6U)
9379#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
9380#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
9381#define GPIO_OTYPER_OT7_Pos (7U)
9382#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
9383#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
9384#define GPIO_OTYPER_OT8_Pos (8U)
9385#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
9386#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
9387#define GPIO_OTYPER_OT9_Pos (9U)
9388#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
9389#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
9390#define GPIO_OTYPER_OT10_Pos (10U)
9391#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
9392#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
9393#define GPIO_OTYPER_OT11_Pos (11U)
9394#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
9395#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
9396#define GPIO_OTYPER_OT12_Pos (12U)
9397#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
9398#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
9399#define GPIO_OTYPER_OT13_Pos (13U)
9400#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
9401#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
9402#define GPIO_OTYPER_OT14_Pos (14U)
9403#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
9404#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
9405#define GPIO_OTYPER_OT15_Pos (15U)
9406#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
9407#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
9408
9409/* Legacy defines */
9410#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
9411#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
9412#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
9413#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
9414#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
9415#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
9416#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
9417#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
9418#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
9419#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
9420#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
9421#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
9422#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
9423#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
9424#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
9425#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
9426
9427/****************** Bits definition for GPIO_OSPEEDR register ***************/
9428#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
9429#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
9430#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
9431#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
9432#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
9433#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
9434#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
9435#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
9436#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
9437#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
9438#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
9439#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
9440#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
9441#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
9442#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
9443#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
9444#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
9445#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
9446#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
9447#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
9448#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
9449#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
9450#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
9451#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
9452#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
9453#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
9454#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
9455#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
9456#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
9457#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
9458#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
9459#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
9460#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
9461#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
9462#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
9463#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
9464#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
9465#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
9466#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
9467#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
9468#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
9469#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
9470#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
9471#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
9472#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
9473#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
9474#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
9475#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
9476#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
9477#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
9478#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
9479#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
9480#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
9481#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
9482#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
9483#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
9484#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
9485#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
9486#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
9487#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
9488#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
9489#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
9490#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
9491#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
9492#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
9493#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
9494#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
9495#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
9496#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
9497#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
9498#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
9499#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
9500#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
9501#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
9502#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
9503#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
9504#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
9505#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
9506#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
9507#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
9509/* Legacy defines */
9510#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
9511#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
9512#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
9513#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
9514#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
9515#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
9516#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
9517#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
9518#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
9519#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
9520#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
9521#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
9522#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
9523#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
9524#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
9525#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
9526#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
9527#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
9528#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
9529#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
9530#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
9531#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
9532#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
9533#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
9534#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
9535#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
9536#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
9537#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
9538#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
9539#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
9540#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
9541#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
9542#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
9543#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
9544#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
9545#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
9546#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
9547#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
9548#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
9549#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
9550#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
9551#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
9552#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
9553#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
9554#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
9555#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
9556#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
9557#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
9558
9559/****************** Bits definition for GPIO_PUPDR register *****************/
9560#define GPIO_PUPDR_PUPD0_Pos (0U)
9561#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
9562#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
9563#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
9564#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
9565#define GPIO_PUPDR_PUPD1_Pos (2U)
9566#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
9567#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
9568#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
9569#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
9570#define GPIO_PUPDR_PUPD2_Pos (4U)
9571#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
9572#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
9573#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
9574#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
9575#define GPIO_PUPDR_PUPD3_Pos (6U)
9576#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
9577#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
9578#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
9579#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
9580#define GPIO_PUPDR_PUPD4_Pos (8U)
9581#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
9582#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
9583#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
9584#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
9585#define GPIO_PUPDR_PUPD5_Pos (10U)
9586#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
9587#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
9588#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
9589#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
9590#define GPIO_PUPDR_PUPD6_Pos (12U)
9591#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
9592#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
9593#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
9594#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
9595#define GPIO_PUPDR_PUPD7_Pos (14U)
9596#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
9597#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
9598#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
9599#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
9600#define GPIO_PUPDR_PUPD8_Pos (16U)
9601#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
9602#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
9603#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
9604#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
9605#define GPIO_PUPDR_PUPD9_Pos (18U)
9606#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
9607#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
9608#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
9609#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
9610#define GPIO_PUPDR_PUPD10_Pos (20U)
9611#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
9612#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
9613#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
9614#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
9615#define GPIO_PUPDR_PUPD11_Pos (22U)
9616#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
9617#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
9618#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
9619#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
9620#define GPIO_PUPDR_PUPD12_Pos (24U)
9621#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
9622#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
9623#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
9624#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
9625#define GPIO_PUPDR_PUPD13_Pos (26U)
9626#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
9627#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
9628#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
9629#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
9630#define GPIO_PUPDR_PUPD14_Pos (28U)
9631#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
9632#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
9633#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
9634#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
9635#define GPIO_PUPDR_PUPD15_Pos (30U)
9636#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
9637#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
9638#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
9639#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
9641/* Legacy defines */
9642#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
9643#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
9644#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
9645#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
9646#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
9647#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
9648#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
9649#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
9650#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
9651#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
9652#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
9653#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
9654#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
9655#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
9656#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
9657#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
9658#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
9659#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
9660#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
9661#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
9662#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
9663#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
9664#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
9665#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
9666#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
9667#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
9668#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
9669#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
9670#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
9671#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
9672#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
9673#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
9674#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
9675#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
9676#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
9677#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
9678#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
9679#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
9680#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
9681#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
9682#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
9683#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
9684#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
9685#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
9686#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
9687#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
9688#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
9689#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
9690
9691/****************** Bits definition for GPIO_IDR register *******************/
9692#define GPIO_IDR_ID0_Pos (0U)
9693#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
9694#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
9695#define GPIO_IDR_ID1_Pos (1U)
9696#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
9697#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
9698#define GPIO_IDR_ID2_Pos (2U)
9699#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
9700#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
9701#define GPIO_IDR_ID3_Pos (3U)
9702#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
9703#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
9704#define GPIO_IDR_ID4_Pos (4U)
9705#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
9706#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
9707#define GPIO_IDR_ID5_Pos (5U)
9708#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
9709#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
9710#define GPIO_IDR_ID6_Pos (6U)
9711#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
9712#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
9713#define GPIO_IDR_ID7_Pos (7U)
9714#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
9715#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
9716#define GPIO_IDR_ID8_Pos (8U)
9717#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
9718#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
9719#define GPIO_IDR_ID9_Pos (9U)
9720#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
9721#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
9722#define GPIO_IDR_ID10_Pos (10U)
9723#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
9724#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
9725#define GPIO_IDR_ID11_Pos (11U)
9726#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
9727#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
9728#define GPIO_IDR_ID12_Pos (12U)
9729#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
9730#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
9731#define GPIO_IDR_ID13_Pos (13U)
9732#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
9733#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
9734#define GPIO_IDR_ID14_Pos (14U)
9735#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
9736#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
9737#define GPIO_IDR_ID15_Pos (15U)
9738#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
9739#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
9740
9741/* Legacy defines */
9742#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
9743#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
9744#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
9745#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
9746#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
9747#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
9748#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
9749#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
9750#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
9751#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
9752#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
9753#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
9754#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
9755#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
9756#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
9757#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
9758
9759/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
9760#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
9761#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
9762#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
9763#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
9764#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
9765#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
9766#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
9767#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
9768#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
9769#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
9770#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
9771#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
9772#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
9773#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
9774#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
9775#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
9776
9777/****************** Bits definition for GPIO_ODR register *******************/
9778#define GPIO_ODR_OD0_Pos (0U)
9779#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
9780#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
9781#define GPIO_ODR_OD1_Pos (1U)
9782#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
9783#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
9784#define GPIO_ODR_OD2_Pos (2U)
9785#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
9786#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
9787#define GPIO_ODR_OD3_Pos (3U)
9788#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
9789#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
9790#define GPIO_ODR_OD4_Pos (4U)
9791#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
9792#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
9793#define GPIO_ODR_OD5_Pos (5U)
9794#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
9795#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
9796#define GPIO_ODR_OD6_Pos (6U)
9797#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
9798#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
9799#define GPIO_ODR_OD7_Pos (7U)
9800#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
9801#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
9802#define GPIO_ODR_OD8_Pos (8U)
9803#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
9804#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
9805#define GPIO_ODR_OD9_Pos (9U)
9806#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
9807#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
9808#define GPIO_ODR_OD10_Pos (10U)
9809#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
9810#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
9811#define GPIO_ODR_OD11_Pos (11U)
9812#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
9813#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
9814#define GPIO_ODR_OD12_Pos (12U)
9815#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
9816#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
9817#define GPIO_ODR_OD13_Pos (13U)
9818#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
9819#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
9820#define GPIO_ODR_OD14_Pos (14U)
9821#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
9822#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
9823#define GPIO_ODR_OD15_Pos (15U)
9824#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
9825#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
9826
9827/* Legacy defines */
9828#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
9829#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
9830#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
9831#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
9832#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
9833#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
9834#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
9835#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
9836#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
9837#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
9838#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
9839#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
9840#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
9841#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
9842#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
9843#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
9844
9845/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
9846#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
9847#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
9848#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
9849#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
9850#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
9851#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
9852#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
9853#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
9854#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
9855#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
9856#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
9857#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
9858#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
9859#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
9860#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
9861#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
9862
9863/****************** Bits definition for GPIO_BSRR register ******************/
9864#define GPIO_BSRR_BS0_Pos (0U)
9865#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
9866#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
9867#define GPIO_BSRR_BS1_Pos (1U)
9868#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
9869#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
9870#define GPIO_BSRR_BS2_Pos (2U)
9871#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
9872#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
9873#define GPIO_BSRR_BS3_Pos (3U)
9874#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
9875#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
9876#define GPIO_BSRR_BS4_Pos (4U)
9877#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
9878#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
9879#define GPIO_BSRR_BS5_Pos (5U)
9880#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
9881#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
9882#define GPIO_BSRR_BS6_Pos (6U)
9883#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
9884#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
9885#define GPIO_BSRR_BS7_Pos (7U)
9886#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
9887#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
9888#define GPIO_BSRR_BS8_Pos (8U)
9889#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
9890#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
9891#define GPIO_BSRR_BS9_Pos (9U)
9892#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
9893#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
9894#define GPIO_BSRR_BS10_Pos (10U)
9895#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
9896#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
9897#define GPIO_BSRR_BS11_Pos (11U)
9898#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
9899#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
9900#define GPIO_BSRR_BS12_Pos (12U)
9901#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
9902#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
9903#define GPIO_BSRR_BS13_Pos (13U)
9904#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
9905#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
9906#define GPIO_BSRR_BS14_Pos (14U)
9907#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
9908#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
9909#define GPIO_BSRR_BS15_Pos (15U)
9910#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
9911#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
9912#define GPIO_BSRR_BR0_Pos (16U)
9913#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
9914#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
9915#define GPIO_BSRR_BR1_Pos (17U)
9916#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
9917#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
9918#define GPIO_BSRR_BR2_Pos (18U)
9919#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
9920#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
9921#define GPIO_BSRR_BR3_Pos (19U)
9922#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
9923#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
9924#define GPIO_BSRR_BR4_Pos (20U)
9925#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
9926#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
9927#define GPIO_BSRR_BR5_Pos (21U)
9928#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
9929#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
9930#define GPIO_BSRR_BR6_Pos (22U)
9931#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
9932#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
9933#define GPIO_BSRR_BR7_Pos (23U)
9934#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
9935#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
9936#define GPIO_BSRR_BR8_Pos (24U)
9937#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
9938#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
9939#define GPIO_BSRR_BR9_Pos (25U)
9940#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
9941#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
9942#define GPIO_BSRR_BR10_Pos (26U)
9943#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
9944#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
9945#define GPIO_BSRR_BR11_Pos (27U)
9946#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
9947#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
9948#define GPIO_BSRR_BR12_Pos (28U)
9949#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
9950#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
9951#define GPIO_BSRR_BR13_Pos (29U)
9952#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
9953#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
9954#define GPIO_BSRR_BR14_Pos (30U)
9955#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
9956#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
9957#define GPIO_BSRR_BR15_Pos (31U)
9958#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
9959#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
9960
9961/* Legacy defines */
9962#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
9963#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
9964#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
9965#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
9966#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
9967#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
9968#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
9969#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
9970#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
9971#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
9972#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
9973#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
9974#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
9975#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
9976#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
9977#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
9978#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
9979#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
9980#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
9981#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
9982#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
9983#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
9984#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
9985#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
9986#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
9987#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
9988#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
9989#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
9990#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
9991#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
9992#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
9993#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
9994
9995/****************** Bit definition for GPIO_LCKR register *********************/
9996#define GPIO_LCKR_LCK0_Pos (0U)
9997#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
9998#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
9999#define GPIO_LCKR_LCK1_Pos (1U)
10000#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
10001#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
10002#define GPIO_LCKR_LCK2_Pos (2U)
10003#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
10004#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
10005#define GPIO_LCKR_LCK3_Pos (3U)
10006#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
10007#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
10008#define GPIO_LCKR_LCK4_Pos (4U)
10009#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
10010#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
10011#define GPIO_LCKR_LCK5_Pos (5U)
10012#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
10013#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
10014#define GPIO_LCKR_LCK6_Pos (6U)
10015#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
10016#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
10017#define GPIO_LCKR_LCK7_Pos (7U)
10018#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
10019#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
10020#define GPIO_LCKR_LCK8_Pos (8U)
10021#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
10022#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
10023#define GPIO_LCKR_LCK9_Pos (9U)
10024#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
10025#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
10026#define GPIO_LCKR_LCK10_Pos (10U)
10027#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
10028#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
10029#define GPIO_LCKR_LCK11_Pos (11U)
10030#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
10031#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
10032#define GPIO_LCKR_LCK12_Pos (12U)
10033#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
10034#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
10035#define GPIO_LCKR_LCK13_Pos (13U)
10036#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
10037#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
10038#define GPIO_LCKR_LCK14_Pos (14U)
10039#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
10040#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
10041#define GPIO_LCKR_LCK15_Pos (15U)
10042#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
10043#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
10044#define GPIO_LCKR_LCKK_Pos (16U)
10045#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
10046#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
10047
10048/****************** Bit definition for GPIO_AFRL register *********************/
10049#define GPIO_AFRL_AFSEL0_Pos (0U)
10050#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
10051#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
10052#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
10053#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
10054#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
10055#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
10056#define GPIO_AFRL_AFSEL1_Pos (4U)
10057#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
10058#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
10059#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
10060#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
10061#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
10062#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
10063#define GPIO_AFRL_AFSEL2_Pos (8U)
10064#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
10065#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
10066#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
10067#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
10068#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
10069#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
10070#define GPIO_AFRL_AFSEL3_Pos (12U)
10071#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
10072#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
10073#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
10074#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
10075#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
10076#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
10077#define GPIO_AFRL_AFSEL4_Pos (16U)
10078#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
10079#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
10080#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
10081#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
10082#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
10083#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
10084#define GPIO_AFRL_AFSEL5_Pos (20U)
10085#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
10086#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
10087#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
10088#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
10089#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
10090#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
10091#define GPIO_AFRL_AFSEL6_Pos (24U)
10092#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
10093#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
10094#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
10095#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
10096#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
10097#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
10098#define GPIO_AFRL_AFSEL7_Pos (28U)
10099#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
10100#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
10101#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
10102#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
10103#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
10104#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
10106/* Legacy defines */
10107#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
10108#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
10109#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
10110#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
10111#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
10112#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
10113#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
10114#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
10115
10116/****************** Bit definition for GPIO_AFRH register *********************/
10117#define GPIO_AFRH_AFSEL8_Pos (0U)
10118#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
10119#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
10120#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
10121#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
10122#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
10123#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
10124#define GPIO_AFRH_AFSEL9_Pos (4U)
10125#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
10126#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
10127#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
10128#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
10129#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
10130#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
10131#define GPIO_AFRH_AFSEL10_Pos (8U)
10132#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
10133#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
10134#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
10135#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
10136#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
10137#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
10138#define GPIO_AFRH_AFSEL11_Pos (12U)
10139#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
10140#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
10141#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
10142#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
10143#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
10144#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
10145#define GPIO_AFRH_AFSEL12_Pos (16U)
10146#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
10147#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
10148#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
10149#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
10150#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
10151#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
10152#define GPIO_AFRH_AFSEL13_Pos (20U)
10153#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
10154#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
10155#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
10156#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
10157#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
10158#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
10159#define GPIO_AFRH_AFSEL14_Pos (24U)
10160#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
10161#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
10162#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
10163#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
10164#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
10165#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
10166#define GPIO_AFRH_AFSEL15_Pos (28U)
10167#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
10168#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
10169#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
10170#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
10171#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
10172#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
10174/* Legacy defines */
10175#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
10176#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
10177#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
10178#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
10179#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
10180#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
10181#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
10182#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
10183
10184/****************** Bits definition for GPIO_BRR register ******************/
10185#define GPIO_BRR_BR0_Pos (0U)
10186#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos)
10187#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
10188#define GPIO_BRR_BR1_Pos (1U)
10189#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos)
10190#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
10191#define GPIO_BRR_BR2_Pos (2U)
10192#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos)
10193#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
10194#define GPIO_BRR_BR3_Pos (3U)
10195#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos)
10196#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
10197#define GPIO_BRR_BR4_Pos (4U)
10198#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos)
10199#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
10200#define GPIO_BRR_BR5_Pos (5U)
10201#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos)
10202#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
10203#define GPIO_BRR_BR6_Pos (6U)
10204#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos)
10205#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
10206#define GPIO_BRR_BR7_Pos (7U)
10207#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos)
10208#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
10209#define GPIO_BRR_BR8_Pos (8U)
10210#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos)
10211#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
10212#define GPIO_BRR_BR9_Pos (9U)
10213#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos)
10214#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
10215#define GPIO_BRR_BR10_Pos (10U)
10216#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos)
10217#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
10218#define GPIO_BRR_BR11_Pos (11U)
10219#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos)
10220#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
10221#define GPIO_BRR_BR12_Pos (12U)
10222#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos)
10223#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
10224#define GPIO_BRR_BR13_Pos (13U)
10225#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos)
10226#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
10227#define GPIO_BRR_BR14_Pos (14U)
10228#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos)
10229#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
10230#define GPIO_BRR_BR15_Pos (15U)
10231#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos)
10232#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
10233
10234/* Legacy defines */
10235#define GPIO_BRR_BR_0 GPIO_BRR_BR0
10236#define GPIO_BRR_BR_1 GPIO_BRR_BR1
10237#define GPIO_BRR_BR_2 GPIO_BRR_BR2
10238#define GPIO_BRR_BR_3 GPIO_BRR_BR3
10239#define GPIO_BRR_BR_4 GPIO_BRR_BR4
10240#define GPIO_BRR_BR_5 GPIO_BRR_BR5
10241#define GPIO_BRR_BR_6 GPIO_BRR_BR6
10242#define GPIO_BRR_BR_7 GPIO_BRR_BR7
10243#define GPIO_BRR_BR_8 GPIO_BRR_BR8
10244#define GPIO_BRR_BR_9 GPIO_BRR_BR9
10245#define GPIO_BRR_BR_10 GPIO_BRR_BR10
10246#define GPIO_BRR_BR_11 GPIO_BRR_BR11
10247#define GPIO_BRR_BR_12 GPIO_BRR_BR12
10248#define GPIO_BRR_BR_13 GPIO_BRR_BR13
10249#define GPIO_BRR_BR_14 GPIO_BRR_BR14
10250#define GPIO_BRR_BR_15 GPIO_BRR_BR15
10251
10252
10253
10254/******************************************************************************/
10255/* */
10256/* HASH */
10257/* */
10258/******************************************************************************/
10259/****************** Bits definition for HASH_CR register ********************/
10260#define HASH_CR_INIT_Pos (2U)
10261#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos)
10262#define HASH_CR_INIT HASH_CR_INIT_Msk
10263#define HASH_CR_DMAE_Pos (3U)
10264#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos)
10265#define HASH_CR_DMAE HASH_CR_DMAE_Msk
10266#define HASH_CR_DATATYPE_Pos (4U)
10267#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos)
10268#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
10269#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos)
10270#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos)
10271#define HASH_CR_MODE_Pos (6U)
10272#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos)
10273#define HASH_CR_MODE HASH_CR_MODE_Msk
10274#define HASH_CR_ALGO_Pos (7U)
10275#define HASH_CR_ALGO_Msk (0x801UL << HASH_CR_ALGO_Pos)
10276#define HASH_CR_ALGO HASH_CR_ALGO_Msk
10277#define HASH_CR_ALGO_0 (0x001UL << HASH_CR_ALGO_Pos)
10278#define HASH_CR_ALGO_1 (0x800UL << HASH_CR_ALGO_Pos)
10279#define HASH_CR_NBW_Pos (8U)
10280#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos)
10281#define HASH_CR_NBW HASH_CR_NBW_Msk
10282#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos)
10283#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos)
10284#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos)
10285#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos)
10286#define HASH_CR_DINNE_Pos (12U)
10287#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos)
10288#define HASH_CR_DINNE HASH_CR_DINNE_Msk
10289#define HASH_CR_MDMAT_Pos (13U)
10290#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos)
10291#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
10292#define HASH_CR_LKEY_Pos (16U)
10293#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos)
10294#define HASH_CR_LKEY HASH_CR_LKEY_Msk
10295
10296/****************** Bits definition for HASH_STR register *******************/
10297#define HASH_STR_NBLW_Pos (0U)
10298#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos)
10299#define HASH_STR_NBLW HASH_STR_NBLW_Msk
10300#define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos)
10301#define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos)
10302#define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos)
10303#define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos)
10304#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos)
10305#define HASH_STR_DCAL_Pos (8U)
10306#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos)
10307#define HASH_STR_DCAL HASH_STR_DCAL_Msk
10308
10309/****************** Bits definition for HASH_IMR register *******************/
10310#define HASH_IMR_DINIE_Pos (0U)
10311#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos)
10312#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
10313#define HASH_IMR_DCIE_Pos (1U)
10314#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos)
10315#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
10316
10317/****************** Bits definition for HASH_SR register ********************/
10318#define HASH_SR_DINIS_Pos (0U)
10319#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos)
10320#define HASH_SR_DINIS HASH_SR_DINIS_Msk
10321#define HASH_SR_DCIS_Pos (1U)
10322#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos)
10323#define HASH_SR_DCIS HASH_SR_DCIS_Msk
10324#define HASH_SR_DMAS_Pos (2U)
10325#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos)
10326#define HASH_SR_DMAS HASH_SR_DMAS_Msk
10327#define HASH_SR_BUSY_Pos (3U)
10328#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos)
10329#define HASH_SR_BUSY HASH_SR_BUSY_Msk
10330
10331/******************************************************************************/
10332/* */
10333/* Inter-integrated Circuit Interface (I2C) */
10334/* */
10335/******************************************************************************/
10336/******************* Bit definition for I2C_CR1 register *******************/
10337#define I2C_CR1_PE_Pos (0U)
10338#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
10339#define I2C_CR1_PE I2C_CR1_PE_Msk
10340#define I2C_CR1_TXIE_Pos (1U)
10341#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
10342#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
10343#define I2C_CR1_RXIE_Pos (2U)
10344#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
10345#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
10346#define I2C_CR1_ADDRIE_Pos (3U)
10347#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
10348#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
10349#define I2C_CR1_NACKIE_Pos (4U)
10350#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
10351#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
10352#define I2C_CR1_STOPIE_Pos (5U)
10353#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
10354#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
10355#define I2C_CR1_TCIE_Pos (6U)
10356#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
10357#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
10358#define I2C_CR1_ERRIE_Pos (7U)
10359#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
10360#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
10361#define I2C_CR1_DNF_Pos (8U)
10362#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
10363#define I2C_CR1_DNF I2C_CR1_DNF_Msk
10364#define I2C_CR1_ANFOFF_Pos (12U)
10365#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
10366#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
10367#define I2C_CR1_SWRST_Pos (13U)
10368#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
10369#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
10370#define I2C_CR1_TXDMAEN_Pos (14U)
10371#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
10372#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
10373#define I2C_CR1_RXDMAEN_Pos (15U)
10374#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
10375#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
10376#define I2C_CR1_SBC_Pos (16U)
10377#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
10378#define I2C_CR1_SBC I2C_CR1_SBC_Msk
10379#define I2C_CR1_NOSTRETCH_Pos (17U)
10380#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
10381#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
10382#define I2C_CR1_WUPEN_Pos (18U)
10383#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)
10384#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk
10385#define I2C_CR1_GCEN_Pos (19U)
10386#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
10387#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
10388#define I2C_CR1_SMBHEN_Pos (20U)
10389#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
10390#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
10391#define I2C_CR1_SMBDEN_Pos (21U)
10392#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
10393#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
10394#define I2C_CR1_ALERTEN_Pos (22U)
10395#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
10396#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
10397#define I2C_CR1_PECEN_Pos (23U)
10398#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
10399#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
10401/****************** Bit definition for I2C_CR2 register ********************/
10402#define I2C_CR2_SADD_Pos (0U)
10403#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
10404#define I2C_CR2_SADD I2C_CR2_SADD_Msk
10405#define I2C_CR2_RD_WRN_Pos (10U)
10406#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
10407#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
10408#define I2C_CR2_ADD10_Pos (11U)
10409#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
10410#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
10411#define I2C_CR2_HEAD10R_Pos (12U)
10412#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
10413#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
10414#define I2C_CR2_START_Pos (13U)
10415#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
10416#define I2C_CR2_START I2C_CR2_START_Msk
10417#define I2C_CR2_STOP_Pos (14U)
10418#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
10419#define I2C_CR2_STOP I2C_CR2_STOP_Msk
10420#define I2C_CR2_NACK_Pos (15U)
10421#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
10422#define I2C_CR2_NACK I2C_CR2_NACK_Msk
10423#define I2C_CR2_NBYTES_Pos (16U)
10424#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
10425#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
10426#define I2C_CR2_RELOAD_Pos (24U)
10427#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
10428#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
10429#define I2C_CR2_AUTOEND_Pos (25U)
10430#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
10431#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
10432#define I2C_CR2_PECBYTE_Pos (26U)
10433#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
10434#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
10436/******************* Bit definition for I2C_OAR1 register ******************/
10437#define I2C_OAR1_OA1_Pos (0U)
10438#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
10439#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
10440#define I2C_OAR1_OA1MODE_Pos (10U)
10441#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
10442#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
10443#define I2C_OAR1_OA1EN_Pos (15U)
10444#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
10445#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
10447/******************* Bit definition for I2C_OAR2 register ******************/
10448#define I2C_OAR2_OA2_Pos (1U)
10449#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
10450#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
10451#define I2C_OAR2_OA2MSK_Pos (8U)
10452#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
10453#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
10454#define I2C_OAR2_OA2NOMASK (0x00000000UL)
10455#define I2C_OAR2_OA2MASK01_Pos (8U)
10456#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
10457#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
10458#define I2C_OAR2_OA2MASK02_Pos (9U)
10459#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
10460#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
10461#define I2C_OAR2_OA2MASK03_Pos (8U)
10462#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
10463#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
10464#define I2C_OAR2_OA2MASK04_Pos (10U)
10465#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
10466#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
10467#define I2C_OAR2_OA2MASK05_Pos (8U)
10468#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
10469#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
10470#define I2C_OAR2_OA2MASK06_Pos (9U)
10471#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
10472#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
10473#define I2C_OAR2_OA2MASK07_Pos (8U)
10474#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
10475#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
10476#define I2C_OAR2_OA2EN_Pos (15U)
10477#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
10478#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
10480/******************* Bit definition for I2C_TIMINGR register *******************/
10481#define I2C_TIMINGR_SCLL_Pos (0U)
10482#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
10483#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
10484#define I2C_TIMINGR_SCLH_Pos (8U)
10485#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
10486#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
10487#define I2C_TIMINGR_SDADEL_Pos (16U)
10488#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
10489#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
10490#define I2C_TIMINGR_SCLDEL_Pos (20U)
10491#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
10492#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
10493#define I2C_TIMINGR_PRESC_Pos (28U)
10494#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
10495#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
10497/******************* Bit definition for I2C_TIMEOUTR register *******************/
10498#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
10499#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
10500#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
10501#define I2C_TIMEOUTR_TIDLE_Pos (12U)
10502#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
10503#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
10504#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
10505#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
10506#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
10507#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
10508#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
10509#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
10510#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
10511#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
10512#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
10514/****************** Bit definition for I2C_ISR register *********************/
10515#define I2C_ISR_TXE_Pos (0U)
10516#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
10517#define I2C_ISR_TXE I2C_ISR_TXE_Msk
10518#define I2C_ISR_TXIS_Pos (1U)
10519#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
10520#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
10521#define I2C_ISR_RXNE_Pos (2U)
10522#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
10523#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
10524#define I2C_ISR_ADDR_Pos (3U)
10525#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
10526#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
10527#define I2C_ISR_NACKF_Pos (4U)
10528#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
10529#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
10530#define I2C_ISR_STOPF_Pos (5U)
10531#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
10532#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
10533#define I2C_ISR_TC_Pos (6U)
10534#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
10535#define I2C_ISR_TC I2C_ISR_TC_Msk
10536#define I2C_ISR_TCR_Pos (7U)
10537#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
10538#define I2C_ISR_TCR I2C_ISR_TCR_Msk
10539#define I2C_ISR_BERR_Pos (8U)
10540#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
10541#define I2C_ISR_BERR I2C_ISR_BERR_Msk
10542#define I2C_ISR_ARLO_Pos (9U)
10543#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
10544#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
10545#define I2C_ISR_OVR_Pos (10U)
10546#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
10547#define I2C_ISR_OVR I2C_ISR_OVR_Msk
10548#define I2C_ISR_PECERR_Pos (11U)
10549#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
10550#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
10551#define I2C_ISR_TIMEOUT_Pos (12U)
10552#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
10553#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
10554#define I2C_ISR_ALERT_Pos (13U)
10555#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
10556#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
10557#define I2C_ISR_BUSY_Pos (15U)
10558#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
10559#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
10560#define I2C_ISR_DIR_Pos (16U)
10561#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
10562#define I2C_ISR_DIR I2C_ISR_DIR_Msk
10563#define I2C_ISR_ADDCODE_Pos (17U)
10564#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
10565#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
10567/****************** Bit definition for I2C_ICR register *********************/
10568#define I2C_ICR_ADDRCF_Pos (3U)
10569#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
10570#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
10571#define I2C_ICR_NACKCF_Pos (4U)
10572#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
10573#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
10574#define I2C_ICR_STOPCF_Pos (5U)
10575#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
10576#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
10577#define I2C_ICR_BERRCF_Pos (8U)
10578#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
10579#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
10580#define I2C_ICR_ARLOCF_Pos (9U)
10581#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
10582#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
10583#define I2C_ICR_OVRCF_Pos (10U)
10584#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
10585#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
10586#define I2C_ICR_PECCF_Pos (11U)
10587#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
10588#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
10589#define I2C_ICR_TIMOUTCF_Pos (12U)
10590#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
10591#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
10592#define I2C_ICR_ALERTCF_Pos (13U)
10593#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
10594#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
10596/****************** Bit definition for I2C_PECR register *********************/
10597#define I2C_PECR_PEC_Pos (0U)
10598#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
10599#define I2C_PECR_PEC I2C_PECR_PEC_Msk
10601/****************** Bit definition for I2C_RXDR register *********************/
10602#define I2C_RXDR_RXDATA_Pos (0U)
10603#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
10604#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
10606/****************** Bit definition for I2C_TXDR register *********************/
10607#define I2C_TXDR_TXDATA_Pos (0U)
10608#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
10609#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
10611/******************************************************************************/
10612/* */
10613/* Independent WATCHDOG */
10614/* */
10615/******************************************************************************/
10616/******************* Bit definition for IWDG_KR register ********************/
10617#define IWDG_KR_KEY_Pos (0U)
10618#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
10619#define IWDG_KR_KEY IWDG_KR_KEY_Msk
10621/******************* Bit definition for IWDG_PR register ********************/
10622#define IWDG_PR_PR_Pos (0U)
10623#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
10624#define IWDG_PR_PR IWDG_PR_PR_Msk
10625#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
10626#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
10627#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
10629/******************* Bit definition for IWDG_RLR register *******************/
10630#define IWDG_RLR_RL_Pos (0U)
10631#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
10632#define IWDG_RLR_RL IWDG_RLR_RL_Msk
10634/******************* Bit definition for IWDG_SR register ********************/
10635#define IWDG_SR_PVU_Pos (0U)
10636#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
10637#define IWDG_SR_PVU IWDG_SR_PVU_Msk
10638#define IWDG_SR_RVU_Pos (1U)
10639#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
10640#define IWDG_SR_RVU IWDG_SR_RVU_Msk
10641#define IWDG_SR_WVU_Pos (2U)
10642#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
10643#define IWDG_SR_WVU IWDG_SR_WVU_Msk
10645/******************* Bit definition for IWDG_KR register ********************/
10646#define IWDG_WINR_WIN_Pos (0U)
10647#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
10648#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
10650/******************************************************************************/
10651/* */
10652/* Firewall */
10653/* */
10654/******************************************************************************/
10655
10656/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
10657#define FW_CSSA_ADD_Pos (8U)
10658#define FW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos)
10659#define FW_CSSA_ADD FW_CSSA_ADD_Msk
10660#define FW_CSL_LENG_Pos (8U)
10661#define FW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos)
10662#define FW_CSL_LENG FW_CSL_LENG_Msk
10663#define FW_NVDSSA_ADD_Pos (8U)
10664#define FW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos)
10665#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk
10666#define FW_NVDSL_LENG_Pos (8U)
10667#define FW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos)
10668#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk
10669#define FW_VDSSA_ADD_Pos (6U)
10670#define FW_VDSSA_ADD_Msk (0xFFFUL << FW_VDSSA_ADD_Pos)
10671#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk
10672#define FW_VDSL_LENG_Pos (6U)
10673#define FW_VDSL_LENG_Msk (0xFFFUL << FW_VDSL_LENG_Pos)
10674#define FW_VDSL_LENG FW_VDSL_LENG_Msk
10676/**************************Bit definition for CR register *********************/
10677#define FW_CR_FPA_Pos (0U)
10678#define FW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos)
10679#define FW_CR_FPA FW_CR_FPA_Msk
10680#define FW_CR_VDS_Pos (1U)
10681#define FW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos)
10682#define FW_CR_VDS FW_CR_VDS_Msk
10683#define FW_CR_VDE_Pos (2U)
10684#define FW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos)
10685#define FW_CR_VDE FW_CR_VDE_Msk
10687/******************************************************************************/
10688/* */
10689/* Power Control */
10690/* */
10691/******************************************************************************/
10692
10693/******************** Bit definition for PWR_CR1 register ********************/
10694
10695#define PWR_CR1_LPR_Pos (14U)
10696#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos)
10697#define PWR_CR1_LPR PWR_CR1_LPR_Msk
10698#define PWR_CR1_VOS_Pos (9U)
10699#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos)
10700#define PWR_CR1_VOS PWR_CR1_VOS_Msk
10701#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos)
10702#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos)
10703#define PWR_CR1_DBP_Pos (8U)
10704#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)
10705#define PWR_CR1_DBP PWR_CR1_DBP_Msk
10706#define PWR_CR1_LPMS_Pos (0U)
10707#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos)
10708#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk
10709#define PWR_CR1_LPMS_STOP0 (0x00000000UL)
10710#define PWR_CR1_LPMS_STOP1_Pos (0U)
10711#define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos)
10712#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk
10713#define PWR_CR1_LPMS_STOP2_Pos (1U)
10714#define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos)
10715#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk
10716#define PWR_CR1_LPMS_STANDBY_Pos (0U)
10717#define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)
10718#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk
10719#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
10720#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)
10721#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk
10724/******************** Bit definition for PWR_CR2 register ********************/
10725#define PWR_CR2_USV_Pos (10U)
10726#define PWR_CR2_USV_Msk (0x1UL << PWR_CR2_USV_Pos)
10727#define PWR_CR2_USV PWR_CR2_USV_Msk
10728#define PWR_CR2_IOSV_Pos (9U)
10729#define PWR_CR2_IOSV_Msk (0x1UL << PWR_CR2_IOSV_Pos)
10730#define PWR_CR2_IOSV PWR_CR2_IOSV_Msk
10732#define PWR_CR2_PVME_Pos (4U)
10733#define PWR_CR2_PVME_Msk (0xFUL << PWR_CR2_PVME_Pos)
10734#define PWR_CR2_PVME PWR_CR2_PVME_Msk
10735#define PWR_CR2_PVME4_Pos (7U)
10736#define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos)
10737#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk
10738#define PWR_CR2_PVME3_Pos (6U)
10739#define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos)
10740#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk
10741#define PWR_CR2_PVME2_Pos (5U)
10742#define PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos)
10743#define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk
10744#define PWR_CR2_PVME1_Pos (4U)
10745#define PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos)
10746#define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk
10748#define PWR_CR2_PLS_Pos (1U)
10749#define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos)
10750#define PWR_CR2_PLS PWR_CR2_PLS_Msk
10751#define PWR_CR2_PLS_LEV0 (0x00000000UL)
10752#define PWR_CR2_PLS_LEV1_Pos (1U)
10753#define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos)
10754#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk
10755#define PWR_CR2_PLS_LEV2_Pos (2U)
10756#define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos)
10757#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk
10758#define PWR_CR2_PLS_LEV3_Pos (1U)
10759#define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos)
10760#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk
10761#define PWR_CR2_PLS_LEV4_Pos (3U)
10762#define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos)
10763#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk
10764#define PWR_CR2_PLS_LEV5_Pos (1U)
10765#define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos)
10766#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk
10767#define PWR_CR2_PLS_LEV6_Pos (2U)
10768#define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos)
10769#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk
10770#define PWR_CR2_PLS_LEV7_Pos (1U)
10771#define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos)
10772#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk
10773#define PWR_CR2_PVDE_Pos (0U)
10774#define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos)
10775#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk
10777/******************** Bit definition for PWR_CR3 register ********************/
10778#define PWR_CR3_EIWUL_Pos (15U)
10779#define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos)
10780#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk
10781#define PWR_CR3_APC_Pos (10U)
10782#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos)
10783#define PWR_CR3_APC PWR_CR3_APC_Msk
10784#define PWR_CR3_RRS_Pos (8U)
10785#define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos)
10786#define PWR_CR3_RRS PWR_CR3_RRS_Msk
10787#define PWR_CR3_EWUP5_Pos (4U)
10788#define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos)
10789#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk
10790#define PWR_CR3_EWUP4_Pos (3U)
10791#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos)
10792#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk
10793#define PWR_CR3_EWUP3_Pos (2U)
10794#define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos)
10795#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk
10796#define PWR_CR3_EWUP2_Pos (1U)
10797#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos)
10798#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk
10799#define PWR_CR3_EWUP1_Pos (0U)
10800#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos)
10801#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk
10802#define PWR_CR3_EWUP_Pos (0U)
10803#define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos)
10804#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk
10806/* Legacy defines */
10807#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
10808#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
10809#define PWR_CR3_EIWF PWR_CR3_EIWUL
10810
10811
10812/******************** Bit definition for PWR_CR4 register ********************/
10813#define PWR_CR4_VBRS_Pos (9U)
10814#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos)
10815#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk
10816#define PWR_CR4_VBE_Pos (8U)
10817#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos)
10818#define PWR_CR4_VBE PWR_CR4_VBE_Msk
10819#define PWR_CR4_WP5_Pos (4U)
10820#define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos)
10821#define PWR_CR4_WP5 PWR_CR4_WP5_Msk
10822#define PWR_CR4_WP4_Pos (3U)
10823#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos)
10824#define PWR_CR4_WP4 PWR_CR4_WP4_Msk
10825#define PWR_CR4_WP3_Pos (2U)
10826#define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos)
10827#define PWR_CR4_WP3 PWR_CR4_WP3_Msk
10828#define PWR_CR4_WP2_Pos (1U)
10829#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos)
10830#define PWR_CR4_WP2 PWR_CR4_WP2_Msk
10831#define PWR_CR4_WP1_Pos (0U)
10832#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos)
10833#define PWR_CR4_WP1 PWR_CR4_WP1_Msk
10835/******************** Bit definition for PWR_SR1 register ********************/
10836#define PWR_SR1_WUFI_Pos (15U)
10837#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos)
10838#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk
10839#define PWR_SR1_SBF_Pos (8U)
10840#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos)
10841#define PWR_SR1_SBF PWR_SR1_SBF_Msk
10842#define PWR_SR1_WUF_Pos (0U)
10843#define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos)
10844#define PWR_SR1_WUF PWR_SR1_WUF_Msk
10845#define PWR_SR1_WUF5_Pos (4U)
10846#define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos)
10847#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk
10848#define PWR_SR1_WUF4_Pos (3U)
10849#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos)
10850#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk
10851#define PWR_SR1_WUF3_Pos (2U)
10852#define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos)
10853#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk
10854#define PWR_SR1_WUF2_Pos (1U)
10855#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos)
10856#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk
10857#define PWR_SR1_WUF1_Pos (0U)
10858#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos)
10859#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk
10861/******************** Bit definition for PWR_SR2 register ********************/
10862#define PWR_SR2_PVMO4_Pos (15U)
10863#define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos)
10864#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk
10865#define PWR_SR2_PVMO3_Pos (14U)
10866#define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos)
10867#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk
10868#define PWR_SR2_PVMO2_Pos (13U)
10869#define PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos)
10870#define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk
10871#define PWR_SR2_PVMO1_Pos (12U)
10872#define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos)
10873#define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk
10874#define PWR_SR2_PVDO_Pos (11U)
10875#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos)
10876#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk
10877#define PWR_SR2_VOSF_Pos (10U)
10878#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos)
10879#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk
10880#define PWR_SR2_REGLPF_Pos (9U)
10881#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos)
10882#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk
10883#define PWR_SR2_REGLPS_Pos (8U)
10884#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos)
10885#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk
10887/******************** Bit definition for PWR_SCR register ********************/
10888#define PWR_SCR_CSBF_Pos (8U)
10889#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos)
10890#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk
10891#define PWR_SCR_CWUF_Pos (0U)
10892#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos)
10893#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk
10894#define PWR_SCR_CWUF5_Pos (4U)
10895#define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos)
10896#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk
10897#define PWR_SCR_CWUF4_Pos (3U)
10898#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos)
10899#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk
10900#define PWR_SCR_CWUF3_Pos (2U)
10901#define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos)
10902#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk
10903#define PWR_SCR_CWUF2_Pos (1U)
10904#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos)
10905#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk
10906#define PWR_SCR_CWUF1_Pos (0U)
10907#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos)
10908#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk
10910/******************** Bit definition for PWR_PUCRA register ********************/
10911#define PWR_PUCRA_PA15_Pos (15U)
10912#define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos)
10913#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk
10914#define PWR_PUCRA_PA13_Pos (13U)
10915#define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos)
10916#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk
10917#define PWR_PUCRA_PA12_Pos (12U)
10918#define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos)
10919#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk
10920#define PWR_PUCRA_PA11_Pos (11U)
10921#define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos)
10922#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk
10923#define PWR_PUCRA_PA10_Pos (10U)
10924#define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos)
10925#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk
10926#define PWR_PUCRA_PA9_Pos (9U)
10927#define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos)
10928#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk
10929#define PWR_PUCRA_PA8_Pos (8U)
10930#define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos)
10931#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk
10932#define PWR_PUCRA_PA7_Pos (7U)
10933#define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos)
10934#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk
10935#define PWR_PUCRA_PA6_Pos (6U)
10936#define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos)
10937#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk
10938#define PWR_PUCRA_PA5_Pos (5U)
10939#define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos)
10940#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk
10941#define PWR_PUCRA_PA4_Pos (4U)
10942#define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos)
10943#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk
10944#define PWR_PUCRA_PA3_Pos (3U)
10945#define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos)
10946#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk
10947#define PWR_PUCRA_PA2_Pos (2U)
10948#define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos)
10949#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk
10950#define PWR_PUCRA_PA1_Pos (1U)
10951#define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos)
10952#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk
10953#define PWR_PUCRA_PA0_Pos (0U)
10954#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos)
10955#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk
10957/******************** Bit definition for PWR_PDCRA register ********************/
10958#define PWR_PDCRA_PA14_Pos (14U)
10959#define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos)
10960#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk
10961#define PWR_PDCRA_PA12_Pos (12U)
10962#define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos)
10963#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk
10964#define PWR_PDCRA_PA11_Pos (11U)
10965#define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos)
10966#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk
10967#define PWR_PDCRA_PA10_Pos (10U)
10968#define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos)
10969#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk
10970#define PWR_PDCRA_PA9_Pos (9U)
10971#define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos)
10972#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk
10973#define PWR_PDCRA_PA8_Pos (8U)
10974#define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos)
10975#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk
10976#define PWR_PDCRA_PA7_Pos (7U)
10977#define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos)
10978#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk
10979#define PWR_PDCRA_PA6_Pos (6U)
10980#define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos)
10981#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk
10982#define PWR_PDCRA_PA5_Pos (5U)
10983#define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos)
10984#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk
10985#define PWR_PDCRA_PA4_Pos (4U)
10986#define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos)
10987#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk
10988#define PWR_PDCRA_PA3_Pos (3U)
10989#define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos)
10990#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk
10991#define PWR_PDCRA_PA2_Pos (2U)
10992#define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos)
10993#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk
10994#define PWR_PDCRA_PA1_Pos (1U)
10995#define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos)
10996#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk
10997#define PWR_PDCRA_PA0_Pos (0U)
10998#define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos)
10999#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk
11001/******************** Bit definition for PWR_PUCRB register ********************/
11002#define PWR_PUCRB_PB15_Pos (15U)
11003#define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos)
11004#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk
11005#define PWR_PUCRB_PB14_Pos (14U)
11006#define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos)
11007#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk
11008#define PWR_PUCRB_PB13_Pos (13U)
11009#define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos)
11010#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk
11011#define PWR_PUCRB_PB12_Pos (12U)
11012#define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos)
11013#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk
11014#define PWR_PUCRB_PB11_Pos (11U)
11015#define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos)
11016#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk
11017#define PWR_PUCRB_PB10_Pos (10U)
11018#define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos)
11019#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk
11020#define PWR_PUCRB_PB9_Pos (9U)
11021#define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos)
11022#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk
11023#define PWR_PUCRB_PB8_Pos (8U)
11024#define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos)
11025#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk
11026#define PWR_PUCRB_PB7_Pos (7U)
11027#define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos)
11028#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk
11029#define PWR_PUCRB_PB6_Pos (6U)
11030#define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos)
11031#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk
11032#define PWR_PUCRB_PB5_Pos (5U)
11033#define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos)
11034#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk
11035#define PWR_PUCRB_PB4_Pos (4U)
11036#define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos)
11037#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk
11038#define PWR_PUCRB_PB3_Pos (3U)
11039#define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos)
11040#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk
11041#define PWR_PUCRB_PB2_Pos (2U)
11042#define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos)
11043#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk
11044#define PWR_PUCRB_PB1_Pos (1U)
11045#define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos)
11046#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk
11047#define PWR_PUCRB_PB0_Pos (0U)
11048#define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos)
11049#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk
11051/******************** Bit definition for PWR_PDCRB register ********************/
11052#define PWR_PDCRB_PB15_Pos (15U)
11053#define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos)
11054#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk
11055#define PWR_PDCRB_PB14_Pos (14U)
11056#define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos)
11057#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk
11058#define PWR_PDCRB_PB13_Pos (13U)
11059#define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos)
11060#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk
11061#define PWR_PDCRB_PB12_Pos (12U)
11062#define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos)
11063#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk
11064#define PWR_PDCRB_PB11_Pos (11U)
11065#define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos)
11066#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk
11067#define PWR_PDCRB_PB10_Pos (10U)
11068#define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos)
11069#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk
11070#define PWR_PDCRB_PB9_Pos (9U)
11071#define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos)
11072#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk
11073#define PWR_PDCRB_PB8_Pos (8U)
11074#define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos)
11075#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk
11076#define PWR_PDCRB_PB7_Pos (7U)
11077#define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos)
11078#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk
11079#define PWR_PDCRB_PB6_Pos (6U)
11080#define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos)
11081#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk
11082#define PWR_PDCRB_PB5_Pos (5U)
11083#define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos)
11084#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk
11085#define PWR_PDCRB_PB3_Pos (3U)
11086#define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos)
11087#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk
11088#define PWR_PDCRB_PB2_Pos (2U)
11089#define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos)
11090#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk
11091#define PWR_PDCRB_PB1_Pos (1U)
11092#define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos)
11093#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk
11094#define PWR_PDCRB_PB0_Pos (0U)
11095#define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos)
11096#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk
11098/******************** Bit definition for PWR_PUCRC register ********************/
11099#define PWR_PUCRC_PC15_Pos (15U)
11100#define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos)
11101#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk
11102#define PWR_PUCRC_PC14_Pos (14U)
11103#define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos)
11104#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk
11105#define PWR_PUCRC_PC13_Pos (13U)
11106#define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos)
11107#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk
11108#define PWR_PUCRC_PC12_Pos (12U)
11109#define PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos)
11110#define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk
11111#define PWR_PUCRC_PC11_Pos (11U)
11112#define PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos)
11113#define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk
11114#define PWR_PUCRC_PC10_Pos (10U)
11115#define PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos)
11116#define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk
11117#define PWR_PUCRC_PC9_Pos (9U)
11118#define PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos)
11119#define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk
11120#define PWR_PUCRC_PC8_Pos (8U)
11121#define PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos)
11122#define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk
11123#define PWR_PUCRC_PC7_Pos (7U)
11124#define PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos)
11125#define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk
11126#define PWR_PUCRC_PC6_Pos (6U)
11127#define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos)
11128#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk
11129#define PWR_PUCRC_PC5_Pos (5U)
11130#define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos)
11131#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk
11132#define PWR_PUCRC_PC4_Pos (4U)
11133#define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos)
11134#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk
11135#define PWR_PUCRC_PC3_Pos (3U)
11136#define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos)
11137#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk
11138#define PWR_PUCRC_PC2_Pos (2U)
11139#define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos)
11140#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk
11141#define PWR_PUCRC_PC1_Pos (1U)
11142#define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos)
11143#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk
11144#define PWR_PUCRC_PC0_Pos (0U)
11145#define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos)
11146#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk
11148/******************** Bit definition for PWR_PDCRC register ********************/
11149#define PWR_PDCRC_PC15_Pos (15U)
11150#define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos)
11151#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk
11152#define PWR_PDCRC_PC14_Pos (14U)
11153#define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos)
11154#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk
11155#define PWR_PDCRC_PC13_Pos (13U)
11156#define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos)
11157#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk
11158#define PWR_PDCRC_PC12_Pos (12U)
11159#define PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos)
11160#define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk
11161#define PWR_PDCRC_PC11_Pos (11U)
11162#define PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos)
11163#define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk
11164#define PWR_PDCRC_PC10_Pos (10U)
11165#define PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos)
11166#define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk
11167#define PWR_PDCRC_PC9_Pos (9U)
11168#define PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos)
11169#define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk
11170#define PWR_PDCRC_PC8_Pos (8U)
11171#define PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos)
11172#define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk
11173#define PWR_PDCRC_PC7_Pos (7U)
11174#define PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos)
11175#define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk
11176#define PWR_PDCRC_PC6_Pos (6U)
11177#define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos)
11178#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk
11179#define PWR_PDCRC_PC5_Pos (5U)
11180#define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos)
11181#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk
11182#define PWR_PDCRC_PC4_Pos (4U)
11183#define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos)
11184#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk
11185#define PWR_PDCRC_PC3_Pos (3U)
11186#define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos)
11187#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk
11188#define PWR_PDCRC_PC2_Pos (2U)
11189#define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos)
11190#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk
11191#define PWR_PDCRC_PC1_Pos (1U)
11192#define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos)
11193#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk
11194#define PWR_PDCRC_PC0_Pos (0U)
11195#define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos)
11196#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk
11198/******************** Bit definition for PWR_PUCRD register ********************/
11199#define PWR_PUCRD_PD15_Pos (15U)
11200#define PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos)
11201#define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk
11202#define PWR_PUCRD_PD14_Pos (14U)
11203#define PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos)
11204#define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk
11205#define PWR_PUCRD_PD13_Pos (13U)
11206#define PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos)
11207#define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk
11208#define PWR_PUCRD_PD12_Pos (12U)
11209#define PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos)
11210#define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk
11211#define PWR_PUCRD_PD11_Pos (11U)
11212#define PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos)
11213#define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk
11214#define PWR_PUCRD_PD10_Pos (10U)
11215#define PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos)
11216#define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk
11217#define PWR_PUCRD_PD9_Pos (9U)
11218#define PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos)
11219#define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk
11220#define PWR_PUCRD_PD8_Pos (8U)
11221#define PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos)
11222#define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk
11223#define PWR_PUCRD_PD7_Pos (7U)
11224#define PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos)
11225#define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk
11226#define PWR_PUCRD_PD6_Pos (6U)
11227#define PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos)
11228#define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk
11229#define PWR_PUCRD_PD5_Pos (5U)
11230#define PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos)
11231#define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk
11232#define PWR_PUCRD_PD4_Pos (4U)
11233#define PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos)
11234#define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk
11235#define PWR_PUCRD_PD3_Pos (3U)
11236#define PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos)
11237#define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk
11238#define PWR_PUCRD_PD2_Pos (2U)
11239#define PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos)
11240#define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk
11241#define PWR_PUCRD_PD1_Pos (1U)
11242#define PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos)
11243#define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk
11244#define PWR_PUCRD_PD0_Pos (0U)
11245#define PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos)
11246#define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk
11248/******************** Bit definition for PWR_PDCRD register ********************/
11249#define PWR_PDCRD_PD15_Pos (15U)
11250#define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos)
11251#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk
11252#define PWR_PDCRD_PD14_Pos (14U)
11253#define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos)
11254#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk
11255#define PWR_PDCRD_PD13_Pos (13U)
11256#define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos)
11257#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk
11258#define PWR_PDCRD_PD12_Pos (12U)
11259#define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos)
11260#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk
11261#define PWR_PDCRD_PD11_Pos (11U)
11262#define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos)
11263#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk
11264#define PWR_PDCRD_PD10_Pos (10U)
11265#define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos)
11266#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk
11267#define PWR_PDCRD_PD9_Pos (9U)
11268#define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos)
11269#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk
11270#define PWR_PDCRD_PD8_Pos (8U)
11271#define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos)
11272#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk
11273#define PWR_PDCRD_PD7_Pos (7U)
11274#define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos)
11275#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk
11276#define PWR_PDCRD_PD6_Pos (6U)
11277#define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos)
11278#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk
11279#define PWR_PDCRD_PD5_Pos (5U)
11280#define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos)
11281#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk
11282#define PWR_PDCRD_PD4_Pos (4U)
11283#define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos)
11284#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk
11285#define PWR_PDCRD_PD3_Pos (3U)
11286#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos)
11287#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk
11288#define PWR_PDCRD_PD2_Pos (2U)
11289#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos)
11290#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk
11291#define PWR_PDCRD_PD1_Pos (1U)
11292#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos)
11293#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk
11294#define PWR_PDCRD_PD0_Pos (0U)
11295#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos)
11296#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk
11298/******************** Bit definition for PWR_PUCRE register ********************/
11299#define PWR_PUCRE_PE15_Pos (15U)
11300#define PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos)
11301#define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk
11302#define PWR_PUCRE_PE14_Pos (14U)
11303#define PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos)
11304#define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk
11305#define PWR_PUCRE_PE13_Pos (13U)
11306#define PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos)
11307#define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk
11308#define PWR_PUCRE_PE12_Pos (12U)
11309#define PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos)
11310#define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk
11311#define PWR_PUCRE_PE11_Pos (11U)
11312#define PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos)
11313#define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk
11314#define PWR_PUCRE_PE10_Pos (10U)
11315#define PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos)
11316#define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk
11317#define PWR_PUCRE_PE9_Pos (9U)
11318#define PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos)
11319#define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk
11320#define PWR_PUCRE_PE8_Pos (8U)
11321#define PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos)
11322#define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk
11323#define PWR_PUCRE_PE7_Pos (7U)
11324#define PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos)
11325#define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk
11326#define PWR_PUCRE_PE6_Pos (6U)
11327#define PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos)
11328#define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk
11329#define PWR_PUCRE_PE5_Pos (5U)
11330#define PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos)
11331#define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk
11332#define PWR_PUCRE_PE4_Pos (4U)
11333#define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos)
11334#define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk
11335#define PWR_PUCRE_PE3_Pos (3U)
11336#define PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos)
11337#define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk
11338#define PWR_PUCRE_PE2_Pos (2U)
11339#define PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos)
11340#define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk
11341#define PWR_PUCRE_PE1_Pos (1U)
11342#define PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos)
11343#define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk
11344#define PWR_PUCRE_PE0_Pos (0U)
11345#define PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos)
11346#define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk
11348/******************** Bit definition for PWR_PDCRE register ********************/
11349#define PWR_PDCRE_PE15_Pos (15U)
11350#define PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos)
11351#define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk
11352#define PWR_PDCRE_PE14_Pos (14U)
11353#define PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos)
11354#define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk
11355#define PWR_PDCRE_PE13_Pos (13U)
11356#define PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos)
11357#define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk
11358#define PWR_PDCRE_PE12_Pos (12U)
11359#define PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos)
11360#define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk
11361#define PWR_PDCRE_PE11_Pos (11U)
11362#define PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos)
11363#define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk
11364#define PWR_PDCRE_PE10_Pos (10U)
11365#define PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos)
11366#define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk
11367#define PWR_PDCRE_PE9_Pos (9U)
11368#define PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos)
11369#define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk
11370#define PWR_PDCRE_PE8_Pos (8U)
11371#define PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos)
11372#define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk
11373#define PWR_PDCRE_PE7_Pos (7U)
11374#define PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos)
11375#define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk
11376#define PWR_PDCRE_PE6_Pos (6U)
11377#define PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos)
11378#define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk
11379#define PWR_PDCRE_PE5_Pos (5U)
11380#define PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos)
11381#define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk
11382#define PWR_PDCRE_PE4_Pos (4U)
11383#define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos)
11384#define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk
11385#define PWR_PDCRE_PE3_Pos (3U)
11386#define PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos)
11387#define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk
11388#define PWR_PDCRE_PE2_Pos (2U)
11389#define PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos)
11390#define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk
11391#define PWR_PDCRE_PE1_Pos (1U)
11392#define PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos)
11393#define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk
11394#define PWR_PDCRE_PE0_Pos (0U)
11395#define PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos)
11396#define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk
11398/******************** Bit definition for PWR_PUCRF register ********************/
11399#define PWR_PUCRF_PF15_Pos (15U)
11400#define PWR_PUCRF_PF15_Msk (0x1UL << PWR_PUCRF_PF15_Pos)
11401#define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk
11402#define PWR_PUCRF_PF14_Pos (14U)
11403#define PWR_PUCRF_PF14_Msk (0x1UL << PWR_PUCRF_PF14_Pos)
11404#define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk
11405#define PWR_PUCRF_PF13_Pos (13U)
11406#define PWR_PUCRF_PF13_Msk (0x1UL << PWR_PUCRF_PF13_Pos)
11407#define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk
11408#define PWR_PUCRF_PF12_Pos (12U)
11409#define PWR_PUCRF_PF12_Msk (0x1UL << PWR_PUCRF_PF12_Pos)
11410#define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk
11411#define PWR_PUCRF_PF11_Pos (11U)
11412#define PWR_PUCRF_PF11_Msk (0x1UL << PWR_PUCRF_PF11_Pos)
11413#define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk
11414#define PWR_PUCRF_PF10_Pos (10U)
11415#define PWR_PUCRF_PF10_Msk (0x1UL << PWR_PUCRF_PF10_Pos)
11416#define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk
11417#define PWR_PUCRF_PF9_Pos (9U)
11418#define PWR_PUCRF_PF9_Msk (0x1UL << PWR_PUCRF_PF9_Pos)
11419#define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk
11420#define PWR_PUCRF_PF8_Pos (8U)
11421#define PWR_PUCRF_PF8_Msk (0x1UL << PWR_PUCRF_PF8_Pos)
11422#define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk
11423#define PWR_PUCRF_PF7_Pos (7U)
11424#define PWR_PUCRF_PF7_Msk (0x1UL << PWR_PUCRF_PF7_Pos)
11425#define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk
11426#define PWR_PUCRF_PF6_Pos (6U)
11427#define PWR_PUCRF_PF6_Msk (0x1UL << PWR_PUCRF_PF6_Pos)
11428#define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk
11429#define PWR_PUCRF_PF5_Pos (5U)
11430#define PWR_PUCRF_PF5_Msk (0x1UL << PWR_PUCRF_PF5_Pos)
11431#define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk
11432#define PWR_PUCRF_PF4_Pos (4U)
11433#define PWR_PUCRF_PF4_Msk (0x1UL << PWR_PUCRF_PF4_Pos)
11434#define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk
11435#define PWR_PUCRF_PF3_Pos (3U)
11436#define PWR_PUCRF_PF3_Msk (0x1UL << PWR_PUCRF_PF3_Pos)
11437#define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk
11438#define PWR_PUCRF_PF2_Pos (2U)
11439#define PWR_PUCRF_PF2_Msk (0x1UL << PWR_PUCRF_PF2_Pos)
11440#define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk
11441#define PWR_PUCRF_PF1_Pos (1U)
11442#define PWR_PUCRF_PF1_Msk (0x1UL << PWR_PUCRF_PF1_Pos)
11443#define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk
11444#define PWR_PUCRF_PF0_Pos (0U)
11445#define PWR_PUCRF_PF0_Msk (0x1UL << PWR_PUCRF_PF0_Pos)
11446#define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk
11448/******************** Bit definition for PWR_PDCRF register ********************/
11449#define PWR_PDCRF_PF15_Pos (15U)
11450#define PWR_PDCRF_PF15_Msk (0x1UL << PWR_PDCRF_PF15_Pos)
11451#define PWR_PDCRF_PF15 PWR_PDCRF_PF15_Msk
11452#define PWR_PDCRF_PF14_Pos (14U)
11453#define PWR_PDCRF_PF14_Msk (0x1UL << PWR_PDCRF_PF14_Pos)
11454#define PWR_PDCRF_PF14 PWR_PDCRF_PF14_Msk
11455#define PWR_PDCRF_PF13_Pos (13U)
11456#define PWR_PDCRF_PF13_Msk (0x1UL << PWR_PDCRF_PF13_Pos)
11457#define PWR_PDCRF_PF13 PWR_PDCRF_PF13_Msk
11458#define PWR_PDCRF_PF12_Pos (12U)
11459#define PWR_PDCRF_PF12_Msk (0x1UL << PWR_PDCRF_PF12_Pos)
11460#define PWR_PDCRF_PF12 PWR_PDCRF_PF12_Msk
11461#define PWR_PDCRF_PF11_Pos (11U)
11462#define PWR_PDCRF_PF11_Msk (0x1UL << PWR_PDCRF_PF11_Pos)
11463#define PWR_PDCRF_PF11 PWR_PDCRF_PF11_Msk
11464#define PWR_PDCRF_PF10_Pos (10U)
11465#define PWR_PDCRF_PF10_Msk (0x1UL << PWR_PDCRF_PF10_Pos)
11466#define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk
11467#define PWR_PDCRF_PF9_Pos (9U)
11468#define PWR_PDCRF_PF9_Msk (0x1UL << PWR_PDCRF_PF9_Pos)
11469#define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk
11470#define PWR_PDCRF_PF8_Pos (8U)
11471#define PWR_PDCRF_PF8_Msk (0x1UL << PWR_PDCRF_PF8_Pos)
11472#define PWR_PDCRF_PF8 PWR_PDCRF_PF8_Msk
11473#define PWR_PDCRF_PF7_Pos (7U)
11474#define PWR_PDCRF_PF7_Msk (0x1UL << PWR_PDCRF_PF7_Pos)
11475#define PWR_PDCRF_PF7 PWR_PDCRF_PF7_Msk
11476#define PWR_PDCRF_PF6_Pos (6U)
11477#define PWR_PDCRF_PF6_Msk (0x1UL << PWR_PDCRF_PF6_Pos)
11478#define PWR_PDCRF_PF6 PWR_PDCRF_PF6_Msk
11479#define PWR_PDCRF_PF5_Pos (5U)
11480#define PWR_PDCRF_PF5_Msk (0x1UL << PWR_PDCRF_PF5_Pos)
11481#define PWR_PDCRF_PF5 PWR_PDCRF_PF5_Msk
11482#define PWR_PDCRF_PF4_Pos (4U)
11483#define PWR_PDCRF_PF4_Msk (0x1UL << PWR_PDCRF_PF4_Pos)
11484#define PWR_PDCRF_PF4 PWR_PDCRF_PF4_Msk
11485#define PWR_PDCRF_PF3_Pos (3U)
11486#define PWR_PDCRF_PF3_Msk (0x1UL << PWR_PDCRF_PF3_Pos)
11487#define PWR_PDCRF_PF3 PWR_PDCRF_PF3_Msk
11488#define PWR_PDCRF_PF2_Pos (2U)
11489#define PWR_PDCRF_PF2_Msk (0x1UL << PWR_PDCRF_PF2_Pos)
11490#define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk
11491#define PWR_PDCRF_PF1_Pos (1U)
11492#define PWR_PDCRF_PF1_Msk (0x1UL << PWR_PDCRF_PF1_Pos)
11493#define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk
11494#define PWR_PDCRF_PF0_Pos (0U)
11495#define PWR_PDCRF_PF0_Msk (0x1UL << PWR_PDCRF_PF0_Pos)
11496#define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk
11498/******************** Bit definition for PWR_PUCRG register ********************/
11499#define PWR_PUCRG_PG15_Pos (15U)
11500#define PWR_PUCRG_PG15_Msk (0x1UL << PWR_PUCRG_PG15_Pos)
11501#define PWR_PUCRG_PG15 PWR_PUCRG_PG15_Msk
11502#define PWR_PUCRG_PG14_Pos (14U)
11503#define PWR_PUCRG_PG14_Msk (0x1UL << PWR_PUCRG_PG14_Pos)
11504#define PWR_PUCRG_PG14 PWR_PUCRG_PG14_Msk
11505#define PWR_PUCRG_PG13_Pos (13U)
11506#define PWR_PUCRG_PG13_Msk (0x1UL << PWR_PUCRG_PG13_Pos)
11507#define PWR_PUCRG_PG13 PWR_PUCRG_PG13_Msk
11508#define PWR_PUCRG_PG12_Pos (12U)
11509#define PWR_PUCRG_PG12_Msk (0x1UL << PWR_PUCRG_PG12_Pos)
11510#define PWR_PUCRG_PG12 PWR_PUCRG_PG12_Msk
11511#define PWR_PUCRG_PG11_Pos (11U)
11512#define PWR_PUCRG_PG11_Msk (0x1UL << PWR_PUCRG_PG11_Pos)
11513#define PWR_PUCRG_PG11 PWR_PUCRG_PG11_Msk
11514#define PWR_PUCRG_PG10_Pos (10U)
11515#define PWR_PUCRG_PG10_Msk (0x1UL << PWR_PUCRG_PG10_Pos)
11516#define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk
11517#define PWR_PUCRG_PG9_Pos (9U)
11518#define PWR_PUCRG_PG9_Msk (0x1UL << PWR_PUCRG_PG9_Pos)
11519#define PWR_PUCRG_PG9 PWR_PUCRG_PG9_Msk
11520#define PWR_PUCRG_PG8_Pos (8U)
11521#define PWR_PUCRG_PG8_Msk (0x1UL << PWR_PUCRG_PG8_Pos)
11522#define PWR_PUCRG_PG8 PWR_PUCRG_PG8_Msk
11523#define PWR_PUCRG_PG7_Pos (7U)
11524#define PWR_PUCRG_PG7_Msk (0x1UL << PWR_PUCRG_PG7_Pos)
11525#define PWR_PUCRG_PG7 PWR_PUCRG_PG7_Msk
11526#define PWR_PUCRG_PG6_Pos (6U)
11527#define PWR_PUCRG_PG6_Msk (0x1UL << PWR_PUCRG_PG6_Pos)
11528#define PWR_PUCRG_PG6 PWR_PUCRG_PG6_Msk
11529#define PWR_PUCRG_PG5_Pos (5U)
11530#define PWR_PUCRG_PG5_Msk (0x1UL << PWR_PUCRG_PG5_Pos)
11531#define PWR_PUCRG_PG5 PWR_PUCRG_PG5_Msk
11532#define PWR_PUCRG_PG4_Pos (4U)
11533#define PWR_PUCRG_PG4_Msk (0x1UL << PWR_PUCRG_PG4_Pos)
11534#define PWR_PUCRG_PG4 PWR_PUCRG_PG4_Msk
11535#define PWR_PUCRG_PG3_Pos (3U)
11536#define PWR_PUCRG_PG3_Msk (0x1UL << PWR_PUCRG_PG3_Pos)
11537#define PWR_PUCRG_PG3 PWR_PUCRG_PG3_Msk
11538#define PWR_PUCRG_PG2_Pos (2U)
11539#define PWR_PUCRG_PG2_Msk (0x1UL << PWR_PUCRG_PG2_Pos)
11540#define PWR_PUCRG_PG2 PWR_PUCRG_PG2_Msk
11541#define PWR_PUCRG_PG1_Pos (1U)
11542#define PWR_PUCRG_PG1_Msk (0x1UL << PWR_PUCRG_PG1_Pos)
11543#define PWR_PUCRG_PG1 PWR_PUCRG_PG1_Msk
11544#define PWR_PUCRG_PG0_Pos (0U)
11545#define PWR_PUCRG_PG0_Msk (0x1UL << PWR_PUCRG_PG0_Pos)
11546#define PWR_PUCRG_PG0 PWR_PUCRG_PG0_Msk
11548/******************** Bit definition for PWR_PDCRG register ********************/
11549#define PWR_PDCRG_PG15_Pos (15U)
11550#define PWR_PDCRG_PG15_Msk (0x1UL << PWR_PDCRG_PG15_Pos)
11551#define PWR_PDCRG_PG15 PWR_PDCRG_PG15_Msk
11552#define PWR_PDCRG_PG14_Pos (14U)
11553#define PWR_PDCRG_PG14_Msk (0x1UL << PWR_PDCRG_PG14_Pos)
11554#define PWR_PDCRG_PG14 PWR_PDCRG_PG14_Msk
11555#define PWR_PDCRG_PG13_Pos (13U)
11556#define PWR_PDCRG_PG13_Msk (0x1UL << PWR_PDCRG_PG13_Pos)
11557#define PWR_PDCRG_PG13 PWR_PDCRG_PG13_Msk
11558#define PWR_PDCRG_PG12_Pos (12U)
11559#define PWR_PDCRG_PG12_Msk (0x1UL << PWR_PDCRG_PG12_Pos)
11560#define PWR_PDCRG_PG12 PWR_PDCRG_PG12_Msk
11561#define PWR_PDCRG_PG11_Pos (11U)
11562#define PWR_PDCRG_PG11_Msk (0x1UL << PWR_PDCRG_PG11_Pos)
11563#define PWR_PDCRG_PG11 PWR_PDCRG_PG11_Msk
11564#define PWR_PDCRG_PG10_Pos (10U)
11565#define PWR_PDCRG_PG10_Msk (0x1UL << PWR_PDCRG_PG10_Pos)
11566#define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk
11567#define PWR_PDCRG_PG9_Pos (9U)
11568#define PWR_PDCRG_PG9_Msk (0x1UL << PWR_PDCRG_PG9_Pos)
11569#define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk
11570#define PWR_PDCRG_PG8_Pos (8U)
11571#define PWR_PDCRG_PG8_Msk (0x1UL << PWR_PDCRG_PG8_Pos)
11572#define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk
11573#define PWR_PDCRG_PG7_Pos (7U)
11574#define PWR_PDCRG_PG7_Msk (0x1UL << PWR_PDCRG_PG7_Pos)
11575#define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk
11576#define PWR_PDCRG_PG6_Pos (6U)
11577#define PWR_PDCRG_PG6_Msk (0x1UL << PWR_PDCRG_PG6_Pos)
11578#define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk
11579#define PWR_PDCRG_PG5_Pos (5U)
11580#define PWR_PDCRG_PG5_Msk (0x1UL << PWR_PDCRG_PG5_Pos)
11581#define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk
11582#define PWR_PDCRG_PG4_Pos (4U)
11583#define PWR_PDCRG_PG4_Msk (0x1UL << PWR_PDCRG_PG4_Pos)
11584#define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk
11585#define PWR_PDCRG_PG3_Pos (3U)
11586#define PWR_PDCRG_PG3_Msk (0x1UL << PWR_PDCRG_PG3_Pos)
11587#define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk
11588#define PWR_PDCRG_PG2_Pos (2U)
11589#define PWR_PDCRG_PG2_Msk (0x1UL << PWR_PDCRG_PG2_Pos)
11590#define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk
11591#define PWR_PDCRG_PG1_Pos (1U)
11592#define PWR_PDCRG_PG1_Msk (0x1UL << PWR_PDCRG_PG1_Pos)
11593#define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk
11594#define PWR_PDCRG_PG0_Pos (0U)
11595#define PWR_PDCRG_PG0_Msk (0x1UL << PWR_PDCRG_PG0_Pos)
11596#define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk
11598/******************** Bit definition for PWR_PUCRH register ********************/
11599#define PWR_PUCRH_PH15_Pos (15U)
11600#define PWR_PUCRH_PH15_Msk (0x1UL << PWR_PUCRH_PH15_Pos)
11601#define PWR_PUCRH_PH15 PWR_PUCRH_PH15_Msk
11602#define PWR_PUCRH_PH14_Pos (14U)
11603#define PWR_PUCRH_PH14_Msk (0x1UL << PWR_PUCRH_PH14_Pos)
11604#define PWR_PUCRH_PH14 PWR_PUCRH_PH14_Msk
11605#define PWR_PUCRH_PH13_Pos (13U)
11606#define PWR_PUCRH_PH13_Msk (0x1UL << PWR_PUCRH_PH13_Pos)
11607#define PWR_PUCRH_PH13 PWR_PUCRH_PH13_Msk
11608#define PWR_PUCRH_PH12_Pos (12U)
11609#define PWR_PUCRH_PH12_Msk (0x1UL << PWR_PUCRH_PH12_Pos)
11610#define PWR_PUCRH_PH12 PWR_PUCRH_PH12_Msk
11611#define PWR_PUCRH_PH11_Pos (11U)
11612#define PWR_PUCRH_PH11_Msk (0x1UL << PWR_PUCRH_PH11_Pos)
11613#define PWR_PUCRH_PH11 PWR_PUCRH_PH11_Msk
11614#define PWR_PUCRH_PH10_Pos (10U)
11615#define PWR_PUCRH_PH10_Msk (0x1UL << PWR_PUCRH_PH10_Pos)
11616#define PWR_PUCRH_PH10 PWR_PUCRH_PH10_Msk
11617#define PWR_PUCRH_PH9_Pos (9U)
11618#define PWR_PUCRH_PH9_Msk (0x1UL << PWR_PUCRH_PH9_Pos)
11619#define PWR_PUCRH_PH9 PWR_PUCRH_PH9_Msk
11620#define PWR_PUCRH_PH8_Pos (8U)
11621#define PWR_PUCRH_PH8_Msk (0x1UL << PWR_PUCRH_PH8_Pos)
11622#define PWR_PUCRH_PH8 PWR_PUCRH_PH8_Msk
11623#define PWR_PUCRH_PH7_Pos (7U)
11624#define PWR_PUCRH_PH7_Msk (0x1UL << PWR_PUCRH_PH7_Pos)
11625#define PWR_PUCRH_PH7 PWR_PUCRH_PH7_Msk
11626#define PWR_PUCRH_PH6_Pos (6U)
11627#define PWR_PUCRH_PH6_Msk (0x1UL << PWR_PUCRH_PH6_Pos)
11628#define PWR_PUCRH_PH6 PWR_PUCRH_PH6_Msk
11629#define PWR_PUCRH_PH5_Pos (5U)
11630#define PWR_PUCRH_PH5_Msk (0x1UL << PWR_PUCRH_PH5_Pos)
11631#define PWR_PUCRH_PH5 PWR_PUCRH_PH5_Msk
11632#define PWR_PUCRH_PH4_Pos (4U)
11633#define PWR_PUCRH_PH4_Msk (0x1UL << PWR_PUCRH_PH4_Pos)
11634#define PWR_PUCRH_PH4 PWR_PUCRH_PH4_Msk
11635#define PWR_PUCRH_PH3_Pos (3U)
11636#define PWR_PUCRH_PH3_Msk (0x1UL << PWR_PUCRH_PH3_Pos)
11637#define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk
11638#define PWR_PUCRH_PH2_Pos (2U)
11639#define PWR_PUCRH_PH2_Msk (0x1UL << PWR_PUCRH_PH2_Pos)
11640#define PWR_PUCRH_PH2 PWR_PUCRH_PH2_Msk
11641#define PWR_PUCRH_PH1_Pos (1U)
11642#define PWR_PUCRH_PH1_Msk (0x1UL << PWR_PUCRH_PH1_Pos)
11643#define PWR_PUCRH_PH1 PWR_PUCRH_PH1_Msk
11644#define PWR_PUCRH_PH0_Pos (0U)
11645#define PWR_PUCRH_PH0_Msk (0x1UL << PWR_PUCRH_PH0_Pos)
11646#define PWR_PUCRH_PH0 PWR_PUCRH_PH0_Msk
11648/******************** Bit definition for PWR_PDCRH register ********************/
11649#define PWR_PDCRH_PH15_Pos (15U)
11650#define PWR_PDCRH_PH15_Msk (0x1UL << PWR_PDCRH_PH15_Pos)
11651#define PWR_PDCRH_PH15 PWR_PDCRH_PH15_Msk
11652#define PWR_PDCRH_PH14_Pos (14U)
11653#define PWR_PDCRH_PH14_Msk (0x1UL << PWR_PDCRH_PH14_Pos)
11654#define PWR_PDCRH_PH14 PWR_PDCRH_PH14_Msk
11655#define PWR_PDCRH_PH13_Pos (13U)
11656#define PWR_PDCRH_PH13_Msk (0x1UL << PWR_PDCRH_PH13_Pos)
11657#define PWR_PDCRH_PH13 PWR_PDCRH_PH13_Msk
11658#define PWR_PDCRH_PH12_Pos (12U)
11659#define PWR_PDCRH_PH12_Msk (0x1UL << PWR_PDCRH_PH12_Pos)
11660#define PWR_PDCRH_PH12 PWR_PDCRH_PH12_Msk
11661#define PWR_PDCRH_PH11_Pos (11U)
11662#define PWR_PDCRH_PH11_Msk (0x1UL << PWR_PDCRH_PH11_Pos)
11663#define PWR_PDCRH_PH11 PWR_PDCRH_PH11_Msk
11664#define PWR_PDCRH_PH10_Pos (10U)
11665#define PWR_PDCRH_PH10_Msk (0x1UL << PWR_PDCRH_PH10_Pos)
11666#define PWR_PDCRH_PH10 PWR_PDCRH_PH10_Msk
11667#define PWR_PDCRH_PH9_Pos (9U)
11668#define PWR_PDCRH_PH9_Msk (0x1UL << PWR_PDCRH_PH9_Pos)
11669#define PWR_PDCRH_PH9 PWR_PDCRH_PH9_Msk
11670#define PWR_PDCRH_PH8_Pos (8U)
11671#define PWR_PDCRH_PH8_Msk (0x1UL << PWR_PDCRH_PH8_Pos)
11672#define PWR_PDCRH_PH8 PWR_PDCRH_PH8_Msk
11673#define PWR_PDCRH_PH7_Pos (7U)
11674#define PWR_PDCRH_PH7_Msk (0x1UL << PWR_PDCRH_PH7_Pos)
11675#define PWR_PDCRH_PH7 PWR_PDCRH_PH7_Msk
11676#define PWR_PDCRH_PH6_Pos (6U)
11677#define PWR_PDCRH_PH6_Msk (0x1UL << PWR_PDCRH_PH6_Pos)
11678#define PWR_PDCRH_PH6 PWR_PDCRH_PH6_Msk
11679#define PWR_PDCRH_PH5_Pos (5U)
11680#define PWR_PDCRH_PH5_Msk (0x1UL << PWR_PDCRH_PH5_Pos)
11681#define PWR_PDCRH_PH5 PWR_PDCRH_PH5_Msk
11682#define PWR_PDCRH_PH4_Pos (4U)
11683#define PWR_PDCRH_PH4_Msk (0x1UL << PWR_PDCRH_PH4_Pos)
11684#define PWR_PDCRH_PH4 PWR_PDCRH_PH4_Msk
11685#define PWR_PDCRH_PH3_Pos (3U)
11686#define PWR_PDCRH_PH3_Msk (0x1UL << PWR_PDCRH_PH3_Pos)
11687#define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk
11688#define PWR_PDCRH_PH2_Pos (2U)
11689#define PWR_PDCRH_PH2_Msk (0x1UL << PWR_PDCRH_PH2_Pos)
11690#define PWR_PDCRH_PH2 PWR_PDCRH_PH2_Msk
11691#define PWR_PDCRH_PH1_Pos (1U)
11692#define PWR_PDCRH_PH1_Msk (0x1UL << PWR_PDCRH_PH1_Pos)
11693#define PWR_PDCRH_PH1 PWR_PDCRH_PH1_Msk
11694#define PWR_PDCRH_PH0_Pos (0U)
11695#define PWR_PDCRH_PH0_Msk (0x1UL << PWR_PDCRH_PH0_Pos)
11696#define PWR_PDCRH_PH0 PWR_PDCRH_PH0_Msk
11698/******************** Bit definition for PWR_PUCRI register ********************/
11699#define PWR_PUCRI_PI11_Pos (11U)
11700#define PWR_PUCRI_PI11_Msk (0x1UL << PWR_PUCRI_PI11_Pos)
11701#define PWR_PUCRI_PI11 PWR_PUCRI_PI11_Msk
11702#define PWR_PUCRI_PI10_Pos (10U)
11703#define PWR_PUCRI_PI10_Msk (0x1UL << PWR_PUCRI_PI10_Pos)
11704#define PWR_PUCRI_PI10 PWR_PUCRI_PI10_Msk
11705#define PWR_PUCRI_PI9_Pos (9U)
11706#define PWR_PUCRI_PI9_Msk (0x1UL << PWR_PUCRI_PI9_Pos)
11707#define PWR_PUCRI_PI9 PWR_PUCRI_PI9_Msk
11708#define PWR_PUCRI_PI8_Pos (8U)
11709#define PWR_PUCRI_PI8_Msk (0x1UL << PWR_PUCRI_PI8_Pos)
11710#define PWR_PUCRI_PI8 PWR_PUCRI_PI8_Msk
11711#define PWR_PUCRI_PI7_Pos (7U)
11712#define PWR_PUCRI_PI7_Msk (0x1UL << PWR_PUCRI_PI7_Pos)
11713#define PWR_PUCRI_PI7 PWR_PUCRI_PI7_Msk
11714#define PWR_PUCRI_PI6_Pos (6U)
11715#define PWR_PUCRI_PI6_Msk (0x1UL << PWR_PUCRI_PI6_Pos)
11716#define PWR_PUCRI_PI6 PWR_PUCRI_PI6_Msk
11717#define PWR_PUCRI_PI5_Pos (5U)
11718#define PWR_PUCRI_PI5_Msk (0x1UL << PWR_PUCRI_PI5_Pos)
11719#define PWR_PUCRI_PI5 PWR_PUCRI_PI5_Msk
11720#define PWR_PUCRI_PI4_Pos (4U)
11721#define PWR_PUCRI_PI4_Msk (0x1UL << PWR_PUCRI_PI4_Pos)
11722#define PWR_PUCRI_PI4 PWR_PUCRI_PI4_Msk
11723#define PWR_PUCRI_PI3_Pos (3U)
11724#define PWR_PUCRI_PI3_Msk (0x1UL << PWR_PUCRI_PI3_Pos)
11725#define PWR_PUCRI_PI3 PWR_PUCRI_PI3_Msk
11726#define PWR_PUCRI_PI2_Pos (2U)
11727#define PWR_PUCRI_PI2_Msk (0x1UL << PWR_PUCRI_PI2_Pos)
11728#define PWR_PUCRI_PI2 PWR_PUCRI_PI2_Msk
11729#define PWR_PUCRI_PI1_Pos (1U)
11730#define PWR_PUCRI_PI1_Msk (0x1UL << PWR_PUCRI_PI1_Pos)
11731#define PWR_PUCRI_PI1 PWR_PUCRI_PI1_Msk
11732#define PWR_PUCRI_PI0_Pos (0U)
11733#define PWR_PUCRI_PI0_Msk (0x1UL << PWR_PUCRI_PI0_Pos)
11734#define PWR_PUCRI_PI0 PWR_PUCRI_PI0_Msk
11736/******************** Bit definition for PWR_PDCRI register ********************/
11737#define PWR_PDCRI_PI11_Pos (11U)
11738#define PWR_PDCRI_PI11_Msk (0x1UL << PWR_PDCRI_PI11_Pos)
11739#define PWR_PDCRI_PI11 PWR_PDCRI_PI11_Msk
11740#define PWR_PDCRI_PI10_Pos (10U)
11741#define PWR_PDCRI_PI10_Msk (0x1UL << PWR_PDCRI_PI10_Pos)
11742#define PWR_PDCRI_PI10 PWR_PDCRI_PI10_Msk
11743#define PWR_PDCRI_PI9_Pos (9U)
11744#define PWR_PDCRI_PI9_Msk (0x1UL << PWR_PDCRI_PI9_Pos)
11745#define PWR_PDCRI_PI9 PWR_PDCRI_PI9_Msk
11746#define PWR_PDCRI_PI8_Pos (8U)
11747#define PWR_PDCRI_PI8_Msk (0x1UL << PWR_PDCRI_PI8_Pos)
11748#define PWR_PDCRI_PI8 PWR_PDCRI_PI8_Msk
11749#define PWR_PDCRI_PI7_Pos (7U)
11750#define PWR_PDCRI_PI7_Msk (0x1UL << PWR_PDCRI_PI7_Pos)
11751#define PWR_PDCRI_PI7 PWR_PDCRI_PI7_Msk
11752#define PWR_PDCRI_PI6_Pos (6U)
11753#define PWR_PDCRI_PI6_Msk (0x1UL << PWR_PDCRI_PI6_Pos)
11754#define PWR_PDCRI_PI6 PWR_PDCRI_PI6_Msk
11755#define PWR_PDCRI_PI5_Pos (5U)
11756#define PWR_PDCRI_PI5_Msk (0x1UL << PWR_PDCRI_PI5_Pos)
11757#define PWR_PDCRI_PI5 PWR_PDCRI_PI5_Msk
11758#define PWR_PDCRI_PI4_Pos (4U)
11759#define PWR_PDCRI_PI4_Msk (0x1UL << PWR_PDCRI_PI4_Pos)
11760#define PWR_PDCRI_PI4 PWR_PDCRI_PI4_Msk
11761#define PWR_PDCRI_PI3_Pos (3U)
11762#define PWR_PDCRI_PI3_Msk (0x1UL << PWR_PDCRI_PI3_Pos)
11763#define PWR_PDCRI_PI3 PWR_PDCRI_PI3_Msk
11764#define PWR_PDCRI_PI2_Pos (2U)
11765#define PWR_PDCRI_PI2_Msk (0x1UL << PWR_PDCRI_PI2_Pos)
11766#define PWR_PDCRI_PI2 PWR_PDCRI_PI2_Msk
11767#define PWR_PDCRI_PI1_Pos (1U)
11768#define PWR_PDCRI_PI1_Msk (0x1UL << PWR_PDCRI_PI1_Pos)
11769#define PWR_PDCRI_PI1 PWR_PDCRI_PI1_Msk
11770#define PWR_PDCRI_PI0_Pos (0U)
11771#define PWR_PDCRI_PI0_Msk (0x1UL << PWR_PDCRI_PI0_Pos)
11772#define PWR_PDCRI_PI0 PWR_PDCRI_PI0_Msk
11775/******************************************************************************/
11776/* */
11777/* Reset and Clock Control */
11778/* */
11779/******************************************************************************/
11780/*
11781* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
11782*/
11783#define RCC_PLLSAI1_SUPPORT
11784#define RCC_PLLP_SUPPORT
11785#define RCC_HSI48_SUPPORT
11786#define RCC_PLLP_DIV_2_31_SUPPORT
11787#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
11788#define RCC_PLLSAI2_SUPPORT
11789#define RCC_PLLSAI2P_DIV_2_31_SUPPORT
11790
11791/******************** Bit definition for RCC_CR register ********************/
11792#define RCC_CR_MSION_Pos (0U)
11793#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos)
11794#define RCC_CR_MSION RCC_CR_MSION_Msk
11795#define RCC_CR_MSIRDY_Pos (1U)
11796#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos)
11797#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk
11798#define RCC_CR_MSIPLLEN_Pos (2U)
11799#define RCC_CR_MSIPLLEN_Msk (0x1UL << RCC_CR_MSIPLLEN_Pos)
11800#define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk
11801#define RCC_CR_MSIRGSEL_Pos (3U)
11802#define RCC_CR_MSIRGSEL_Msk (0x1UL << RCC_CR_MSIRGSEL_Pos)
11803#define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk
11806#define RCC_CR_MSIRANGE_Pos (4U)
11807#define RCC_CR_MSIRANGE_Msk (0xFUL << RCC_CR_MSIRANGE_Pos)
11808#define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk
11809#define RCC_CR_MSIRANGE_0 (0x0UL << RCC_CR_MSIRANGE_Pos)
11810#define RCC_CR_MSIRANGE_1 (0x1UL << RCC_CR_MSIRANGE_Pos)
11811#define RCC_CR_MSIRANGE_2 (0x2UL << RCC_CR_MSIRANGE_Pos)
11812#define RCC_CR_MSIRANGE_3 (0x3UL << RCC_CR_MSIRANGE_Pos)
11813#define RCC_CR_MSIRANGE_4 (0x4UL << RCC_CR_MSIRANGE_Pos)
11814#define RCC_CR_MSIRANGE_5 (0x5UL << RCC_CR_MSIRANGE_Pos)
11815#define RCC_CR_MSIRANGE_6 (0x6UL << RCC_CR_MSIRANGE_Pos)
11816#define RCC_CR_MSIRANGE_7 (0x7UL << RCC_CR_MSIRANGE_Pos)
11817#define RCC_CR_MSIRANGE_8 (0x8UL << RCC_CR_MSIRANGE_Pos)
11818#define RCC_CR_MSIRANGE_9 (0x9UL << RCC_CR_MSIRANGE_Pos)
11819#define RCC_CR_MSIRANGE_10 (0xAUL << RCC_CR_MSIRANGE_Pos)
11820#define RCC_CR_MSIRANGE_11 (0xBUL << RCC_CR_MSIRANGE_Pos)
11822#define RCC_CR_HSION_Pos (8U)
11823#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
11824#define RCC_CR_HSION RCC_CR_HSION_Msk
11825#define RCC_CR_HSIKERON_Pos (9U)
11826#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)
11827#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk
11828#define RCC_CR_HSIRDY_Pos (10U)
11829#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
11830#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
11831#define RCC_CR_HSIASFS_Pos (11U)
11832#define RCC_CR_HSIASFS_Msk (0x1UL << RCC_CR_HSIASFS_Pos)
11833#define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk
11835#define RCC_CR_HSEON_Pos (16U)
11836#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
11837#define RCC_CR_HSEON RCC_CR_HSEON_Msk
11838#define RCC_CR_HSERDY_Pos (17U)
11839#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
11840#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
11841#define RCC_CR_HSEBYP_Pos (18U)
11842#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
11843#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
11844#define RCC_CR_CSSON_Pos (19U)
11845#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
11846#define RCC_CR_CSSON RCC_CR_CSSON_Msk
11848#define RCC_CR_PLLON_Pos (24U)
11849#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
11850#define RCC_CR_PLLON RCC_CR_PLLON_Msk
11851#define RCC_CR_PLLRDY_Pos (25U)
11852#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
11853#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
11854#define RCC_CR_PLLSAI1ON_Pos (26U)
11855#define RCC_CR_PLLSAI1ON_Msk (0x1UL << RCC_CR_PLLSAI1ON_Pos)
11856#define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk
11857#define RCC_CR_PLLSAI1RDY_Pos (27U)
11858#define RCC_CR_PLLSAI1RDY_Msk (0x1UL << RCC_CR_PLLSAI1RDY_Pos)
11859#define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk
11860#define RCC_CR_PLLSAI2ON_Pos (28U)
11861#define RCC_CR_PLLSAI2ON_Msk (0x1UL << RCC_CR_PLLSAI2ON_Pos)
11862#define RCC_CR_PLLSAI2ON RCC_CR_PLLSAI2ON_Msk
11863#define RCC_CR_PLLSAI2RDY_Pos (29U)
11864#define RCC_CR_PLLSAI2RDY_Msk (0x1UL << RCC_CR_PLLSAI2RDY_Pos)
11865#define RCC_CR_PLLSAI2RDY RCC_CR_PLLSAI2RDY_Msk
11867/******************** Bit definition for RCC_ICSCR register ***************/
11869#define RCC_ICSCR_MSICAL_Pos (0U)
11870#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos)
11871#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk
11872#define RCC_ICSCR_MSICAL_0 (0x01UL << RCC_ICSCR_MSICAL_Pos)
11873#define RCC_ICSCR_MSICAL_1 (0x02UL << RCC_ICSCR_MSICAL_Pos)
11874#define RCC_ICSCR_MSICAL_2 (0x04UL << RCC_ICSCR_MSICAL_Pos)
11875#define RCC_ICSCR_MSICAL_3 (0x08UL << RCC_ICSCR_MSICAL_Pos)
11876#define RCC_ICSCR_MSICAL_4 (0x10UL << RCC_ICSCR_MSICAL_Pos)
11877#define RCC_ICSCR_MSICAL_5 (0x20UL << RCC_ICSCR_MSICAL_Pos)
11878#define RCC_ICSCR_MSICAL_6 (0x40UL << RCC_ICSCR_MSICAL_Pos)
11879#define RCC_ICSCR_MSICAL_7 (0x80UL << RCC_ICSCR_MSICAL_Pos)
11882#define RCC_ICSCR_MSITRIM_Pos (8U)
11883#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos)
11884#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk
11885#define RCC_ICSCR_MSITRIM_0 (0x01UL << RCC_ICSCR_MSITRIM_Pos)
11886#define RCC_ICSCR_MSITRIM_1 (0x02UL << RCC_ICSCR_MSITRIM_Pos)
11887#define RCC_ICSCR_MSITRIM_2 (0x04UL << RCC_ICSCR_MSITRIM_Pos)
11888#define RCC_ICSCR_MSITRIM_3 (0x08UL << RCC_ICSCR_MSITRIM_Pos)
11889#define RCC_ICSCR_MSITRIM_4 (0x10UL << RCC_ICSCR_MSITRIM_Pos)
11890#define RCC_ICSCR_MSITRIM_5 (0x20UL << RCC_ICSCR_MSITRIM_Pos)
11891#define RCC_ICSCR_MSITRIM_6 (0x40UL << RCC_ICSCR_MSITRIM_Pos)
11892#define RCC_ICSCR_MSITRIM_7 (0x80UL << RCC_ICSCR_MSITRIM_Pos)
11895#define RCC_ICSCR_HSICAL_Pos (16U)
11896#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos)
11897#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk
11898#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos)
11899#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos)
11900#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos)
11901#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos)
11902#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos)
11903#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos)
11904#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos)
11905#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos)
11908#define RCC_ICSCR_HSITRIM_Pos (24U)
11909#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos)
11910#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk
11911#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos)
11912#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos)
11913#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos)
11914#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos)
11915#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos)
11916#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos)
11917#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos)
11919/******************** Bit definition for RCC_CFGR register ******************/
11921#define RCC_CFGR_SW_Pos (0U)
11922#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
11923#define RCC_CFGR_SW RCC_CFGR_SW_Msk
11924#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
11925#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
11927#define RCC_CFGR_SW_MSI (0x00000000UL)
11928#define RCC_CFGR_SW_HSI (0x00000001UL)
11929#define RCC_CFGR_SW_HSE (0x00000002UL)
11930#define RCC_CFGR_SW_PLL (0x00000003UL)
11933#define RCC_CFGR_SWS_Pos (2U)
11934#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
11935#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
11936#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
11937#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
11939#define RCC_CFGR_SWS_MSI (0x00000000UL)
11940#define RCC_CFGR_SWS_HSI (0x00000004UL)
11941#define RCC_CFGR_SWS_HSE (0x00000008UL)
11942#define RCC_CFGR_SWS_PLL (0x0000000CUL)
11945#define RCC_CFGR_HPRE_Pos (4U)
11946#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
11947#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
11948#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
11949#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
11950#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
11951#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
11953#define RCC_CFGR_HPRE_DIV1 (0x00000000UL)
11954#define RCC_CFGR_HPRE_DIV2 (0x00000080UL)
11955#define RCC_CFGR_HPRE_DIV4 (0x00000090UL)
11956#define RCC_CFGR_HPRE_DIV8 (0x000000A0UL)
11957#define RCC_CFGR_HPRE_DIV16 (0x000000B0UL)
11958#define RCC_CFGR_HPRE_DIV64 (0x000000C0UL)
11959#define RCC_CFGR_HPRE_DIV128 (0x000000D0UL)
11960#define RCC_CFGR_HPRE_DIV256 (0x000000E0UL)
11961#define RCC_CFGR_HPRE_DIV512 (0x000000F0UL)
11964#define RCC_CFGR_PPRE1_Pos (8U)
11965#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
11966#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
11967#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
11968#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
11969#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
11971#define RCC_CFGR_PPRE1_DIV1 (0x00000000UL)
11972#define RCC_CFGR_PPRE1_DIV2 (0x00000400UL)
11973#define RCC_CFGR_PPRE1_DIV4 (0x00000500UL)
11974#define RCC_CFGR_PPRE1_DIV8 (0x00000600UL)
11975#define RCC_CFGR_PPRE1_DIV16 (0x00000700UL)
11978#define RCC_CFGR_PPRE2_Pos (11U)
11979#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
11980#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
11981#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
11982#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
11983#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
11985#define RCC_CFGR_PPRE2_DIV1 (0x00000000UL)
11986#define RCC_CFGR_PPRE2_DIV2 (0x00002000UL)
11987#define RCC_CFGR_PPRE2_DIV4 (0x00002800UL)
11988#define RCC_CFGR_PPRE2_DIV8 (0x00003000UL)
11989#define RCC_CFGR_PPRE2_DIV16 (0x00003800UL)
11991#define RCC_CFGR_STOPWUCK_Pos (15U)
11992#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos)
11993#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk
11996#define RCC_CFGR_MCOSEL_Pos (24U)
11997#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos)
11998#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk
11999#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos)
12000#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos)
12001#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos)
12002#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos)
12004#define RCC_CFGR_MCOPRE_Pos (28U)
12005#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)
12006#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk
12007#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos)
12008#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos)
12009#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos)
12011#define RCC_CFGR_MCOPRE_DIV1 (0x00000000UL)
12012#define RCC_CFGR_MCOPRE_DIV2 (0x10000000UL)
12013#define RCC_CFGR_MCOPRE_DIV4 (0x20000000UL)
12014#define RCC_CFGR_MCOPRE_DIV8 (0x30000000UL)
12015#define RCC_CFGR_MCOPRE_DIV16 (0x40000000UL)
12017/* Legacy aliases */
12018#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
12019#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
12020#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
12021#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
12022#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
12023#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
12024
12025/******************** Bit definition for RCC_PLLCFGR register ***************/
12026#define RCC_PLLCFGR_PLLSRC_Pos (0U)
12027#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)
12028#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
12029
12030#define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
12031#define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_MSI_Pos)
12032#define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk
12033#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
12034#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)
12035#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk
12036#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
12037#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
12038#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
12040#define RCC_PLLCFGR_PLLM_Pos (4U)
12041#define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos)
12042#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
12043#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos)
12044#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos)
12045#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos)
12047#define RCC_PLLCFGR_PLLN_Pos (8U)
12048#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos)
12049#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
12050#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos)
12051#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos)
12052#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos)
12053#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos)
12054#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos)
12055#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos)
12056#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos)
12058#define RCC_PLLCFGR_PLLPEN_Pos (16U)
12059#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)
12060#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
12061#define RCC_PLLCFGR_PLLP_Pos (17U)
12062#define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos)
12063#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
12064#define RCC_PLLCFGR_PLLQEN_Pos (20U)
12065#define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)
12066#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
12067
12068#define RCC_PLLCFGR_PLLQ_Pos (21U)
12069#define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos)
12070#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
12071#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
12072#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
12074#define RCC_PLLCFGR_PLLREN_Pos (24U)
12075#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos)
12076#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
12077#define RCC_PLLCFGR_PLLR_Pos (25U)
12078#define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos)
12079#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
12080#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)
12081#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)
12083#define RCC_PLLCFGR_PLLPDIV_Pos (27U)
12084#define RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)
12085#define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
12086#define RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)
12087#define RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)
12088#define RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)
12089#define RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)
12090#define RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)
12092/******************** Bit definition for RCC_PLLSAI1CFGR register ************/
12093#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
12094#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FUL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
12095#define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
12096#define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
12097#define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
12098#define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
12099#define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
12100#define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
12101#define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
12102#define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
12104#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
12105#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos)
12106#define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
12107#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
12108#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)
12109#define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
12110
12111#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
12112#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos)
12113#define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
12114#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
12115#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
12116#define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
12117#define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
12118#define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
12120#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
12121#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos)
12122#define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
12123#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
12124#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
12125#define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
12126#define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
12127#define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
12129#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos (27U)
12130#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk (0x1FUL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
12131#define RCC_PLLSAI1CFGR_PLLSAI1PDIV RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk
12132#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 (0x01UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
12133#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 (0x02UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
12134#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 (0x04UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
12135#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 (0x08UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
12136#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 (0x10UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
12138/******************** Bit definition for RCC_PLLSAI2CFGR register ************/
12139#define RCC_PLLSAI2CFGR_PLLSAI2N_Pos (8U)
12140#define RCC_PLLSAI2CFGR_PLLSAI2N_Msk (0x7FUL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
12141#define RCC_PLLSAI2CFGR_PLLSAI2N RCC_PLLSAI2CFGR_PLLSAI2N_Msk
12142#define RCC_PLLSAI2CFGR_PLLSAI2N_0 (0x01UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
12143#define RCC_PLLSAI2CFGR_PLLSAI2N_1 (0x02UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
12144#define RCC_PLLSAI2CFGR_PLLSAI2N_2 (0x04UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
12145#define RCC_PLLSAI2CFGR_PLLSAI2N_3 (0x08UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
12146#define RCC_PLLSAI2CFGR_PLLSAI2N_4 (0x10UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
12147#define RCC_PLLSAI2CFGR_PLLSAI2N_5 (0x20UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
12148#define RCC_PLLSAI2CFGR_PLLSAI2N_6 (0x40UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
12150#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos (16U)
12151#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos)
12152#define RCC_PLLSAI2CFGR_PLLSAI2PEN RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk
12153#define RCC_PLLSAI2CFGR_PLLSAI2P_Pos (17U)
12154#define RCC_PLLSAI2CFGR_PLLSAI2P_Msk (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)
12155#define RCC_PLLSAI2CFGR_PLLSAI2P RCC_PLLSAI2CFGR_PLLSAI2P_Msk
12156
12157#define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos (24U)
12158#define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos)
12159#define RCC_PLLSAI2CFGR_PLLSAI2REN RCC_PLLSAI2CFGR_PLLSAI2REN_Msk
12160#define RCC_PLLSAI2CFGR_PLLSAI2R_Pos (25U)
12161#define RCC_PLLSAI2CFGR_PLLSAI2R_Msk (0x3UL << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
12162#define RCC_PLLSAI2CFGR_PLLSAI2R RCC_PLLSAI2CFGR_PLLSAI2R_Msk
12163#define RCC_PLLSAI2CFGR_PLLSAI2R_0 (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
12164#define RCC_PLLSAI2CFGR_PLLSAI2R_1 (0x2UL << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
12166#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos (27U)
12167#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk (0x1FUL << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)
12168#define RCC_PLLSAI2CFGR_PLLSAI2PDIV RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk
12169#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_0 (0x01UL << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)
12170#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_1 (0x02UL << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)
12171#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_2 (0x04UL << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)
12172#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_3 (0x08UL << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)
12173#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_4 (0x10UL << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)
12175/******************** Bit definition for RCC_CIER register ******************/
12176#define RCC_CIER_LSIRDYIE_Pos (0U)
12177#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)
12178#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
12179#define RCC_CIER_LSERDYIE_Pos (1U)
12180#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)
12181#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
12182#define RCC_CIER_MSIRDYIE_Pos (2U)
12183#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos)
12184#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
12185#define RCC_CIER_HSIRDYIE_Pos (3U)
12186#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)
12187#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
12188#define RCC_CIER_HSERDYIE_Pos (4U)
12189#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)
12190#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
12191#define RCC_CIER_PLLRDYIE_Pos (5U)
12192#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos)
12193#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
12194#define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
12195#define RCC_CIER_PLLSAI1RDYIE_Msk (0x1UL << RCC_CIER_PLLSAI1RDYIE_Pos)
12196#define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
12197#define RCC_CIER_PLLSAI2RDYIE_Pos (7U)
12198#define RCC_CIER_PLLSAI2RDYIE_Msk (0x1UL << RCC_CIER_PLLSAI2RDYIE_Pos)
12199#define RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE_Msk
12200#define RCC_CIER_LSECSSIE_Pos (9U)
12201#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos)
12202#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
12203#define RCC_CIER_HSI48RDYIE_Pos (10U)
12204#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)
12205#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
12206
12207/******************** Bit definition for RCC_CIFR register ******************/
12208#define RCC_CIFR_LSIRDYF_Pos (0U)
12209#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)
12210#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
12211#define RCC_CIFR_LSERDYF_Pos (1U)
12212#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)
12213#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
12214#define RCC_CIFR_MSIRDYF_Pos (2U)
12215#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos)
12216#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
12217#define RCC_CIFR_HSIRDYF_Pos (3U)
12218#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)
12219#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
12220#define RCC_CIFR_HSERDYF_Pos (4U)
12221#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)
12222#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
12223#define RCC_CIFR_PLLRDYF_Pos (5U)
12224#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)
12225#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
12226#define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
12227#define RCC_CIFR_PLLSAI1RDYF_Msk (0x1UL << RCC_CIFR_PLLSAI1RDYF_Pos)
12228#define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
12229#define RCC_CIFR_PLLSAI2RDYF_Pos (7U)
12230#define RCC_CIFR_PLLSAI2RDYF_Msk (0x1UL << RCC_CIFR_PLLSAI2RDYF_Pos)
12231#define RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF_Msk
12232#define RCC_CIFR_CSSF_Pos (8U)
12233#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos)
12234#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
12235#define RCC_CIFR_LSECSSF_Pos (9U)
12236#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos)
12237#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
12238#define RCC_CIFR_HSI48RDYF_Pos (10U)
12239#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos)
12240#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
12241
12242/******************** Bit definition for RCC_CICR register ******************/
12243#define RCC_CICR_LSIRDYC_Pos (0U)
12244#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)
12245#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
12246#define RCC_CICR_LSERDYC_Pos (1U)
12247#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)
12248#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
12249#define RCC_CICR_MSIRDYC_Pos (2U)
12250#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos)
12251#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
12252#define RCC_CICR_HSIRDYC_Pos (3U)
12253#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)
12254#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
12255#define RCC_CICR_HSERDYC_Pos (4U)
12256#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)
12257#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
12258#define RCC_CICR_PLLRDYC_Pos (5U)
12259#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)
12260#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
12261#define RCC_CICR_PLLSAI1RDYC_Pos (6U)
12262#define RCC_CICR_PLLSAI1RDYC_Msk (0x1UL << RCC_CICR_PLLSAI1RDYC_Pos)
12263#define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
12264#define RCC_CICR_PLLSAI2RDYC_Pos (7U)
12265#define RCC_CICR_PLLSAI2RDYC_Msk (0x1UL << RCC_CICR_PLLSAI2RDYC_Pos)
12266#define RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC_Msk
12267#define RCC_CICR_CSSC_Pos (8U)
12268#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos)
12269#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
12270#define RCC_CICR_LSECSSC_Pos (9U)
12271#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos)
12272#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
12273#define RCC_CICR_HSI48RDYC_Pos (10U)
12274#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos)
12275#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
12276
12277/******************** Bit definition for RCC_AHB1RSTR register **************/
12278#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
12279#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
12280#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
12281#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
12282#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
12283#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
12284#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
12285#define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)
12286#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
12287#define RCC_AHB1RSTR_CRCRST_Pos (12U)
12288#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
12289#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
12290#define RCC_AHB1RSTR_TSCRST_Pos (16U)
12291#define RCC_AHB1RSTR_TSCRST_Msk (0x1UL << RCC_AHB1RSTR_TSCRST_Pos)
12292#define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
12293#define RCC_AHB1RSTR_DMA2DRST_Pos (17U)
12294#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos)
12295#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
12296
12297/******************** Bit definition for RCC_AHB2RSTR register **************/
12298#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
12299#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)
12300#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
12301#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
12302#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)
12303#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
12304#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
12305#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)
12306#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
12307#define RCC_AHB2RSTR_GPIODRST_Pos (3U)
12308#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)
12309#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
12310#define RCC_AHB2RSTR_GPIOERST_Pos (4U)
12311#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)
12312#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
12313#define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
12314#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)
12315#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
12316#define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
12317#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)
12318#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
12319#define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
12320#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)
12321#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
12322#define RCC_AHB2RSTR_GPIOIRST_Pos (8U)
12323#define RCC_AHB2RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOIRST_Pos)
12324#define RCC_AHB2RSTR_GPIOIRST RCC_AHB2RSTR_GPIOIRST_Msk
12325#define RCC_AHB2RSTR_OTGFSRST_Pos (12U)
12326#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
12327#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
12328#define RCC_AHB2RSTR_ADCRST_Pos (13U)
12329#define RCC_AHB2RSTR_ADCRST_Msk (0x1UL << RCC_AHB2RSTR_ADCRST_Pos)
12330#define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
12331#define RCC_AHB2RSTR_DCMIRST_Pos (14U)
12332#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
12333#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
12334#define RCC_AHB2RSTR_AESRST_Pos (16U)
12335#define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos)
12336#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk
12337#define RCC_AHB2RSTR_HASHRST_Pos (17U)
12338#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)
12339#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
12340#define RCC_AHB2RSTR_RNGRST_Pos (18U)
12341#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
12342#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
12343
12344/******************** Bit definition for RCC_AHB3RSTR register **************/
12345#define RCC_AHB3RSTR_FMCRST_Pos (0U)
12346#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
12347#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
12348#define RCC_AHB3RSTR_QSPIRST_Pos (8U)
12349#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
12350#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
12351
12352/******************** Bit definition for RCC_APB1RSTR1 register **************/
12353#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
12354#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)
12355#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
12356#define RCC_APB1RSTR1_TIM3RST_Pos (1U)
12357#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)
12358#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
12359#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
12360#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)
12361#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
12362#define RCC_APB1RSTR1_TIM5RST_Pos (3U)
12363#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)
12364#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
12365#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
12366#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)
12367#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
12368#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
12369#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)
12370#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
12371#define RCC_APB1RSTR1_LCDRST_Pos (9U)
12372#define RCC_APB1RSTR1_LCDRST_Msk (0x1UL << RCC_APB1RSTR1_LCDRST_Pos)
12373#define RCC_APB1RSTR1_LCDRST RCC_APB1RSTR1_LCDRST_Msk
12374#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
12375#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)
12376#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
12377#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
12378#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)
12379#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
12380#define RCC_APB1RSTR1_USART2RST_Pos (17U)
12381#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)
12382#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
12383#define RCC_APB1RSTR1_USART3RST_Pos (18U)
12384#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)
12385#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
12386#define RCC_APB1RSTR1_UART4RST_Pos (19U)
12387#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)
12388#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
12389#define RCC_APB1RSTR1_UART5RST_Pos (20U)
12390#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)
12391#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
12392#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
12393#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)
12394#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
12395#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
12396#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)
12397#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
12398#define RCC_APB1RSTR1_I2C3RST_Pos (23U)
12399#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)
12400#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
12401#define RCC_APB1RSTR1_CRSRST_Pos (24U)
12402#define RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)
12403#define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
12404#define RCC_APB1RSTR1_CAN1RST_Pos (25U)
12405#define RCC_APB1RSTR1_CAN1RST_Msk (0x1UL << RCC_APB1RSTR1_CAN1RST_Pos)
12406#define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk
12407#define RCC_APB1RSTR1_CAN2RST_Pos (26U)
12408#define RCC_APB1RSTR1_CAN2RST_Msk (0x1UL << RCC_APB1RSTR1_CAN2RST_Pos)
12409#define RCC_APB1RSTR1_CAN2RST RCC_APB1RSTR1_CAN2RST_Msk
12410#define RCC_APB1RSTR1_PWRRST_Pos (28U)
12411#define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)
12412#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
12413#define RCC_APB1RSTR1_DAC1RST_Pos (29U)
12414#define RCC_APB1RSTR1_DAC1RST_Msk (0x1UL << RCC_APB1RSTR1_DAC1RST_Pos)
12415#define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
12416#define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
12417#define RCC_APB1RSTR1_OPAMPRST_Msk (0x1UL << RCC_APB1RSTR1_OPAMPRST_Pos)
12418#define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
12419#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
12420#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)
12421#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
12422
12423/******************** Bit definition for RCC_APB1RSTR2 register **************/
12424#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
12425#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)
12426#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
12427#define RCC_APB1RSTR2_I2C4RST_Pos (1U)
12428#define RCC_APB1RSTR2_I2C4RST_Msk (0x1UL << RCC_APB1RSTR2_I2C4RST_Pos)
12429#define RCC_APB1RSTR2_I2C4RST RCC_APB1RSTR2_I2C4RST_Msk
12430#define RCC_APB1RSTR2_SWPMI1RST_Pos (2U)
12431#define RCC_APB1RSTR2_SWPMI1RST_Msk (0x1UL << RCC_APB1RSTR2_SWPMI1RST_Pos)
12432#define RCC_APB1RSTR2_SWPMI1RST RCC_APB1RSTR2_SWPMI1RST_Msk
12433#define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
12434#define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos)
12435#define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
12436
12437/******************** Bit definition for RCC_APB2RSTR register **************/
12438#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
12439#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
12440#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
12441#define RCC_APB2RSTR_SDMMC1RST_Pos (10U)
12442#define RCC_APB2RSTR_SDMMC1RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC1RST_Pos)
12443#define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
12444#define RCC_APB2RSTR_TIM1RST_Pos (11U)
12445#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
12446#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
12447#define RCC_APB2RSTR_SPI1RST_Pos (12U)
12448#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
12449#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
12450#define RCC_APB2RSTR_TIM8RST_Pos (13U)
12451#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
12452#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
12453#define RCC_APB2RSTR_USART1RST_Pos (14U)
12454#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
12455#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
12456#define RCC_APB2RSTR_TIM15RST_Pos (16U)
12457#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)
12458#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
12459#define RCC_APB2RSTR_TIM16RST_Pos (17U)
12460#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)
12461#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
12462#define RCC_APB2RSTR_TIM17RST_Pos (18U)
12463#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)
12464#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
12465#define RCC_APB2RSTR_SAI1RST_Pos (21U)
12466#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
12467#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
12468#define RCC_APB2RSTR_SAI2RST_Pos (22U)
12469#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)
12470#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
12471#define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
12472#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos)
12473#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
12474
12475/******************** Bit definition for RCC_AHB1ENR register ***************/
12476#define RCC_AHB1ENR_DMA1EN_Pos (0U)
12477#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
12478#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
12479#define RCC_AHB1ENR_DMA2EN_Pos (1U)
12480#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
12481#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
12482#define RCC_AHB1ENR_FLASHEN_Pos (8U)
12483#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)
12484#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
12485#define RCC_AHB1ENR_CRCEN_Pos (12U)
12486#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
12487#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
12488#define RCC_AHB1ENR_TSCEN_Pos (16U)
12489#define RCC_AHB1ENR_TSCEN_Msk (0x1UL << RCC_AHB1ENR_TSCEN_Pos)
12490#define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
12491#define RCC_AHB1ENR_DMA2DEN_Pos (17U)
12492#define RCC_AHB1ENR_DMA2DEN_Msk (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos)
12493#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
12494
12495/******************** Bit definition for RCC_AHB2ENR register ***************/
12496#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
12497#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)
12498#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
12499#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
12500#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)
12501#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
12502#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
12503#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)
12504#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
12505#define RCC_AHB2ENR_GPIODEN_Pos (3U)
12506#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)
12507#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
12508#define RCC_AHB2ENR_GPIOEEN_Pos (4U)
12509#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)
12510#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
12511#define RCC_AHB2ENR_GPIOFEN_Pos (5U)
12512#define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)
12513#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
12514#define RCC_AHB2ENR_GPIOGEN_Pos (6U)
12515#define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)
12516#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
12517#define RCC_AHB2ENR_GPIOHEN_Pos (7U)
12518#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos)
12519#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
12520#define RCC_AHB2ENR_GPIOIEN_Pos (8U)
12521#define RCC_AHB2ENR_GPIOIEN_Msk (0x1UL << RCC_AHB2ENR_GPIOIEN_Pos)
12522#define RCC_AHB2ENR_GPIOIEN RCC_AHB2ENR_GPIOIEN_Msk
12523#define RCC_AHB2ENR_OTGFSEN_Pos (12U)
12524#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
12525#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
12526#define RCC_AHB2ENR_ADCEN_Pos (13U)
12527#define RCC_AHB2ENR_ADCEN_Msk (0x1UL << RCC_AHB2ENR_ADCEN_Pos)
12528#define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
12529#define RCC_AHB2ENR_DCMIEN_Pos (14U)
12530#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
12531#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
12532#define RCC_AHB2ENR_AESEN_Pos (16U)
12533#define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos)
12534#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk
12535#define RCC_AHB2ENR_HASHEN_Pos (17U)
12536#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos)
12537#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
12538#define RCC_AHB2ENR_RNGEN_Pos (18U)
12539#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
12540#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
12541
12542/******************** Bit definition for RCC_AHB3ENR register ***************/
12543#define RCC_AHB3ENR_FMCEN_Pos (0U)
12544#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
12545#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
12546#define RCC_AHB3ENR_QSPIEN_Pos (8U)
12547#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
12548#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
12549
12550/******************** Bit definition for RCC_APB1ENR1 register ***************/
12551#define RCC_APB1ENR1_TIM2EN_Pos (0U)
12552#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)
12553#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
12554#define RCC_APB1ENR1_TIM3EN_Pos (1U)
12555#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)
12556#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
12557#define RCC_APB1ENR1_TIM4EN_Pos (2U)
12558#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)
12559#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
12560#define RCC_APB1ENR1_TIM5EN_Pos (3U)
12561#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)
12562#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
12563#define RCC_APB1ENR1_TIM6EN_Pos (4U)
12564#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)
12565#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
12566#define RCC_APB1ENR1_TIM7EN_Pos (5U)
12567#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)
12568#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
12569#define RCC_APB1ENR1_LCDEN_Pos (9U)
12570#define RCC_APB1ENR1_LCDEN_Msk (0x1UL << RCC_APB1ENR1_LCDEN_Pos)
12571#define RCC_APB1ENR1_LCDEN RCC_APB1ENR1_LCDEN_Msk
12572#define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
12573#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)
12574#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
12575#define RCC_APB1ENR1_WWDGEN_Pos (11U)
12576#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)
12577#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
12578#define RCC_APB1ENR1_SPI2EN_Pos (14U)
12579#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)
12580#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
12581#define RCC_APB1ENR1_SPI3EN_Pos (15U)
12582#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)
12583#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
12584#define RCC_APB1ENR1_USART2EN_Pos (17U)
12585#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)
12586#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
12587#define RCC_APB1ENR1_USART3EN_Pos (18U)
12588#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)
12589#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
12590#define RCC_APB1ENR1_UART4EN_Pos (19U)
12591#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos)
12592#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
12593#define RCC_APB1ENR1_UART5EN_Pos (20U)
12594#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos)
12595#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
12596#define RCC_APB1ENR1_I2C1EN_Pos (21U)
12597#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)
12598#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
12599#define RCC_APB1ENR1_I2C2EN_Pos (22U)
12600#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)
12601#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
12602#define RCC_APB1ENR1_I2C3EN_Pos (23U)
12603#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)
12604#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
12605#define RCC_APB1ENR1_CRSEN_Pos (24U)
12606#define RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos)
12607#define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
12608#define RCC_APB1ENR1_CAN1EN_Pos (25U)
12609#define RCC_APB1ENR1_CAN1EN_Msk (0x1UL << RCC_APB1ENR1_CAN1EN_Pos)
12610#define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk
12611#define RCC_APB1ENR1_CAN2EN_Pos (26U)
12612#define RCC_APB1ENR1_CAN2EN_Msk (0x1UL << RCC_APB1ENR1_CAN2EN_Pos)
12613#define RCC_APB1ENR1_CAN2EN RCC_APB1ENR1_CAN2EN_Msk
12614#define RCC_APB1ENR1_PWREN_Pos (28U)
12615#define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos)
12616#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
12617#define RCC_APB1ENR1_DAC1EN_Pos (29U)
12618#define RCC_APB1ENR1_DAC1EN_Msk (0x1UL << RCC_APB1ENR1_DAC1EN_Pos)
12619#define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
12620#define RCC_APB1ENR1_OPAMPEN_Pos (30U)
12621#define RCC_APB1ENR1_OPAMPEN_Msk (0x1UL << RCC_APB1ENR1_OPAMPEN_Pos)
12622#define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
12623#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
12624#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)
12625#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
12626
12627/******************** Bit definition for RCC_APB1RSTR2 register **************/
12628#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
12629#define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)
12630#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
12631#define RCC_APB1ENR2_I2C4EN_Pos (1U)
12632#define RCC_APB1ENR2_I2C4EN_Msk (0x1UL << RCC_APB1ENR2_I2C4EN_Pos)
12633#define RCC_APB1ENR2_I2C4EN RCC_APB1ENR2_I2C4EN_Msk
12634#define RCC_APB1ENR2_SWPMI1EN_Pos (2U)
12635#define RCC_APB1ENR2_SWPMI1EN_Msk (0x1UL << RCC_APB1ENR2_SWPMI1EN_Pos)
12636#define RCC_APB1ENR2_SWPMI1EN RCC_APB1ENR2_SWPMI1EN_Msk
12637#define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
12638#define RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos)
12639#define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
12640
12641/******************** Bit definition for RCC_APB2ENR register ***************/
12642#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
12643#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
12644#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
12645#define RCC_APB2ENR_FWEN_Pos (7U)
12646#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos)
12647#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
12648#define RCC_APB2ENR_SDMMC1EN_Pos (10U)
12649#define RCC_APB2ENR_SDMMC1EN_Msk (0x1UL << RCC_APB2ENR_SDMMC1EN_Pos)
12650#define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
12651#define RCC_APB2ENR_TIM1EN_Pos (11U)
12652#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
12653#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
12654#define RCC_APB2ENR_SPI1EN_Pos (12U)
12655#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
12656#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
12657#define RCC_APB2ENR_TIM8EN_Pos (13U)
12658#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
12659#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
12660#define RCC_APB2ENR_USART1EN_Pos (14U)
12661#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
12662#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
12663#define RCC_APB2ENR_TIM15EN_Pos (16U)
12664#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)
12665#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
12666#define RCC_APB2ENR_TIM16EN_Pos (17U)
12667#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)
12668#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
12669#define RCC_APB2ENR_TIM17EN_Pos (18U)
12670#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)
12671#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
12672#define RCC_APB2ENR_SAI1EN_Pos (21U)
12673#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
12674#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
12675#define RCC_APB2ENR_SAI2EN_Pos (22U)
12676#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos)
12677#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
12678#define RCC_APB2ENR_DFSDM1EN_Pos (24U)
12679#define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)
12680#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
12681
12682/******************** Bit definition for RCC_AHB1SMENR register ***************/
12683#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
12684#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)
12685#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
12686#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
12687#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)
12688#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
12689#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
12690#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)
12691#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
12692#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
12693#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)
12694#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
12695#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
12696#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)
12697#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
12698#define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
12699#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos)
12700#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
12701#define RCC_AHB1SMENR_DMA2DSMEN_Pos (17U)
12702#define RCC_AHB1SMENR_DMA2DSMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2DSMEN_Pos)
12703#define RCC_AHB1SMENR_DMA2DSMEN RCC_AHB1SMENR_DMA2DSMEN_Msk
12704
12705/******************** Bit definition for RCC_AHB2SMENR register *************/
12706#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
12707#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)
12708#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
12709#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
12710#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)
12711#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
12712#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
12713#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)
12714#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
12715#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
12716#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)
12717#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
12718#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
12719#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)
12720#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
12721#define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
12722#define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)
12723#define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
12724#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
12725#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)
12726#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
12727#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
12728#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos)
12729#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
12730#define RCC_AHB2SMENR_GPIOISMEN_Pos (8U)
12731#define RCC_AHB2SMENR_GPIOISMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOISMEN_Pos)
12732#define RCC_AHB2SMENR_GPIOISMEN RCC_AHB2SMENR_GPIOISMEN_Msk
12733#define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
12734#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)
12735#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
12736#define RCC_AHB2SMENR_OTGFSSMEN_Pos (12U)
12737#define RCC_AHB2SMENR_OTGFSSMEN_Msk (0x1UL << RCC_AHB2SMENR_OTGFSSMEN_Pos)
12738#define RCC_AHB2SMENR_OTGFSSMEN RCC_AHB2SMENR_OTGFSSMEN_Msk
12739#define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
12740#define RCC_AHB2SMENR_ADCSMEN_Msk (0x1UL << RCC_AHB2SMENR_ADCSMEN_Pos)
12741#define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
12742#define RCC_AHB2SMENR_DCMISMEN_Pos (14U)
12743#define RCC_AHB2SMENR_DCMISMEN_Msk (0x1UL << RCC_AHB2SMENR_DCMISMEN_Pos)
12744#define RCC_AHB2SMENR_DCMISMEN RCC_AHB2SMENR_DCMISMEN_Msk
12745#define RCC_AHB2SMENR_AESSMEN_Pos (16U)
12746#define RCC_AHB2SMENR_AESSMEN_Msk (0x1UL << RCC_AHB2SMENR_AESSMEN_Pos)
12747#define RCC_AHB2SMENR_AESSMEN RCC_AHB2SMENR_AESSMEN_Msk
12748#define RCC_AHB2SMENR_HASHSMEN_Pos (17U)
12749#define RCC_AHB2SMENR_HASHSMEN_Msk (0x1UL << RCC_AHB2SMENR_HASHSMEN_Pos)
12750#define RCC_AHB2SMENR_HASHSMEN RCC_AHB2SMENR_HASHSMEN_Msk
12751#define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
12752#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)
12753#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
12754
12755/******************** Bit definition for RCC_AHB3SMENR register *************/
12756#define RCC_AHB3SMENR_FMCSMEN_Pos (0U)
12757#define RCC_AHB3SMENR_FMCSMEN_Msk (0x1UL << RCC_AHB3SMENR_FMCSMEN_Pos)
12758#define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk
12759#define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
12760#define RCC_AHB3SMENR_QSPISMEN_Msk (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos)
12761#define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
12762
12763/******************** Bit definition for RCC_APB1SMENR1 register *************/
12764#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
12765#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)
12766#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
12767#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
12768#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)
12769#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
12770#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
12771#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)
12772#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
12773#define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
12774#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos)
12775#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
12776#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
12777#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)
12778#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
12779#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
12780#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)
12781#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
12782#define RCC_APB1SMENR1_LCDSMEN_Pos (9U)
12783#define RCC_APB1SMENR1_LCDSMEN_Msk (0x1UL << RCC_APB1SMENR1_LCDSMEN_Pos)
12784#define RCC_APB1SMENR1_LCDSMEN RCC_APB1SMENR1_LCDSMEN_Msk
12785#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
12786#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)
12787#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
12788#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
12789#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)
12790#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
12791#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
12792#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)
12793#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
12794#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
12795#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)
12796#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
12797#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
12798#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)
12799#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
12800#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
12801#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)
12802#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
12803#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
12804#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)
12805#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
12806#define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
12807#define RCC_APB1SMENR1_UART5SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos)
12808#define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
12809#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
12810#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)
12811#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
12812#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
12813#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)
12814#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
12815#define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
12816#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)
12817#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
12818#define RCC_APB1SMENR1_CRSSMEN_Pos (24U)
12819#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)
12820#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
12821#define RCC_APB1SMENR1_CAN1SMEN_Pos (25U)
12822#define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1UL << RCC_APB1SMENR1_CAN1SMEN_Pos)
12823#define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk
12824#define RCC_APB1SMENR1_CAN2SMEN_Pos (26U)
12825#define RCC_APB1SMENR1_CAN2SMEN_Msk (0x1UL << RCC_APB1SMENR1_CAN2SMEN_Pos)
12826#define RCC_APB1SMENR1_CAN2SMEN RCC_APB1SMENR1_CAN2SMEN_Msk
12827#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
12828#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)
12829#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
12830#define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
12831#define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1UL << RCC_APB1SMENR1_DAC1SMEN_Pos)
12832#define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
12833#define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
12834#define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1UL << RCC_APB1SMENR1_OPAMPSMEN_Pos)
12835#define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
12836#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
12837#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)
12838#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
12839
12840/******************** Bit definition for RCC_APB1SMENR2 register *************/
12841#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
12842#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)
12843#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
12844#define RCC_APB1SMENR2_I2C4SMEN_Pos (1U)
12845#define RCC_APB1SMENR2_I2C4SMEN_Msk (0x1UL << RCC_APB1SMENR2_I2C4SMEN_Pos)
12846#define RCC_APB1SMENR2_I2C4SMEN RCC_APB1SMENR2_I2C4SMEN_Msk
12847#define RCC_APB1SMENR2_SWPMI1SMEN_Pos (2U)
12848#define RCC_APB1SMENR2_SWPMI1SMEN_Msk (0x1UL << RCC_APB1SMENR2_SWPMI1SMEN_Pos)
12849#define RCC_APB1SMENR2_SWPMI1SMEN RCC_APB1SMENR2_SWPMI1SMEN_Msk
12850#define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
12851#define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos)
12852#define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
12853
12854/******************** Bit definition for RCC_APB2SMENR register *************/
12855#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
12856#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)
12857#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
12858#define RCC_APB2SMENR_SDMMC1SMEN_Pos (10U)
12859#define RCC_APB2SMENR_SDMMC1SMEN_Msk (0x1UL << RCC_APB2SMENR_SDMMC1SMEN_Pos)
12860#define RCC_APB2SMENR_SDMMC1SMEN RCC_APB2SMENR_SDMMC1SMEN_Msk
12861#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
12862#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)
12863#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
12864#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
12865#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)
12866#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
12867#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
12868#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)
12869#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
12870#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
12871#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)
12872#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
12873#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
12874#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)
12875#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
12876#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
12877#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)
12878#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
12879#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
12880#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)
12881#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
12882#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
12883#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)
12884#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
12885#define RCC_APB2SMENR_SAI2SMEN_Pos (22U)
12886#define RCC_APB2SMENR_SAI2SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI2SMEN_Pos)
12887#define RCC_APB2SMENR_SAI2SMEN RCC_APB2SMENR_SAI2SMEN_Msk
12888#define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U)
12889#define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1UL << RCC_APB2SMENR_DFSDM1SMEN_Pos)
12890#define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk
12891
12892/******************** Bit definition for RCC_CCIPR register ******************/
12893#define RCC_CCIPR_USART1SEL_Pos (0U)
12894#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)
12895#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
12896#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)
12897#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)
12899#define RCC_CCIPR_USART2SEL_Pos (2U)
12900#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)
12901#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
12902#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)
12903#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)
12905#define RCC_CCIPR_USART3SEL_Pos (4U)
12906#define RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)
12907#define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
12908#define RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)
12909#define RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)
12911#define RCC_CCIPR_UART4SEL_Pos (6U)
12912#define RCC_CCIPR_UART4SEL_Msk (0x3UL << RCC_CCIPR_UART4SEL_Pos)
12913#define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
12914#define RCC_CCIPR_UART4SEL_0 (0x1UL << RCC_CCIPR_UART4SEL_Pos)
12915#define RCC_CCIPR_UART4SEL_1 (0x2UL << RCC_CCIPR_UART4SEL_Pos)
12917#define RCC_CCIPR_UART5SEL_Pos (8U)
12918#define RCC_CCIPR_UART5SEL_Msk (0x3UL << RCC_CCIPR_UART5SEL_Pos)
12919#define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
12920#define RCC_CCIPR_UART5SEL_0 (0x1UL << RCC_CCIPR_UART5SEL_Pos)
12921#define RCC_CCIPR_UART5SEL_1 (0x2UL << RCC_CCIPR_UART5SEL_Pos)
12923#define RCC_CCIPR_LPUART1SEL_Pos (10U)
12924#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)
12925#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
12926#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)
12927#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)
12929#define RCC_CCIPR_I2C1SEL_Pos (12U)
12930#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos)
12931#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
12932#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos)
12933#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos)
12935#define RCC_CCIPR_I2C2SEL_Pos (14U)
12936#define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos)
12937#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
12938#define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos)
12939#define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos)
12941#define RCC_CCIPR_I2C3SEL_Pos (16U)
12942#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos)
12943#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
12944#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos)
12945#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos)
12947#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
12948#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)
12949#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
12950#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)
12951#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)
12953#define RCC_CCIPR_LPTIM2SEL_Pos (20U)
12954#define RCC_CCIPR_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos)
12955#define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
12956#define RCC_CCIPR_LPTIM2SEL_0 (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos)
12957#define RCC_CCIPR_LPTIM2SEL_1 (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos)
12959#define RCC_CCIPR_SAI1SEL_Pos (22U)
12960#define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)
12961#define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
12962#define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)
12963#define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)
12965#define RCC_CCIPR_SAI2SEL_Pos (24U)
12966#define RCC_CCIPR_SAI2SEL_Msk (0x3UL << RCC_CCIPR_SAI2SEL_Pos)
12967#define RCC_CCIPR_SAI2SEL RCC_CCIPR_SAI2SEL_Msk
12968#define RCC_CCIPR_SAI2SEL_0 (0x1UL << RCC_CCIPR_SAI2SEL_Pos)
12969#define RCC_CCIPR_SAI2SEL_1 (0x2UL << RCC_CCIPR_SAI2SEL_Pos)
12971#define RCC_CCIPR_CLK48SEL_Pos (26U)
12972#define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos)
12973#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
12974#define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos)
12975#define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos)
12977#define RCC_CCIPR_ADCSEL_Pos (28U)
12978#define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos)
12979#define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
12980#define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos)
12981#define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos)
12983#define RCC_CCIPR_SWPMI1SEL_Pos (30U)
12984#define RCC_CCIPR_SWPMI1SEL_Msk (0x1UL << RCC_CCIPR_SWPMI1SEL_Pos)
12985#define RCC_CCIPR_SWPMI1SEL RCC_CCIPR_SWPMI1SEL_Msk
12986
12987#define RCC_CCIPR_DFSDM1SEL_Pos (31U)
12988#define RCC_CCIPR_DFSDM1SEL_Msk (0x1UL << RCC_CCIPR_DFSDM1SEL_Pos)
12989#define RCC_CCIPR_DFSDM1SEL RCC_CCIPR_DFSDM1SEL_Msk
12990
12991/******************** Bit definition for RCC_BDCR register ******************/
12992#define RCC_BDCR_LSEON_Pos (0U)
12993#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
12994#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
12995#define RCC_BDCR_LSERDY_Pos (1U)
12996#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
12997#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
12998#define RCC_BDCR_LSEBYP_Pos (2U)
12999#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
13000#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
13001
13002#define RCC_BDCR_LSEDRV_Pos (3U)
13003#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
13004#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
13005#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
13006#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
13008#define RCC_BDCR_LSECSSON_Pos (5U)
13009#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos)
13010#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
13011#define RCC_BDCR_LSECSSD_Pos (6U)
13012#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos)
13013#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
13014
13015#define RCC_BDCR_RTCSEL_Pos (8U)
13016#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
13017#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
13018#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
13019#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
13021#define RCC_BDCR_RTCEN_Pos (15U)
13022#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
13023#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
13024#define RCC_BDCR_BDRST_Pos (16U)
13025#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
13026#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
13027#define RCC_BDCR_LSCOEN_Pos (24U)
13028#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos)
13029#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
13030#define RCC_BDCR_LSCOSEL_Pos (25U)
13031#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos)
13032#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
13033
13034/******************** Bit definition for RCC_CSR register *******************/
13035#define RCC_CSR_LSION_Pos (0U)
13036#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
13037#define RCC_CSR_LSION RCC_CSR_LSION_Msk
13038#define RCC_CSR_LSIRDY_Pos (1U)
13039#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
13040#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
13041
13042#define RCC_CSR_MSISRANGE_Pos (8U)
13043#define RCC_CSR_MSISRANGE_Msk (0xFUL << RCC_CSR_MSISRANGE_Pos)
13044#define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
13045#define RCC_CSR_MSISRANGE_1 (0x4UL << RCC_CSR_MSISRANGE_Pos)
13046#define RCC_CSR_MSISRANGE_2 (0x5UL << RCC_CSR_MSISRANGE_Pos)
13047#define RCC_CSR_MSISRANGE_4 (0x6UL << RCC_CSR_MSISRANGE_Pos)
13048#define RCC_CSR_MSISRANGE_8 (0x7UL << RCC_CSR_MSISRANGE_Pos)
13050#define RCC_CSR_RMVF_Pos (23U)
13051#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
13052#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
13053#define RCC_CSR_FWRSTF_Pos (24U)
13054#define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos)
13055#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
13056#define RCC_CSR_OBLRSTF_Pos (25U)
13057#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos)
13058#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
13059#define RCC_CSR_PINRSTF_Pos (26U)
13060#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
13061#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
13062#define RCC_CSR_BORRSTF_Pos (27U)
13063#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
13064#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
13065#define RCC_CSR_SFTRSTF_Pos (28U)
13066#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
13067#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
13068#define RCC_CSR_IWDGRSTF_Pos (29U)
13069#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
13070#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
13071#define RCC_CSR_WWDGRSTF_Pos (30U)
13072#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
13073#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
13074#define RCC_CSR_LPWRRSTF_Pos (31U)
13075#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
13076#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
13077
13078/******************** Bit definition for RCC_CRRCR register *****************/
13079#define RCC_CRRCR_HSI48ON_Pos (0U)
13080#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos)
13081#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
13082#define RCC_CRRCR_HSI48RDY_Pos (1U)
13083#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos)
13084#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
13085
13087#define RCC_CRRCR_HSI48CAL_Pos (7U)
13088#define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)
13089#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk
13090#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)
13091#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)
13092#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)
13093#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)
13094#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)
13095#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)
13096#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)
13097#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)
13098#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)
13100/******************** Bit definition for RCC_CCIPR2 register ******************/
13101#define RCC_CCIPR2_I2C4SEL_Pos (0U)
13102#define RCC_CCIPR2_I2C4SEL_Msk (0x3UL << RCC_CCIPR2_I2C4SEL_Pos)
13103#define RCC_CCIPR2_I2C4SEL RCC_CCIPR2_I2C4SEL_Msk
13104#define RCC_CCIPR2_I2C4SEL_0 (0x1UL << RCC_CCIPR2_I2C4SEL_Pos)
13105#define RCC_CCIPR2_I2C4SEL_1 (0x2UL << RCC_CCIPR2_I2C4SEL_Pos)
13107/******************************************************************************/
13108/* */
13109/* RNG */
13110/* */
13111/******************************************************************************/
13112/******************** Bits definition for RNG_CR register *******************/
13113#define RNG_CR_RNGEN_Pos (2U)
13114#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
13115#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
13116#define RNG_CR_IE_Pos (3U)
13117#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
13118#define RNG_CR_IE RNG_CR_IE_Msk
13119
13120/******************** Bits definition for RNG_SR register *******************/
13121#define RNG_SR_DRDY_Pos (0U)
13122#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
13123#define RNG_SR_DRDY RNG_SR_DRDY_Msk
13124#define RNG_SR_CECS_Pos (1U)
13125#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
13126#define RNG_SR_CECS RNG_SR_CECS_Msk
13127#define RNG_SR_SECS_Pos (2U)
13128#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
13129#define RNG_SR_SECS RNG_SR_SECS_Msk
13130#define RNG_SR_CEIS_Pos (5U)
13131#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
13132#define RNG_SR_CEIS RNG_SR_CEIS_Msk
13133#define RNG_SR_SEIS_Pos (6U)
13134#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
13135#define RNG_SR_SEIS RNG_SR_SEIS_Msk
13136
13137/******************************************************************************/
13138/* */
13139/* Real-Time Clock (RTC) */
13140/* */
13141/******************************************************************************/
13142/*
13143* @brief Specific device feature definitions
13144*/
13145#define RTC_TAMPER1_SUPPORT
13146#define RTC_TAMPER2_SUPPORT
13147#define RTC_TAMPER3_SUPPORT
13148
13149#define RTC_WAKEUP_SUPPORT
13150#define RTC_BACKUP_SUPPORT
13151/******************** Number of backup registers ******************************/
13152#define RTC_BKP_NUMBER 32U
13153
13154
13155/******************** Bits definition for RTC_TR register *******************/
13156#define RTC_TR_PM_Pos (22U)
13157#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
13158#define RTC_TR_PM RTC_TR_PM_Msk
13159#define RTC_TR_HT_Pos (20U)
13160#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
13161#define RTC_TR_HT RTC_TR_HT_Msk
13162#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
13163#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
13164#define RTC_TR_HU_Pos (16U)
13165#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
13166#define RTC_TR_HU RTC_TR_HU_Msk
13167#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
13168#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
13169#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
13170#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
13171#define RTC_TR_MNT_Pos (12U)
13172#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
13173#define RTC_TR_MNT RTC_TR_MNT_Msk
13174#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
13175#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
13176#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
13177#define RTC_TR_MNU_Pos (8U)
13178#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
13179#define RTC_TR_MNU RTC_TR_MNU_Msk
13180#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
13181#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
13182#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
13183#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
13184#define RTC_TR_ST_Pos (4U)
13185#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
13186#define RTC_TR_ST RTC_TR_ST_Msk
13187#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
13188#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
13189#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
13190#define RTC_TR_SU_Pos (0U)
13191#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
13192#define RTC_TR_SU RTC_TR_SU_Msk
13193#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
13194#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
13195#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
13196#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
13198/******************** Bits definition for RTC_DR register *******************/
13199#define RTC_DR_YT_Pos (20U)
13200#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
13201#define RTC_DR_YT RTC_DR_YT_Msk
13202#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
13203#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
13204#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
13205#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
13206#define RTC_DR_YU_Pos (16U)
13207#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
13208#define RTC_DR_YU RTC_DR_YU_Msk
13209#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
13210#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
13211#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
13212#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
13213#define RTC_DR_WDU_Pos (13U)
13214#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
13215#define RTC_DR_WDU RTC_DR_WDU_Msk
13216#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
13217#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
13218#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
13219#define RTC_DR_MT_Pos (12U)
13220#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
13221#define RTC_DR_MT RTC_DR_MT_Msk
13222#define RTC_DR_MU_Pos (8U)
13223#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
13224#define RTC_DR_MU RTC_DR_MU_Msk
13225#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
13226#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
13227#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
13228#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
13229#define RTC_DR_DT_Pos (4U)
13230#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
13231#define RTC_DR_DT RTC_DR_DT_Msk
13232#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
13233#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
13234#define RTC_DR_DU_Pos (0U)
13235#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
13236#define RTC_DR_DU RTC_DR_DU_Msk
13237#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
13238#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
13239#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
13240#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
13242/******************** Bits definition for RTC_CR register *******************/
13243#define RTC_CR_ITSE_Pos (24U)
13244#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)
13245#define RTC_CR_ITSE RTC_CR_ITSE_Msk
13246#define RTC_CR_COE_Pos (23U)
13247#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
13248#define RTC_CR_COE RTC_CR_COE_Msk
13249#define RTC_CR_OSEL_Pos (21U)
13250#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
13251#define RTC_CR_OSEL RTC_CR_OSEL_Msk
13252#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
13253#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
13254#define RTC_CR_POL_Pos (20U)
13255#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
13256#define RTC_CR_POL RTC_CR_POL_Msk
13257#define RTC_CR_COSEL_Pos (19U)
13258#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
13259#define RTC_CR_COSEL RTC_CR_COSEL_Msk
13260#define RTC_CR_BKP_Pos (18U)
13261#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
13262#define RTC_CR_BKP RTC_CR_BKP_Msk
13263#define RTC_CR_SUB1H_Pos (17U)
13264#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
13265#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
13266#define RTC_CR_ADD1H_Pos (16U)
13267#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
13268#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
13269#define RTC_CR_TSIE_Pos (15U)
13270#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
13271#define RTC_CR_TSIE RTC_CR_TSIE_Msk
13272#define RTC_CR_WUTIE_Pos (14U)
13273#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
13274#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
13275#define RTC_CR_ALRBIE_Pos (13U)
13276#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
13277#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
13278#define RTC_CR_ALRAIE_Pos (12U)
13279#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
13280#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
13281#define RTC_CR_TSE_Pos (11U)
13282#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
13283#define RTC_CR_TSE RTC_CR_TSE_Msk
13284#define RTC_CR_WUTE_Pos (10U)
13285#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
13286#define RTC_CR_WUTE RTC_CR_WUTE_Msk
13287#define RTC_CR_ALRBE_Pos (9U)
13288#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
13289#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
13290#define RTC_CR_ALRAE_Pos (8U)
13291#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
13292#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
13293#define RTC_CR_FMT_Pos (6U)
13294#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
13295#define RTC_CR_FMT RTC_CR_FMT_Msk
13296#define RTC_CR_BYPSHAD_Pos (5U)
13297#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
13298#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
13299#define RTC_CR_REFCKON_Pos (4U)
13300#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
13301#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
13302#define RTC_CR_TSEDGE_Pos (3U)
13303#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
13304#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
13305#define RTC_CR_WUCKSEL_Pos (0U)
13306#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
13307#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
13308#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
13309#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
13310#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
13312/* Legacy defines */
13313#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
13314#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
13315#define RTC_CR_BCK RTC_CR_BKP
13316
13317/******************** Bits definition for RTC_ISR register ******************/
13318#define RTC_ISR_ITSF_Pos (17U)
13319#define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos)
13320#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
13321#define RTC_ISR_RECALPF_Pos (16U)
13322#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
13323#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
13324#define RTC_ISR_TAMP3F_Pos (15U)
13325#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)
13326#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
13327#define RTC_ISR_TAMP2F_Pos (14U)
13328#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
13329#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
13330#define RTC_ISR_TAMP1F_Pos (13U)
13331#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
13332#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
13333#define RTC_ISR_TSOVF_Pos (12U)
13334#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
13335#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
13336#define RTC_ISR_TSF_Pos (11U)
13337#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
13338#define RTC_ISR_TSF RTC_ISR_TSF_Msk
13339#define RTC_ISR_WUTF_Pos (10U)
13340#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
13341#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
13342#define RTC_ISR_ALRBF_Pos (9U)
13343#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
13344#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
13345#define RTC_ISR_ALRAF_Pos (8U)
13346#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
13347#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
13348#define RTC_ISR_INIT_Pos (7U)
13349#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
13350#define RTC_ISR_INIT RTC_ISR_INIT_Msk
13351#define RTC_ISR_INITF_Pos (6U)
13352#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
13353#define RTC_ISR_INITF RTC_ISR_INITF_Msk
13354#define RTC_ISR_RSF_Pos (5U)
13355#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
13356#define RTC_ISR_RSF RTC_ISR_RSF_Msk
13357#define RTC_ISR_INITS_Pos (4U)
13358#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
13359#define RTC_ISR_INITS RTC_ISR_INITS_Msk
13360#define RTC_ISR_SHPF_Pos (3U)
13361#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
13362#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
13363#define RTC_ISR_WUTWF_Pos (2U)
13364#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
13365#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
13366#define RTC_ISR_ALRBWF_Pos (1U)
13367#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
13368#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
13369#define RTC_ISR_ALRAWF_Pos (0U)
13370#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
13371#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
13372
13373/******************** Bits definition for RTC_PRER register *****************/
13374#define RTC_PRER_PREDIV_A_Pos (16U)
13375#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
13376#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
13377#define RTC_PRER_PREDIV_S_Pos (0U)
13378#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
13379#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
13380
13381/******************** Bits definition for RTC_WUTR register *****************/
13382#define RTC_WUTR_WUT_Pos (0U)
13383#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
13384#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
13385
13386/******************** Bits definition for RTC_ALRMAR register ***************/
13387#define RTC_ALRMAR_MSK4_Pos (31U)
13388#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
13389#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
13390#define RTC_ALRMAR_WDSEL_Pos (30U)
13391#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
13392#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
13393#define RTC_ALRMAR_DT_Pos (28U)
13394#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
13395#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
13396#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
13397#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
13398#define RTC_ALRMAR_DU_Pos (24U)
13399#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
13400#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
13401#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
13402#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
13403#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
13404#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
13405#define RTC_ALRMAR_MSK3_Pos (23U)
13406#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
13407#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
13408#define RTC_ALRMAR_PM_Pos (22U)
13409#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
13410#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
13411#define RTC_ALRMAR_HT_Pos (20U)
13412#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
13413#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
13414#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
13415#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
13416#define RTC_ALRMAR_HU_Pos (16U)
13417#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
13418#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
13419#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
13420#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
13421#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
13422#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
13423#define RTC_ALRMAR_MSK2_Pos (15U)
13424#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
13425#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
13426#define RTC_ALRMAR_MNT_Pos (12U)
13427#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
13428#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
13429#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
13430#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
13431#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
13432#define RTC_ALRMAR_MNU_Pos (8U)
13433#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
13434#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
13435#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
13436#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
13437#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
13438#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
13439#define RTC_ALRMAR_MSK1_Pos (7U)
13440#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
13441#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
13442#define RTC_ALRMAR_ST_Pos (4U)
13443#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
13444#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
13445#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
13446#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
13447#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
13448#define RTC_ALRMAR_SU_Pos (0U)
13449#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
13450#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
13451#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
13452#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
13453#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
13454#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
13456/******************** Bits definition for RTC_ALRMBR register ***************/
13457#define RTC_ALRMBR_MSK4_Pos (31U)
13458#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
13459#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
13460#define RTC_ALRMBR_WDSEL_Pos (30U)
13461#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
13462#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
13463#define RTC_ALRMBR_DT_Pos (28U)
13464#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
13465#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
13466#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
13467#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
13468#define RTC_ALRMBR_DU_Pos (24U)
13469#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
13470#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
13471#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
13472#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
13473#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
13474#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
13475#define RTC_ALRMBR_MSK3_Pos (23U)
13476#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
13477#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
13478#define RTC_ALRMBR_PM_Pos (22U)
13479#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
13480#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
13481#define RTC_ALRMBR_HT_Pos (20U)
13482#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
13483#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
13484#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
13485#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
13486#define RTC_ALRMBR_HU_Pos (16U)
13487#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
13488#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
13489#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
13490#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
13491#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
13492#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
13493#define RTC_ALRMBR_MSK2_Pos (15U)
13494#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
13495#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
13496#define RTC_ALRMBR_MNT_Pos (12U)
13497#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
13498#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
13499#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
13500#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
13501#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
13502#define RTC_ALRMBR_MNU_Pos (8U)
13503#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
13504#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
13505#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
13506#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
13507#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
13508#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
13509#define RTC_ALRMBR_MSK1_Pos (7U)
13510#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
13511#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
13512#define RTC_ALRMBR_ST_Pos (4U)
13513#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
13514#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
13515#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
13516#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
13517#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
13518#define RTC_ALRMBR_SU_Pos (0U)
13519#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
13520#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
13521#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
13522#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
13523#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
13524#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
13526/******************** Bits definition for RTC_WPR register ******************/
13527#define RTC_WPR_KEY_Pos (0U)
13528#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
13529#define RTC_WPR_KEY RTC_WPR_KEY_Msk
13530
13531/******************** Bits definition for RTC_SSR register ******************/
13532#define RTC_SSR_SS_Pos (0U)
13533#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
13534#define RTC_SSR_SS RTC_SSR_SS_Msk
13535
13536/******************** Bits definition for RTC_SHIFTR register ***************/
13537#define RTC_SHIFTR_SUBFS_Pos (0U)
13538#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
13539#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
13540#define RTC_SHIFTR_ADD1S_Pos (31U)
13541#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
13542#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
13543
13544/******************** Bits definition for RTC_TSTR register *****************/
13545#define RTC_TSTR_PM_Pos (22U)
13546#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
13547#define RTC_TSTR_PM RTC_TSTR_PM_Msk
13548#define RTC_TSTR_HT_Pos (20U)
13549#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
13550#define RTC_TSTR_HT RTC_TSTR_HT_Msk
13551#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
13552#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
13553#define RTC_TSTR_HU_Pos (16U)
13554#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
13555#define RTC_TSTR_HU RTC_TSTR_HU_Msk
13556#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
13557#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
13558#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
13559#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
13560#define RTC_TSTR_MNT_Pos (12U)
13561#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
13562#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
13563#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
13564#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
13565#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
13566#define RTC_TSTR_MNU_Pos (8U)
13567#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
13568#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
13569#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
13570#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
13571#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
13572#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
13573#define RTC_TSTR_ST_Pos (4U)
13574#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
13575#define RTC_TSTR_ST RTC_TSTR_ST_Msk
13576#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
13577#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
13578#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
13579#define RTC_TSTR_SU_Pos (0U)
13580#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
13581#define RTC_TSTR_SU RTC_TSTR_SU_Msk
13582#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
13583#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
13584#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
13585#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
13587/******************** Bits definition for RTC_TSDR register *****************/
13588#define RTC_TSDR_WDU_Pos (13U)
13589#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
13590#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
13591#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
13592#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
13593#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
13594#define RTC_TSDR_MT_Pos (12U)
13595#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
13596#define RTC_TSDR_MT RTC_TSDR_MT_Msk
13597#define RTC_TSDR_MU_Pos (8U)
13598#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
13599#define RTC_TSDR_MU RTC_TSDR_MU_Msk
13600#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
13601#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
13602#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
13603#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
13604#define RTC_TSDR_DT_Pos (4U)
13605#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
13606#define RTC_TSDR_DT RTC_TSDR_DT_Msk
13607#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
13608#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
13609#define RTC_TSDR_DU_Pos (0U)
13610#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
13611#define RTC_TSDR_DU RTC_TSDR_DU_Msk
13612#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
13613#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
13614#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
13615#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
13617/******************** Bits definition for RTC_TSSSR register ****************/
13618#define RTC_TSSSR_SS_Pos (0U)
13619#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
13620#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
13621
13622/******************** Bits definition for RTC_CAL register *****************/
13623#define RTC_CALR_CALP_Pos (15U)
13624#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
13625#define RTC_CALR_CALP RTC_CALR_CALP_Msk
13626#define RTC_CALR_CALW8_Pos (14U)
13627#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
13628#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
13629#define RTC_CALR_CALW16_Pos (13U)
13630#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
13631#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
13632#define RTC_CALR_CALM_Pos (0U)
13633#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
13634#define RTC_CALR_CALM RTC_CALR_CALM_Msk
13635#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
13636#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
13637#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
13638#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
13639#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
13640#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
13641#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
13642#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
13643#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
13645/******************** Bits definition for RTC_TAMPCR register ***************/
13646#define RTC_TAMPCR_TAMP3MF_Pos (24U)
13647#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)
13648#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
13649#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
13650#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)
13651#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
13652#define RTC_TAMPCR_TAMP3IE_Pos (22U)
13653#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)
13654#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
13655#define RTC_TAMPCR_TAMP2MF_Pos (21U)
13656#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)
13657#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
13658#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
13659#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)
13660#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
13661#define RTC_TAMPCR_TAMP2IE_Pos (19U)
13662#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)
13663#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
13664#define RTC_TAMPCR_TAMP1MF_Pos (18U)
13665#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)
13666#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
13667#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
13668#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)
13669#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
13670#define RTC_TAMPCR_TAMP1IE_Pos (16U)
13671#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)
13672#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
13673#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
13674#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)
13675#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
13676#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
13677#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)
13678#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
13679#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)
13680#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)
13681#define RTC_TAMPCR_TAMPFLT_Pos (11U)
13682#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)
13683#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
13684#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)
13685#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)
13686#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
13687#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)
13688#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
13689#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)
13690#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)
13691#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)
13692#define RTC_TAMPCR_TAMPTS_Pos (7U)
13693#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos)
13694#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
13695#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
13696#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)
13697#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
13698#define RTC_TAMPCR_TAMP3E_Pos (5U)
13699#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos)
13700#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
13701#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
13702#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)
13703#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
13704#define RTC_TAMPCR_TAMP2E_Pos (3U)
13705#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos)
13706#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
13707#define RTC_TAMPCR_TAMPIE_Pos (2U)
13708#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos)
13709#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
13710#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
13711#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)
13712#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
13713#define RTC_TAMPCR_TAMP1E_Pos (0U)
13714#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos)
13715#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
13716
13717/******************** Bits definition for RTC_ALRMASSR register *************/
13718#define RTC_ALRMASSR_MASKSS_Pos (24U)
13719#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
13720#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
13721#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
13722#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
13723#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
13724#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
13725#define RTC_ALRMASSR_SS_Pos (0U)
13726#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
13727#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
13728
13729/******************** Bits definition for RTC_ALRMBSSR register *************/
13730#define RTC_ALRMBSSR_MASKSS_Pos (24U)
13731#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
13732#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
13733#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
13734#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
13735#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
13736#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
13737#define RTC_ALRMBSSR_SS_Pos (0U)
13738#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
13739#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
13740
13741/******************** Bits definition for RTC_0R register *******************/
13742#define RTC_OR_OUT_RMP_Pos (1U)
13743#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos)
13744#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
13745#define RTC_OR_ALARMOUTTYPE_Pos (0U)
13746#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)
13747#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
13748
13749
13750/******************** Bits definition for RTC_BKP0R register ****************/
13751#define RTC_BKP0R_Pos (0U)
13752#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
13753#define RTC_BKP0R RTC_BKP0R_Msk
13754
13755/******************** Bits definition for RTC_BKP1R register ****************/
13756#define RTC_BKP1R_Pos (0U)
13757#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
13758#define RTC_BKP1R RTC_BKP1R_Msk
13759
13760/******************** Bits definition for RTC_BKP2R register ****************/
13761#define RTC_BKP2R_Pos (0U)
13762#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
13763#define RTC_BKP2R RTC_BKP2R_Msk
13764
13765/******************** Bits definition for RTC_BKP3R register ****************/
13766#define RTC_BKP3R_Pos (0U)
13767#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
13768#define RTC_BKP3R RTC_BKP3R_Msk
13769
13770/******************** Bits definition for RTC_BKP4R register ****************/
13771#define RTC_BKP4R_Pos (0U)
13772#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
13773#define RTC_BKP4R RTC_BKP4R_Msk
13774
13775/******************** Bits definition for RTC_BKP5R register ****************/
13776#define RTC_BKP5R_Pos (0U)
13777#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
13778#define RTC_BKP5R RTC_BKP5R_Msk
13779
13780/******************** Bits definition for RTC_BKP6R register ****************/
13781#define RTC_BKP6R_Pos (0U)
13782#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
13783#define RTC_BKP6R RTC_BKP6R_Msk
13784
13785/******************** Bits definition for RTC_BKP7R register ****************/
13786#define RTC_BKP7R_Pos (0U)
13787#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
13788#define RTC_BKP7R RTC_BKP7R_Msk
13789
13790/******************** Bits definition for RTC_BKP8R register ****************/
13791#define RTC_BKP8R_Pos (0U)
13792#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
13793#define RTC_BKP8R RTC_BKP8R_Msk
13794
13795/******************** Bits definition for RTC_BKP9R register ****************/
13796#define RTC_BKP9R_Pos (0U)
13797#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
13798#define RTC_BKP9R RTC_BKP9R_Msk
13799
13800/******************** Bits definition for RTC_BKP10R register ***************/
13801#define RTC_BKP10R_Pos (0U)
13802#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
13803#define RTC_BKP10R RTC_BKP10R_Msk
13804
13805/******************** Bits definition for RTC_BKP11R register ***************/
13806#define RTC_BKP11R_Pos (0U)
13807#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
13808#define RTC_BKP11R RTC_BKP11R_Msk
13809
13810/******************** Bits definition for RTC_BKP12R register ***************/
13811#define RTC_BKP12R_Pos (0U)
13812#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
13813#define RTC_BKP12R RTC_BKP12R_Msk
13814
13815/******************** Bits definition for RTC_BKP13R register ***************/
13816#define RTC_BKP13R_Pos (0U)
13817#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
13818#define RTC_BKP13R RTC_BKP13R_Msk
13819
13820/******************** Bits definition for RTC_BKP14R register ***************/
13821#define RTC_BKP14R_Pos (0U)
13822#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
13823#define RTC_BKP14R RTC_BKP14R_Msk
13824
13825/******************** Bits definition for RTC_BKP15R register ***************/
13826#define RTC_BKP15R_Pos (0U)
13827#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
13828#define RTC_BKP15R RTC_BKP15R_Msk
13829
13830/******************** Bits definition for RTC_BKP16R register ***************/
13831#define RTC_BKP16R_Pos (0U)
13832#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
13833#define RTC_BKP16R RTC_BKP16R_Msk
13834
13835/******************** Bits definition for RTC_BKP17R register ***************/
13836#define RTC_BKP17R_Pos (0U)
13837#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
13838#define RTC_BKP17R RTC_BKP17R_Msk
13839
13840/******************** Bits definition for RTC_BKP18R register ***************/
13841#define RTC_BKP18R_Pos (0U)
13842#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
13843#define RTC_BKP18R RTC_BKP18R_Msk
13844
13845/******************** Bits definition for RTC_BKP19R register ***************/
13846#define RTC_BKP19R_Pos (0U)
13847#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
13848#define RTC_BKP19R RTC_BKP19R_Msk
13849
13850/******************** Bits definition for RTC_BKP20R register ***************/
13851#define RTC_BKP20R_Pos (0U)
13852#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos)
13853#define RTC_BKP20R RTC_BKP20R_Msk
13854
13855/******************** Bits definition for RTC_BKP21R register ***************/
13856#define RTC_BKP21R_Pos (0U)
13857#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos)
13858#define RTC_BKP21R RTC_BKP21R_Msk
13859
13860/******************** Bits definition for RTC_BKP22R register ***************/
13861#define RTC_BKP22R_Pos (0U)
13862#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos)
13863#define RTC_BKP22R RTC_BKP22R_Msk
13864
13865/******************** Bits definition for RTC_BKP23R register ***************/
13866#define RTC_BKP23R_Pos (0U)
13867#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos)
13868#define RTC_BKP23R RTC_BKP23R_Msk
13869
13870/******************** Bits definition for RTC_BKP24R register ***************/
13871#define RTC_BKP24R_Pos (0U)
13872#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos)
13873#define RTC_BKP24R RTC_BKP24R_Msk
13874
13875/******************** Bits definition for RTC_BKP25R register ***************/
13876#define RTC_BKP25R_Pos (0U)
13877#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos)
13878#define RTC_BKP25R RTC_BKP25R_Msk
13879
13880/******************** Bits definition for RTC_BKP26R register ***************/
13881#define RTC_BKP26R_Pos (0U)
13882#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos)
13883#define RTC_BKP26R RTC_BKP26R_Msk
13884
13885/******************** Bits definition for RTC_BKP27R register ***************/
13886#define RTC_BKP27R_Pos (0U)
13887#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos)
13888#define RTC_BKP27R RTC_BKP27R_Msk
13889
13890/******************** Bits definition for RTC_BKP28R register ***************/
13891#define RTC_BKP28R_Pos (0U)
13892#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos)
13893#define RTC_BKP28R RTC_BKP28R_Msk
13894
13895/******************** Bits definition for RTC_BKP29R register ***************/
13896#define RTC_BKP29R_Pos (0U)
13897#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos)
13898#define RTC_BKP29R RTC_BKP29R_Msk
13899
13900/******************** Bits definition for RTC_BKP30R register ***************/
13901#define RTC_BKP30R_Pos (0U)
13902#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos)
13903#define RTC_BKP30R RTC_BKP30R_Msk
13904
13905/******************** Bits definition for RTC_BKP31R register ***************/
13906#define RTC_BKP31R_Pos (0U)
13907#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos)
13908#define RTC_BKP31R RTC_BKP31R_Msk
13909
13910/******************************************************************************/
13911/* */
13912/* Serial Audio Interface */
13913/* */
13914/******************************************************************************/
13915/******************** Bit definition for SAI_GCR register *******************/
13916#define SAI_GCR_SYNCIN_Pos (0U)
13917#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
13918#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
13919#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
13920#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
13922#define SAI_GCR_SYNCOUT_Pos (4U)
13923#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
13924#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
13925#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
13926#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
13928/******************* Bit definition for SAI_xCR1 register *******************/
13929#define SAI_xCR1_MODE_Pos (0U)
13930#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
13931#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
13932#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
13933#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
13935#define SAI_xCR1_PRTCFG_Pos (2U)
13936#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
13937#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
13938#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
13939#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
13941#define SAI_xCR1_DS_Pos (5U)
13942#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
13943#define SAI_xCR1_DS SAI_xCR1_DS_Msk
13944#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
13945#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
13946#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
13948#define SAI_xCR1_LSBFIRST_Pos (8U)
13949#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
13950#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
13951#define SAI_xCR1_CKSTR_Pos (9U)
13952#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
13953#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
13955#define SAI_xCR1_SYNCEN_Pos (10U)
13956#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
13957#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
13958#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
13959#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
13961#define SAI_xCR1_MONO_Pos (12U)
13962#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
13963#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
13964#define SAI_xCR1_OUTDRIV_Pos (13U)
13965#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
13966#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
13967#define SAI_xCR1_SAIEN_Pos (16U)
13968#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
13969#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
13970#define SAI_xCR1_DMAEN_Pos (17U)
13971#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
13972#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
13973#define SAI_xCR1_NODIV_Pos (19U)
13974#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
13975#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
13977#define SAI_xCR1_MCKDIV_Pos (20U)
13978#define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos)
13979#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
13980#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos)
13981#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos)
13982#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos)
13983#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos)
13985/******************* Bit definition for SAI_xCR2 register *******************/
13986#define SAI_xCR2_FTH_Pos (0U)
13987#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
13988#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
13989#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
13990#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
13991#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
13993#define SAI_xCR2_FFLUSH_Pos (3U)
13994#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
13995#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
13996#define SAI_xCR2_TRIS_Pos (4U)
13997#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
13998#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
13999#define SAI_xCR2_MUTE_Pos (5U)
14000#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
14001#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
14002#define SAI_xCR2_MUTEVAL_Pos (6U)
14003#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
14004#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
14007#define SAI_xCR2_MUTECNT_Pos (7U)
14008#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
14009#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
14010#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
14011#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
14012#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
14013#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
14014#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
14015#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
14017#define SAI_xCR2_CPL_Pos (13U)
14018#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
14019#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
14020#define SAI_xCR2_COMP_Pos (14U)
14021#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
14022#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
14023#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
14024#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
14027/****************** Bit definition for SAI_xFRCR register *******************/
14028#define SAI_xFRCR_FRL_Pos (0U)
14029#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
14030#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
14031#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
14032#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
14033#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
14034#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
14035#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
14036#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
14037#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
14038#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
14040#define SAI_xFRCR_FSALL_Pos (8U)
14041#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
14042#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
14043#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
14044#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
14045#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
14046#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
14047#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
14048#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
14049#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
14051#define SAI_xFRCR_FSDEF_Pos (16U)
14052#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
14053#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
14054#define SAI_xFRCR_FSPOL_Pos (17U)
14055#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
14056#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
14057#define SAI_xFRCR_FSOFF_Pos (18U)
14058#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
14059#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
14061/****************** Bit definition for SAI_xSLOTR register *******************/
14062#define SAI_xSLOTR_FBOFF_Pos (0U)
14063#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
14064#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
14065#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
14066#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
14067#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
14068#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
14069#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
14071#define SAI_xSLOTR_SLOTSZ_Pos (6U)
14072#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
14073#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
14074#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
14075#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
14077#define SAI_xSLOTR_NBSLOT_Pos (8U)
14078#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
14079#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
14080#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
14081#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
14082#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
14083#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
14085#define SAI_xSLOTR_SLOTEN_Pos (16U)
14086#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
14087#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
14089/******************* Bit definition for SAI_xIMR register *******************/
14090#define SAI_xIMR_OVRUDRIE_Pos (0U)
14091#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
14092#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
14093#define SAI_xIMR_MUTEDETIE_Pos (1U)
14094#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
14095#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
14096#define SAI_xIMR_WCKCFGIE_Pos (2U)
14097#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
14098#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
14099#define SAI_xIMR_FREQIE_Pos (3U)
14100#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
14101#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
14102#define SAI_xIMR_CNRDYIE_Pos (4U)
14103#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
14104#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
14105#define SAI_xIMR_AFSDETIE_Pos (5U)
14106#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
14107#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
14108#define SAI_xIMR_LFSDETIE_Pos (6U)
14109#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
14110#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
14112/******************** Bit definition for SAI_xSR register *******************/
14113#define SAI_xSR_OVRUDR_Pos (0U)
14114#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
14115#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
14116#define SAI_xSR_MUTEDET_Pos (1U)
14117#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
14118#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
14119#define SAI_xSR_WCKCFG_Pos (2U)
14120#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
14121#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
14122#define SAI_xSR_FREQ_Pos (3U)
14123#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
14124#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
14125#define SAI_xSR_CNRDY_Pos (4U)
14126#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
14127#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
14128#define SAI_xSR_AFSDET_Pos (5U)
14129#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
14130#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
14131#define SAI_xSR_LFSDET_Pos (6U)
14132#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
14133#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
14135#define SAI_xSR_FLVL_Pos (16U)
14136#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
14137#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
14138#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
14139#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
14140#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
14142/****************** Bit definition for SAI_xCLRFR register ******************/
14143#define SAI_xCLRFR_COVRUDR_Pos (0U)
14144#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
14145#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
14146#define SAI_xCLRFR_CMUTEDET_Pos (1U)
14147#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
14148#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
14149#define SAI_xCLRFR_CWCKCFG_Pos (2U)
14150#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
14151#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
14152#define SAI_xCLRFR_CFREQ_Pos (3U)
14153#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
14154#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
14155#define SAI_xCLRFR_CCNRDY_Pos (4U)
14156#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
14157#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
14158#define SAI_xCLRFR_CAFSDET_Pos (5U)
14159#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
14160#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
14161#define SAI_xCLRFR_CLFSDET_Pos (6U)
14162#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
14163#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
14165/****************** Bit definition for SAI_xDR register ******************/
14166#define SAI_xDR_DATA_Pos (0U)
14167#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
14168#define SAI_xDR_DATA SAI_xDR_DATA_Msk
14169
14170/******************************************************************************/
14171/* */
14172/* LCD Controller (LCD) */
14173/* */
14174/******************************************************************************/
14175
14176/******************* Bit definition for LCD_CR register *********************/
14177#define LCD_CR_LCDEN_Pos (0U)
14178#define LCD_CR_LCDEN_Msk (0x1UL << LCD_CR_LCDEN_Pos)
14179#define LCD_CR_LCDEN LCD_CR_LCDEN_Msk
14180#define LCD_CR_VSEL_Pos (1U)
14181#define LCD_CR_VSEL_Msk (0x1UL << LCD_CR_VSEL_Pos)
14182#define LCD_CR_VSEL LCD_CR_VSEL_Msk
14184#define LCD_CR_DUTY_Pos (2U)
14185#define LCD_CR_DUTY_Msk (0x7UL << LCD_CR_DUTY_Pos)
14186#define LCD_CR_DUTY LCD_CR_DUTY_Msk
14187#define LCD_CR_DUTY_0 (0x1UL << LCD_CR_DUTY_Pos)
14188#define LCD_CR_DUTY_1 (0x2UL << LCD_CR_DUTY_Pos)
14189#define LCD_CR_DUTY_2 (0x4UL << LCD_CR_DUTY_Pos)
14191#define LCD_CR_BIAS_Pos (5U)
14192#define LCD_CR_BIAS_Msk (0x3UL << LCD_CR_BIAS_Pos)
14193#define LCD_CR_BIAS LCD_CR_BIAS_Msk
14194#define LCD_CR_BIAS_0 (0x1UL << LCD_CR_BIAS_Pos)
14195#define LCD_CR_BIAS_1 (0x2UL << LCD_CR_BIAS_Pos)
14197#define LCD_CR_MUX_SEG_Pos (7U)
14198#define LCD_CR_MUX_SEG_Msk (0x1UL << LCD_CR_MUX_SEG_Pos)
14199#define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk
14200#define LCD_CR_BUFEN_Pos (8U)
14201#define LCD_CR_BUFEN_Msk (0x1UL << LCD_CR_BUFEN_Pos)
14202#define LCD_CR_BUFEN LCD_CR_BUFEN_Msk
14204/******************* Bit definition for LCD_FCR register ********************/
14205#define LCD_FCR_HD_Pos (0U)
14206#define LCD_FCR_HD_Msk (0x1UL << LCD_FCR_HD_Pos)
14207#define LCD_FCR_HD LCD_FCR_HD_Msk
14208#define LCD_FCR_SOFIE_Pos (1U)
14209#define LCD_FCR_SOFIE_Msk (0x1UL << LCD_FCR_SOFIE_Pos)
14210#define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk
14211#define LCD_FCR_UDDIE_Pos (3U)
14212#define LCD_FCR_UDDIE_Msk (0x1UL << LCD_FCR_UDDIE_Pos)
14213#define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk
14215#define LCD_FCR_PON_Pos (4U)
14216#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos)
14217#define LCD_FCR_PON LCD_FCR_PON_Msk
14218#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos)
14219#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos)
14220#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos)
14222#define LCD_FCR_DEAD_Pos (7U)
14223#define LCD_FCR_DEAD_Msk (0x7UL << LCD_FCR_DEAD_Pos)
14224#define LCD_FCR_DEAD LCD_FCR_DEAD_Msk
14225#define LCD_FCR_DEAD_0 (0x1UL << LCD_FCR_DEAD_Pos)
14226#define LCD_FCR_DEAD_1 (0x2UL << LCD_FCR_DEAD_Pos)
14227#define LCD_FCR_DEAD_2 (0x4UL << LCD_FCR_DEAD_Pos)
14229#define LCD_FCR_CC_Pos (10U)
14230#define LCD_FCR_CC_Msk (0x7UL << LCD_FCR_CC_Pos)
14231#define LCD_FCR_CC LCD_FCR_CC_Msk
14232#define LCD_FCR_CC_0 (0x1UL << LCD_FCR_CC_Pos)
14233#define LCD_FCR_CC_1 (0x2UL << LCD_FCR_CC_Pos)
14234#define LCD_FCR_CC_2 (0x4UL << LCD_FCR_CC_Pos)
14236#define LCD_FCR_BLINKF_Pos (13U)
14237#define LCD_FCR_BLINKF_Msk (0x7UL << LCD_FCR_BLINKF_Pos)
14238#define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk
14239#define LCD_FCR_BLINKF_0 (0x1UL << LCD_FCR_BLINKF_Pos)
14240#define LCD_FCR_BLINKF_1 (0x2UL << LCD_FCR_BLINKF_Pos)
14241#define LCD_FCR_BLINKF_2 (0x4UL << LCD_FCR_BLINKF_Pos)
14243#define LCD_FCR_BLINK_Pos (16U)
14244#define LCD_FCR_BLINK_Msk (0x3UL << LCD_FCR_BLINK_Pos)
14245#define LCD_FCR_BLINK LCD_FCR_BLINK_Msk
14246#define LCD_FCR_BLINK_0 (0x1UL << LCD_FCR_BLINK_Pos)
14247#define LCD_FCR_BLINK_1 (0x2UL << LCD_FCR_BLINK_Pos)
14249#define LCD_FCR_DIV_Pos (18U)
14250#define LCD_FCR_DIV_Msk (0xFUL << LCD_FCR_DIV_Pos)
14251#define LCD_FCR_DIV LCD_FCR_DIV_Msk
14252#define LCD_FCR_PS_Pos (22U)
14253#define LCD_FCR_PS_Msk (0xFUL << LCD_FCR_PS_Pos)
14254#define LCD_FCR_PS LCD_FCR_PS_Msk
14256/******************* Bit definition for LCD_SR register *********************/
14257#define LCD_SR_ENS_Pos (0U)
14258#define LCD_SR_ENS_Msk (0x1UL << LCD_SR_ENS_Pos)
14259#define LCD_SR_ENS LCD_SR_ENS_Msk
14260#define LCD_SR_SOF_Pos (1U)
14261#define LCD_SR_SOF_Msk (0x1UL << LCD_SR_SOF_Pos)
14262#define LCD_SR_SOF LCD_SR_SOF_Msk
14263#define LCD_SR_UDR_Pos (2U)
14264#define LCD_SR_UDR_Msk (0x1UL << LCD_SR_UDR_Pos)
14265#define LCD_SR_UDR LCD_SR_UDR_Msk
14266#define LCD_SR_UDD_Pos (3U)
14267#define LCD_SR_UDD_Msk (0x1UL << LCD_SR_UDD_Pos)
14268#define LCD_SR_UDD LCD_SR_UDD_Msk
14269#define LCD_SR_RDY_Pos (4U)
14270#define LCD_SR_RDY_Msk (0x1UL << LCD_SR_RDY_Pos)
14271#define LCD_SR_RDY LCD_SR_RDY_Msk
14272#define LCD_SR_FCRSR_Pos (5U)
14273#define LCD_SR_FCRSR_Msk (0x1UL << LCD_SR_FCRSR_Pos)
14274#define LCD_SR_FCRSR LCD_SR_FCRSR_Msk
14276/******************* Bit definition for LCD_CLR register ********************/
14277#define LCD_CLR_SOFC_Pos (1U)
14278#define LCD_CLR_SOFC_Msk (0x1UL << LCD_CLR_SOFC_Pos)
14279#define LCD_CLR_SOFC LCD_CLR_SOFC_Msk
14280#define LCD_CLR_UDDC_Pos (3U)
14281#define LCD_CLR_UDDC_Msk (0x1UL << LCD_CLR_UDDC_Pos)
14282#define LCD_CLR_UDDC LCD_CLR_UDDC_Msk
14284/******************* Bit definition for LCD_RAM register ********************/
14285#define LCD_RAM_SEGMENT_DATA_Pos (0U)
14286#define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)
14287#define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk
14289/******************************************************************************/
14290/* */
14291/* SDMMC Interface */
14292/* */
14293/******************************************************************************/
14294/****************** Bit definition for SDMMC_POWER register ******************/
14295#define SDMMC_POWER_PWRCTRL_Pos (0U)
14296#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos)
14297#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk
14298#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos)
14299#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos)
14301/****************** Bit definition for SDMMC_CLKCR register ******************/
14302#define SDMMC_CLKCR_CLKDIV_Pos (0U)
14303#define SDMMC_CLKCR_CLKDIV_Msk (0xFFUL << SDMMC_CLKCR_CLKDIV_Pos)
14304#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk
14305#define SDMMC_CLKCR_CLKEN_Pos (8U)
14306#define SDMMC_CLKCR_CLKEN_Msk (0x1UL << SDMMC_CLKCR_CLKEN_Pos)
14307#define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk
14308#define SDMMC_CLKCR_PWRSAV_Pos (9U)
14309#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)
14310#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk
14311#define SDMMC_CLKCR_BYPASS_Pos (10U)
14312#define SDMMC_CLKCR_BYPASS_Msk (0x1UL << SDMMC_CLKCR_BYPASS_Pos)
14313#define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk
14315#define SDMMC_CLKCR_WIDBUS_Pos (11U)
14316#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)
14317#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk
14318#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)
14319#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)
14321#define SDMMC_CLKCR_NEGEDGE_Pos (13U)
14322#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)
14323#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk
14324#define SDMMC_CLKCR_HWFC_EN_Pos (14U)
14325#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)
14326#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk
14328/******************* Bit definition for SDMMC_ARG register *******************/
14329#define SDMMC_ARG_CMDARG_Pos (0U)
14330#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)
14331#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk
14333/******************* Bit definition for SDMMC_CMD register *******************/
14334#define SDMMC_CMD_CMDINDEX_Pos (0U)
14335#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)
14336#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk
14338#define SDMMC_CMD_WAITRESP_Pos (6U)
14339#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos)
14340#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk
14341#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos)
14342#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos)
14344#define SDMMC_CMD_WAITINT_Pos (8U)
14345#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos)
14346#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk
14347#define SDMMC_CMD_WAITPEND_Pos (9U)
14348#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos)
14349#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk
14350#define SDMMC_CMD_CPSMEN_Pos (10U)
14351#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos)
14352#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk
14353#define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
14354#define SDMMC_CMD_SDIOSUSPEND_Msk (0x1UL << SDMMC_CMD_SDIOSUSPEND_Pos)
14355#define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk
14357/***************** Bit definition for SDMMC_RESPCMD register *****************/
14358#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
14359#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)
14360#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk
14362/****************** Bit definition for SDMMC_RESP1 register ******************/
14363#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
14364#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)
14365#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk
14367/****************** Bit definition for SDMMC_RESP2 register ******************/
14368#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
14369#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)
14370#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk
14372/****************** Bit definition for SDMMC_RESP3 register ******************/
14373#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
14374#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)
14375#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk
14377/****************** Bit definition for SDMMC_RESP4 register ******************/
14378#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
14379#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)
14380#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk
14382/****************** Bit definition for SDMMC_DTIMER register *****************/
14383#define SDMMC_DTIMER_DATATIME_Pos (0U)
14384#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)
14385#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk
14387/****************** Bit definition for SDMMC_DLEN register *******************/
14388#define SDMMC_DLEN_DATALENGTH_Pos (0U)
14389#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)
14390#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk
14392/****************** Bit definition for SDMMC_DCTRL register ******************/
14393#define SDMMC_DCTRL_DTEN_Pos (0U)
14394#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos)
14395#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk
14396#define SDMMC_DCTRL_DTDIR_Pos (1U)
14397#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos)
14398#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk
14399#define SDMMC_DCTRL_DTMODE_Pos (2U)
14400#define SDMMC_DCTRL_DTMODE_Msk (0x1UL << SDMMC_DCTRL_DTMODE_Pos)
14401#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk
14402#define SDMMC_DCTRL_DMAEN_Pos (3U)
14403#define SDMMC_DCTRL_DMAEN_Msk (0x1UL << SDMMC_DCTRL_DMAEN_Pos)
14404#define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk
14406#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
14407#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
14408#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk
14409#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
14410#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
14411#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
14412#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
14414#define SDMMC_DCTRL_RWSTART_Pos (8U)
14415#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos)
14416#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk
14417#define SDMMC_DCTRL_RWSTOP_Pos (9U)
14418#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)
14419#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk
14420#define SDMMC_DCTRL_RWMOD_Pos (10U)
14421#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos)
14422#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk
14423#define SDMMC_DCTRL_SDIOEN_Pos (11U)
14424#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)
14425#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk
14427/****************** Bit definition for SDMMC_DCOUNT register *****************/
14428#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
14429#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)
14430#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk
14432/****************** Bit definition for SDMMC_STA register ********************/
14433#define SDMMC_STA_CCRCFAIL_Pos (0U)
14434#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos)
14435#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk
14436#define SDMMC_STA_DCRCFAIL_Pos (1U)
14437#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos)
14438#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk
14439#define SDMMC_STA_CTIMEOUT_Pos (2U)
14440#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos)
14441#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk
14442#define SDMMC_STA_DTIMEOUT_Pos (3U)
14443#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos)
14444#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk
14445#define SDMMC_STA_TXUNDERR_Pos (4U)
14446#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos)
14447#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk
14448#define SDMMC_STA_RXOVERR_Pos (5U)
14449#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos)
14450#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk
14451#define SDMMC_STA_CMDREND_Pos (6U)
14452#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos)
14453#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk
14454#define SDMMC_STA_CMDSENT_Pos (7U)
14455#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos)
14456#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk
14457#define SDMMC_STA_DATAEND_Pos (8U)
14458#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos)
14459#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk
14460#define SDMMC_STA_STBITERR_Pos (9U)
14461#define SDMMC_STA_STBITERR_Msk (0x1UL << SDMMC_STA_STBITERR_Pos)
14462#define SDMMC_STA_STBITERR SDMMC_STA_STBITERR_Msk
14463#define SDMMC_STA_DBCKEND_Pos (10U)
14464#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos)
14465#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk
14466#define SDMMC_STA_CMDACT_Pos (11U)
14467#define SDMMC_STA_CMDACT_Msk (0x1UL << SDMMC_STA_CMDACT_Pos)
14468#define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk
14469#define SDMMC_STA_TXACT_Pos (12U)
14470#define SDMMC_STA_TXACT_Msk (0x1UL << SDMMC_STA_TXACT_Pos)
14471#define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk
14472#define SDMMC_STA_RXACT_Pos (13U)
14473#define SDMMC_STA_RXACT_Msk (0x1UL << SDMMC_STA_RXACT_Pos)
14474#define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk
14475#define SDMMC_STA_TXFIFOHE_Pos (14U)
14476#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos)
14477#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk
14478#define SDMMC_STA_RXFIFOHF_Pos (15U)
14479#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos)
14480#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk
14481#define SDMMC_STA_TXFIFOF_Pos (16U)
14482#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos)
14483#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk
14484#define SDMMC_STA_RXFIFOF_Pos (17U)
14485#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos)
14486#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk
14487#define SDMMC_STA_TXFIFOE_Pos (18U)
14488#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos)
14489#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk
14490#define SDMMC_STA_RXFIFOE_Pos (19U)
14491#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos)
14492#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk
14493#define SDMMC_STA_TXDAVL_Pos (20U)
14494#define SDMMC_STA_TXDAVL_Msk (0x1UL << SDMMC_STA_TXDAVL_Pos)
14495#define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk
14496#define SDMMC_STA_RXDAVL_Pos (21U)
14497#define SDMMC_STA_RXDAVL_Msk (0x1UL << SDMMC_STA_RXDAVL_Pos)
14498#define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk
14499#define SDMMC_STA_SDIOIT_Pos (22U)
14500#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos)
14501#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk
14503/******************* Bit definition for SDMMC_ICR register *******************/
14504#define SDMMC_ICR_CCRCFAILC_Pos (0U)
14505#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)
14506#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk
14507#define SDMMC_ICR_DCRCFAILC_Pos (1U)
14508#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)
14509#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk
14510#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
14511#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)
14512#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk
14513#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
14514#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)
14515#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk
14516#define SDMMC_ICR_TXUNDERRC_Pos (4U)
14517#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)
14518#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk
14519#define SDMMC_ICR_RXOVERRC_Pos (5U)
14520#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos)
14521#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk
14522#define SDMMC_ICR_CMDRENDC_Pos (6U)
14523#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos)
14524#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk
14525#define SDMMC_ICR_CMDSENTC_Pos (7U)
14526#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos)
14527#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk
14528#define SDMMC_ICR_DATAENDC_Pos (8U)
14529#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos)
14530#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk
14531#define SDMMC_ICR_STBITERRC_Pos (9U)
14532#define SDMMC_ICR_STBITERRC_Msk (0x1UL << SDMMC_ICR_STBITERRC_Pos)
14533#define SDMMC_ICR_STBITERRC SDMMC_ICR_STBITERRC_Msk
14534#define SDMMC_ICR_DBCKENDC_Pos (10U)
14535#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos)
14536#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk
14537#define SDMMC_ICR_SDIOITC_Pos (22U)
14538#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos)
14539#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk
14541/****************** Bit definition for SDMMC_MASK register *******************/
14542#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
14543#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)
14544#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk
14545#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
14546#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)
14547#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk
14548#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
14549#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)
14550#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk
14551#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
14552#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)
14553#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk
14554#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
14555#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)
14556#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk
14557#define SDMMC_MASK_RXOVERRIE_Pos (5U)
14558#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)
14559#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk
14560#define SDMMC_MASK_CMDRENDIE_Pos (6U)
14561#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)
14562#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk
14563#define SDMMC_MASK_CMDSENTIE_Pos (7U)
14564#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)
14565#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk
14566#define SDMMC_MASK_DATAENDIE_Pos (8U)
14567#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos)
14568#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk
14569#define SDMMC_MASK_DBCKENDIE_Pos (10U)
14570#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)
14571#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk
14572#define SDMMC_MASK_CMDACTIE_Pos (11U)
14573#define SDMMC_MASK_CMDACTIE_Msk (0x1UL << SDMMC_MASK_CMDACTIE_Pos)
14574#define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk
14575#define SDMMC_MASK_TXACTIE_Pos (12U)
14576#define SDMMC_MASK_TXACTIE_Msk (0x1UL << SDMMC_MASK_TXACTIE_Pos)
14577#define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk
14578#define SDMMC_MASK_RXACTIE_Pos (13U)
14579#define SDMMC_MASK_RXACTIE_Msk (0x1UL << SDMMC_MASK_RXACTIE_Pos)
14580#define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk
14581#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
14582#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)
14583#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk
14584#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
14585#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)
14586#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk
14587#define SDMMC_MASK_TXFIFOFIE_Pos (16U)
14588#define SDMMC_MASK_TXFIFOFIE_Msk (0x1UL << SDMMC_MASK_TXFIFOFIE_Pos)
14589#define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk
14590#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
14591#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)
14592#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk
14593#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
14594#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)
14595#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk
14596#define SDMMC_MASK_RXFIFOEIE_Pos (19U)
14597#define SDMMC_MASK_RXFIFOEIE_Msk (0x1UL << SDMMC_MASK_RXFIFOEIE_Pos)
14598#define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk
14599#define SDMMC_MASK_TXDAVLIE_Pos (20U)
14600#define SDMMC_MASK_TXDAVLIE_Msk (0x1UL << SDMMC_MASK_TXDAVLIE_Pos)
14601#define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk
14602#define SDMMC_MASK_RXDAVLIE_Pos (21U)
14603#define SDMMC_MASK_RXDAVLIE_Msk (0x1UL << SDMMC_MASK_RXDAVLIE_Pos)
14604#define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk
14605#define SDMMC_MASK_SDIOITIE_Pos (22U)
14606#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos)
14607#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk
14609/***************** Bit definition for SDMMC_FIFOCNT register *****************/
14610#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
14611#define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDMMC_FIFOCNT_FIFOCOUNT_Pos)
14612#define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk
14614/****************** Bit definition for SDMMC_FIFO register *******************/
14615#define SDMMC_FIFO_FIFODATA_Pos (0U)
14616#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)
14617#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk
14619/******************************************************************************/
14620/* */
14621/* Serial Peripheral Interface (SPI) */
14622/* */
14623/******************************************************************************/
14624/******************* Bit definition for SPI_CR1 register ********************/
14625#define SPI_CR1_CPHA_Pos (0U)
14626#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
14627#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
14628#define SPI_CR1_CPOL_Pos (1U)
14629#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
14630#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
14631#define SPI_CR1_MSTR_Pos (2U)
14632#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
14633#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
14635#define SPI_CR1_BR_Pos (3U)
14636#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
14637#define SPI_CR1_BR SPI_CR1_BR_Msk
14638#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
14639#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
14640#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
14642#define SPI_CR1_SPE_Pos (6U)
14643#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
14644#define SPI_CR1_SPE SPI_CR1_SPE_Msk
14645#define SPI_CR1_LSBFIRST_Pos (7U)
14646#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
14647#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
14648#define SPI_CR1_SSI_Pos (8U)
14649#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
14650#define SPI_CR1_SSI SPI_CR1_SSI_Msk
14651#define SPI_CR1_SSM_Pos (9U)
14652#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
14653#define SPI_CR1_SSM SPI_CR1_SSM_Msk
14654#define SPI_CR1_RXONLY_Pos (10U)
14655#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
14656#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
14657#define SPI_CR1_CRCL_Pos (11U)
14658#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)
14659#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk
14660#define SPI_CR1_CRCNEXT_Pos (12U)
14661#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
14662#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
14663#define SPI_CR1_CRCEN_Pos (13U)
14664#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
14665#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
14666#define SPI_CR1_BIDIOE_Pos (14U)
14667#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
14668#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
14669#define SPI_CR1_BIDIMODE_Pos (15U)
14670#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
14671#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
14673/******************* Bit definition for SPI_CR2 register ********************/
14674#define SPI_CR2_RXDMAEN_Pos (0U)
14675#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
14676#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
14677#define SPI_CR2_TXDMAEN_Pos (1U)
14678#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
14679#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
14680#define SPI_CR2_SSOE_Pos (2U)
14681#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
14682#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
14683#define SPI_CR2_NSSP_Pos (3U)
14684#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)
14685#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk
14686#define SPI_CR2_FRF_Pos (4U)
14687#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
14688#define SPI_CR2_FRF SPI_CR2_FRF_Msk
14689#define SPI_CR2_ERRIE_Pos (5U)
14690#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
14691#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
14692#define SPI_CR2_RXNEIE_Pos (6U)
14693#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
14694#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
14695#define SPI_CR2_TXEIE_Pos (7U)
14696#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
14697#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
14698#define SPI_CR2_DS_Pos (8U)
14699#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)
14700#define SPI_CR2_DS SPI_CR2_DS_Msk
14701#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)
14702#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)
14703#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)
14704#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)
14705#define SPI_CR2_FRXTH_Pos (12U)
14706#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)
14707#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk
14708#define SPI_CR2_LDMARX_Pos (13U)
14709#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)
14710#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk
14711#define SPI_CR2_LDMATX_Pos (14U)
14712#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)
14713#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk
14715/******************** Bit definition for SPI_SR register ********************/
14716#define SPI_SR_RXNE_Pos (0U)
14717#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
14718#define SPI_SR_RXNE SPI_SR_RXNE_Msk
14719#define SPI_SR_TXE_Pos (1U)
14720#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
14721#define SPI_SR_TXE SPI_SR_TXE_Msk
14722#define SPI_SR_CHSIDE_Pos (2U)
14723#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
14724#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
14725#define SPI_SR_UDR_Pos (3U)
14726#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
14727#define SPI_SR_UDR SPI_SR_UDR_Msk
14728#define SPI_SR_CRCERR_Pos (4U)
14729#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
14730#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
14731#define SPI_SR_MODF_Pos (5U)
14732#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
14733#define SPI_SR_MODF SPI_SR_MODF_Msk
14734#define SPI_SR_OVR_Pos (6U)
14735#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
14736#define SPI_SR_OVR SPI_SR_OVR_Msk
14737#define SPI_SR_BSY_Pos (7U)
14738#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
14739#define SPI_SR_BSY SPI_SR_BSY_Msk
14740#define SPI_SR_FRE_Pos (8U)
14741#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
14742#define SPI_SR_FRE SPI_SR_FRE_Msk
14743#define SPI_SR_FRLVL_Pos (9U)
14744#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)
14745#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk
14746#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)
14747#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)
14748#define SPI_SR_FTLVL_Pos (11U)
14749#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)
14750#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk
14751#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)
14752#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)
14754/******************** Bit definition for SPI_DR register ********************/
14755#define SPI_DR_DR_Pos (0U)
14756#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
14757#define SPI_DR_DR SPI_DR_DR_Msk
14759/******************* Bit definition for SPI_CRCPR register ******************/
14760#define SPI_CRCPR_CRCPOLY_Pos (0U)
14761#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
14762#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
14764/****************** Bit definition for SPI_RXCRCR register ******************/
14765#define SPI_RXCRCR_RXCRC_Pos (0U)
14766#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
14767#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
14769/****************** Bit definition for SPI_TXCRCR register ******************/
14770#define SPI_TXCRCR_TXCRC_Pos (0U)
14771#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
14772#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
14774/******************************************************************************/
14775/* */
14776/* QUADSPI */
14777/* */
14778/******************************************************************************/
14779/***************** Bit definition for QUADSPI_CR register *******************/
14780#define QUADSPI_CR_EN_Pos (0U)
14781#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
14782#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
14783#define QUADSPI_CR_ABORT_Pos (1U)
14784#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
14785#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
14786#define QUADSPI_CR_DMAEN_Pos (2U)
14787#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
14788#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
14789#define QUADSPI_CR_TCEN_Pos (3U)
14790#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
14791#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
14792#define QUADSPI_CR_SSHIFT_Pos (4U)
14793#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
14794#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
14795#define QUADSPI_CR_DFM_Pos (6U)
14796#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos)
14797#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
14798#define QUADSPI_CR_FSEL_Pos (7U)
14799#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos)
14800#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
14801#define QUADSPI_CR_FTHRES_Pos (8U)
14802#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos)
14803#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
14804#define QUADSPI_CR_TEIE_Pos (16U)
14805#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
14806#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
14807#define QUADSPI_CR_TCIE_Pos (17U)
14808#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
14809#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
14810#define QUADSPI_CR_FTIE_Pos (18U)
14811#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
14812#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
14813#define QUADSPI_CR_SMIE_Pos (19U)
14814#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
14815#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
14816#define QUADSPI_CR_TOIE_Pos (20U)
14817#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
14818#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
14819#define QUADSPI_CR_APMS_Pos (22U)
14820#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
14821#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
14822#define QUADSPI_CR_PMM_Pos (23U)
14823#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
14824#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
14825#define QUADSPI_CR_PRESCALER_Pos (24U)
14826#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
14827#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
14829/***************** Bit definition for QUADSPI_DCR register ******************/
14830#define QUADSPI_DCR_CKMODE_Pos (0U)
14831#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
14832#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
14833#define QUADSPI_DCR_CSHT_Pos (8U)
14834#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
14835#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
14836#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
14837#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
14838#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
14839#define QUADSPI_DCR_FSIZE_Pos (16U)
14840#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
14841#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
14843/****************** Bit definition for QUADSPI_SR register *******************/
14844#define QUADSPI_SR_TEF_Pos (0U)
14845#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
14846#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
14847#define QUADSPI_SR_TCF_Pos (1U)
14848#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
14849#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
14850#define QUADSPI_SR_FTF_Pos (2U)
14851#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
14852#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
14853#define QUADSPI_SR_SMF_Pos (3U)
14854#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
14855#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
14856#define QUADSPI_SR_TOF_Pos (4U)
14857#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
14858#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
14859#define QUADSPI_SR_BUSY_Pos (5U)
14860#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
14861#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
14862#define QUADSPI_SR_FLEVEL_Pos (8U)
14863#define QUADSPI_SR_FLEVEL_Msk (0x1FUL << QUADSPI_SR_FLEVEL_Pos)
14864#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
14866/****************** Bit definition for QUADSPI_FCR register ******************/
14867#define QUADSPI_FCR_CTEF_Pos (0U)
14868#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
14869#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
14870#define QUADSPI_FCR_CTCF_Pos (1U)
14871#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
14872#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
14873#define QUADSPI_FCR_CSMF_Pos (3U)
14874#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
14875#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
14876#define QUADSPI_FCR_CTOF_Pos (4U)
14877#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
14878#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
14880/****************** Bit definition for QUADSPI_DLR register ******************/
14881#define QUADSPI_DLR_DL_Pos (0U)
14882#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
14883#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
14885/****************** Bit definition for QUADSPI_CCR register ******************/
14886#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
14887#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
14888#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
14889#define QUADSPI_CCR_IMODE_Pos (8U)
14890#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
14891#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
14892#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
14893#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
14894#define QUADSPI_CCR_ADMODE_Pos (10U)
14895#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
14896#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
14897#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
14898#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
14899#define QUADSPI_CCR_ADSIZE_Pos (12U)
14900#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
14901#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
14902#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
14903#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
14904#define QUADSPI_CCR_ABMODE_Pos (14U)
14905#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
14906#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
14907#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
14908#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
14909#define QUADSPI_CCR_ABSIZE_Pos (16U)
14910#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
14911#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
14912#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
14913#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
14914#define QUADSPI_CCR_DCYC_Pos (18U)
14915#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
14916#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
14917#define QUADSPI_CCR_DMODE_Pos (24U)
14918#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
14919#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
14920#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
14921#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
14922#define QUADSPI_CCR_FMODE_Pos (26U)
14923#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
14924#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
14925#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
14926#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
14927#define QUADSPI_CCR_SIOO_Pos (28U)
14928#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
14929#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
14930#define QUADSPI_CCR_DHHC_Pos (30U)
14931#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos)
14932#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
14933#define QUADSPI_CCR_DDRM_Pos (31U)
14934#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
14935#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
14937/****************** Bit definition for QUADSPI_AR register *******************/
14938#define QUADSPI_AR_ADDRESS_Pos (0U)
14939#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
14940#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
14942/****************** Bit definition for QUADSPI_ABR register ******************/
14943#define QUADSPI_ABR_ALTERNATE_Pos (0U)
14944#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
14945#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
14947/****************** Bit definition for QUADSPI_DR register *******************/
14948#define QUADSPI_DR_DATA_Pos (0U)
14949#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
14950#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
14952/****************** Bit definition for QUADSPI_PSMKR register ****************/
14953#define QUADSPI_PSMKR_MASK_Pos (0U)
14954#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
14955#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
14957/****************** Bit definition for QUADSPI_PSMAR register ****************/
14958#define QUADSPI_PSMAR_MATCH_Pos (0U)
14959#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
14960#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
14962/****************** Bit definition for QUADSPI_PIR register *****************/
14963#define QUADSPI_PIR_INTERVAL_Pos (0U)
14964#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
14965#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
14967/****************** Bit definition for QUADSPI_LPTR register *****************/
14968#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
14969#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
14970#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
14972/******************************************************************************/
14973/* */
14974/* SYSCFG */
14975/* */
14976/******************************************************************************/
14977/****************** Bit definition for SYSCFG_MEMRMP register ***************/
14978#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
14979#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
14980#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
14981#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
14982#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
14983#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
14985#define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
14986#define SYSCFG_MEMRMP_FB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos)
14987#define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk
14989/****************** Bit definition for SYSCFG_CFGR1 register ******************/
14990#define SYSCFG_CFGR1_FWDIS_Pos (0U)
14991#define SYSCFG_CFGR1_FWDIS_Msk (0x1UL << SYSCFG_CFGR1_FWDIS_Pos)
14992#define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk
14993#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
14994#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)
14995#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk
14996#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
14997#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)
14998#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk
14999#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
15000#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)
15001#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk
15002#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
15003#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)
15004#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk
15005#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
15006#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)
15007#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk
15008#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
15009#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)
15010#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk
15011#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
15012#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)
15013#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk
15014#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
15015#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)
15016#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk
15017#define SYSCFG_CFGR1_I2C4_FMP_Pos (23U)
15018#define SYSCFG_CFGR1_I2C4_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C4_FMP_Pos)
15019#define SYSCFG_CFGR1_I2C4_FMP SYSCFG_CFGR1_I2C4_FMP_Msk
15020#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000UL)
15021#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000UL)
15022#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000UL)
15023#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000UL)
15024#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000UL)
15025#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000UL)
15027/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
15028#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
15029#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
15030#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
15031#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
15032#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
15033#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
15034#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
15035#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
15036#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
15037#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
15038#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
15039#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
15044#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000UL)
15045#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001UL)
15046#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002UL)
15047#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003UL)
15048#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004UL)
15049#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005UL)
15050#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006UL)
15051#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007UL)
15052#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008UL)
15057#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000UL)
15058#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010UL)
15059#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020UL)
15060#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030UL)
15061#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040UL)
15062#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050UL)
15063#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060UL)
15064#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070UL)
15065#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080UL)
15070#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000UL)
15071#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100UL)
15072#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200UL)
15073#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300UL)
15074#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400UL)
15075#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500UL)
15076#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600UL)
15077#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700UL)
15078#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800UL)
15083#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000UL)
15084#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000UL)
15085#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000UL)
15086#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000UL)
15087#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000UL)
15088#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000UL)
15089#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000UL)
15090#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000UL)
15091#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000UL)
15093/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
15094#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
15095#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
15096#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
15097#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
15098#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
15099#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
15100#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
15101#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
15102#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
15103#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
15104#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
15105#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
15109#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000UL)
15110#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001UL)
15111#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002UL)
15112#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003UL)
15113#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004UL)
15114#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005UL)
15115#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006UL)
15116#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007UL)
15117#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008UL)
15122#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000UL)
15123#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010UL)
15124#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020UL)
15125#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030UL)
15126#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040UL)
15127#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050UL)
15128#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060UL)
15129#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070UL)
15130#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080UL)
15135#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000UL)
15136#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100UL)
15137#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200UL)
15138#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300UL)
15139#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400UL)
15140#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500UL)
15141#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600UL)
15142#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700UL)
15143#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800UL)
15148#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000UL)
15149#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000UL)
15150#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000UL)
15151#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000UL)
15152#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000UL)
15153#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000UL)
15154#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000UL)
15155#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000UL)
15156#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000UL)
15158/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
15159#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
15160#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
15161#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
15162#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
15163#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
15164#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
15165#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
15166#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
15167#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
15168#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
15169#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
15170#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
15175#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000UL)
15176#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001UL)
15177#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002UL)
15178#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003UL)
15179#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004UL)
15180#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005UL)
15181#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006UL)
15182#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007UL)
15183#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008UL)
15188#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000UL)
15189#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010UL)
15190#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020UL)
15191#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030UL)
15192#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040UL)
15193#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050UL)
15194#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060UL)
15195#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070UL)
15196#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080UL)
15201#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000UL)
15202#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100UL)
15203#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200UL)
15204#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300UL)
15205#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400UL)
15206#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500UL)
15207#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600UL)
15208#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700UL)
15209#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800UL)
15214#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000UL)
15215#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000UL)
15216#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000UL)
15217#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000UL)
15218#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000UL)
15219#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000UL)
15220#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000UL)
15221#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000UL)
15222#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000UL)
15224/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
15225#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
15226#define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)
15227#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
15228#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
15229#define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)
15230#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
15231#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
15232#define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)
15233#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
15234#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
15235#define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)
15236#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
15241#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000UL)
15242#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001UL)
15243#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002UL)
15244#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003UL)
15245#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004UL)
15246#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005UL)
15247#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006UL)
15248#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007UL)
15253#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000UL)
15254#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010UL)
15255#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020UL)
15256#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030UL)
15257#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040UL)
15258#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050UL)
15259#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060UL)
15260#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070UL)
15265#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000UL)
15266#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100UL)
15267#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200UL)
15268#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300UL)
15269#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400UL)
15270#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500UL)
15271#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600UL)
15272#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700UL)
15277#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000UL)
15278#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000UL)
15279#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000UL)
15280#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000UL)
15281#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000UL)
15282#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000UL)
15283#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000UL)
15284#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000UL)
15286/****************** Bit definition for SYSCFG_SCSR register ****************/
15287#define SYSCFG_SCSR_SRAM2ER_Pos (0U)
15288#define SYSCFG_SCSR_SRAM2ER_Msk (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)
15289#define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk
15290#define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
15291#define SYSCFG_SCSR_SRAM2BSY_Msk (0x1UL << SYSCFG_SCSR_SRAM2BSY_Pos)
15292#define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk
15294/****************** Bit definition for SYSCFG_CFGR2 register ****************/
15295#define SYSCFG_CFGR2_CLL_Pos (0U)
15296#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos)
15297#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk
15298#define SYSCFG_CFGR2_SPL_Pos (1U)
15299#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos)
15300#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk
15301#define SYSCFG_CFGR2_PVDL_Pos (2U)
15302#define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos)
15303#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk
15304#define SYSCFG_CFGR2_ECCL_Pos (3U)
15305#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos)
15306#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk
15307#define SYSCFG_CFGR2_SPF_Pos (8U)
15308#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos)
15309#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk
15311/****************** Bit definition for SYSCFG_SWPR register ****************/
15312#define SYSCFG_SWPR_PAGE0_Pos (0U)
15313#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos)
15314#define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk
15315#define SYSCFG_SWPR_PAGE1_Pos (1U)
15316#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos)
15317#define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk
15318#define SYSCFG_SWPR_PAGE2_Pos (2U)
15319#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos)
15320#define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk
15321#define SYSCFG_SWPR_PAGE3_Pos (3U)
15322#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos)
15323#define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk
15324#define SYSCFG_SWPR_PAGE4_Pos (4U)
15325#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos)
15326#define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk
15327#define SYSCFG_SWPR_PAGE5_Pos (5U)
15328#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos)
15329#define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk
15330#define SYSCFG_SWPR_PAGE6_Pos (6U)
15331#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos)
15332#define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk
15333#define SYSCFG_SWPR_PAGE7_Pos (7U)
15334#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos)
15335#define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk
15336#define SYSCFG_SWPR_PAGE8_Pos (8U)
15337#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos)
15338#define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk
15339#define SYSCFG_SWPR_PAGE9_Pos (9U)
15340#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos)
15341#define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk
15342#define SYSCFG_SWPR_PAGE10_Pos (10U)
15343#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos)
15344#define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk
15345#define SYSCFG_SWPR_PAGE11_Pos (11U)
15346#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos)
15347#define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk
15348#define SYSCFG_SWPR_PAGE12_Pos (12U)
15349#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos)
15350#define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk
15351#define SYSCFG_SWPR_PAGE13_Pos (13U)
15352#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos)
15353#define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk
15354#define SYSCFG_SWPR_PAGE14_Pos (14U)
15355#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos)
15356#define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk
15357#define SYSCFG_SWPR_PAGE15_Pos (15U)
15358#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos)
15359#define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk
15360#define SYSCFG_SWPR_PAGE16_Pos (16U)
15361#define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos)
15362#define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk
15363#define SYSCFG_SWPR_PAGE17_Pos (17U)
15364#define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos)
15365#define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk
15366#define SYSCFG_SWPR_PAGE18_Pos (18U)
15367#define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos)
15368#define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk
15369#define SYSCFG_SWPR_PAGE19_Pos (19U)
15370#define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos)
15371#define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk
15372#define SYSCFG_SWPR_PAGE20_Pos (20U)
15373#define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos)
15374#define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk
15375#define SYSCFG_SWPR_PAGE21_Pos (21U)
15376#define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos)
15377#define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk
15378#define SYSCFG_SWPR_PAGE22_Pos (22U)
15379#define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos)
15380#define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk
15381#define SYSCFG_SWPR_PAGE23_Pos (23U)
15382#define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos)
15383#define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk
15384#define SYSCFG_SWPR_PAGE24_Pos (24U)
15385#define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos)
15386#define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk
15387#define SYSCFG_SWPR_PAGE25_Pos (25U)
15388#define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos)
15389#define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk
15390#define SYSCFG_SWPR_PAGE26_Pos (26U)
15391#define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos)
15392#define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk
15393#define SYSCFG_SWPR_PAGE27_Pos (27U)
15394#define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos)
15395#define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk
15396#define SYSCFG_SWPR_PAGE28_Pos (28U)
15397#define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos)
15398#define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk
15399#define SYSCFG_SWPR_PAGE29_Pos (29U)
15400#define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos)
15401#define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk
15402#define SYSCFG_SWPR_PAGE30_Pos (30U)
15403#define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos)
15404#define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk
15405#define SYSCFG_SWPR_PAGE31_Pos (31U)
15406#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos)
15407#define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk
15409/****************** Bit definition for SYSCFG_SWPR2 register ***************/
15410#define SYSCFG_SWPR2_PAGE32_Pos (0U)
15411#define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos)
15412#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk
15413#define SYSCFG_SWPR2_PAGE33_Pos (1U)
15414#define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos)
15415#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk
15416#define SYSCFG_SWPR2_PAGE34_Pos (2U)
15417#define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos)
15418#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk
15419#define SYSCFG_SWPR2_PAGE35_Pos (3U)
15420#define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos)
15421#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk
15422#define SYSCFG_SWPR2_PAGE36_Pos (4U)
15423#define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos)
15424#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk
15425#define SYSCFG_SWPR2_PAGE37_Pos (5U)
15426#define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos)
15427#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk
15428#define SYSCFG_SWPR2_PAGE38_Pos (6U)
15429#define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos)
15430#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk
15431#define SYSCFG_SWPR2_PAGE39_Pos (7U)
15432#define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos)
15433#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk
15434#define SYSCFG_SWPR2_PAGE40_Pos (8U)
15435#define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos)
15436#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk
15437#define SYSCFG_SWPR2_PAGE41_Pos (9U)
15438#define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos)
15439#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk
15440#define SYSCFG_SWPR2_PAGE42_Pos (10U)
15441#define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos)
15442#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk
15443#define SYSCFG_SWPR2_PAGE43_Pos (11U)
15444#define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos)
15445#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk
15446#define SYSCFG_SWPR2_PAGE44_Pos (12U)
15447#define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos)
15448#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk
15449#define SYSCFG_SWPR2_PAGE45_Pos (13U)
15450#define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos)
15451#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk
15452#define SYSCFG_SWPR2_PAGE46_Pos (14U)
15453#define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos)
15454#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk
15455#define SYSCFG_SWPR2_PAGE47_Pos (15U)
15456#define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos)
15457#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk
15458#define SYSCFG_SWPR2_PAGE48_Pos (16U)
15459#define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos)
15460#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk
15461#define SYSCFG_SWPR2_PAGE49_Pos (17U)
15462#define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos)
15463#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk
15464#define SYSCFG_SWPR2_PAGE50_Pos (18U)
15465#define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos)
15466#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk
15467#define SYSCFG_SWPR2_PAGE51_Pos (19U)
15468#define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos)
15469#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk
15470#define SYSCFG_SWPR2_PAGE52_Pos (20U)
15471#define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos)
15472#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk
15473#define SYSCFG_SWPR2_PAGE53_Pos (21U)
15474#define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos)
15475#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk
15476#define SYSCFG_SWPR2_PAGE54_Pos (22U)
15477#define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos)
15478#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk
15479#define SYSCFG_SWPR2_PAGE55_Pos (23U)
15480#define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos)
15481#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk
15482#define SYSCFG_SWPR2_PAGE56_Pos (24U)
15483#define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos)
15484#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk
15485#define SYSCFG_SWPR2_PAGE57_Pos (25U)
15486#define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos)
15487#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk
15488#define SYSCFG_SWPR2_PAGE58_Pos (26U)
15489#define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos)
15490#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk
15491#define SYSCFG_SWPR2_PAGE59_Pos (27U)
15492#define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos)
15493#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk
15494#define SYSCFG_SWPR2_PAGE60_Pos (28U)
15495#define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos)
15496#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk
15497#define SYSCFG_SWPR2_PAGE61_Pos (29U)
15498#define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos)
15499#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk
15500#define SYSCFG_SWPR2_PAGE62_Pos (30U)
15501#define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos)
15502#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk
15503#define SYSCFG_SWPR2_PAGE63_Pos (31U)
15504#define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos)
15505#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk
15507/****************** Bit definition for SYSCFG_SKR register ****************/
15508#define SYSCFG_SKR_KEY_Pos (0U)
15509#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos)
15510#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk
15515/******************************************************************************/
15516/* */
15517/* TIM */
15518/* */
15519/******************************************************************************/
15520/******************* Bit definition for TIM_CR1 register ********************/
15521#define TIM_CR1_CEN_Pos (0U)
15522#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
15523#define TIM_CR1_CEN TIM_CR1_CEN_Msk
15524#define TIM_CR1_UDIS_Pos (1U)
15525#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
15526#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
15527#define TIM_CR1_URS_Pos (2U)
15528#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
15529#define TIM_CR1_URS TIM_CR1_URS_Msk
15530#define TIM_CR1_OPM_Pos (3U)
15531#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
15532#define TIM_CR1_OPM TIM_CR1_OPM_Msk
15533#define TIM_CR1_DIR_Pos (4U)
15534#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
15535#define TIM_CR1_DIR TIM_CR1_DIR_Msk
15537#define TIM_CR1_CMS_Pos (5U)
15538#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
15539#define TIM_CR1_CMS TIM_CR1_CMS_Msk
15540#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
15541#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
15543#define TIM_CR1_ARPE_Pos (7U)
15544#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
15545#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
15547#define TIM_CR1_CKD_Pos (8U)
15548#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
15549#define TIM_CR1_CKD TIM_CR1_CKD_Msk
15550#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
15551#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
15553#define TIM_CR1_UIFREMAP_Pos (11U)
15554#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)
15555#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk
15557/******************* Bit definition for TIM_CR2 register ********************/
15558#define TIM_CR2_CCPC_Pos (0U)
15559#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
15560#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
15561#define TIM_CR2_CCUS_Pos (2U)
15562#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
15563#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
15564#define TIM_CR2_CCDS_Pos (3U)
15565#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
15566#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
15568#define TIM_CR2_MMS_Pos (4U)
15569#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
15570#define TIM_CR2_MMS TIM_CR2_MMS_Msk
15571#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
15572#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
15573#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
15575#define TIM_CR2_TI1S_Pos (7U)
15576#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
15577#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
15578#define TIM_CR2_OIS1_Pos (8U)
15579#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
15580#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
15581#define TIM_CR2_OIS1N_Pos (9U)
15582#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
15583#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
15584#define TIM_CR2_OIS2_Pos (10U)
15585#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
15586#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
15587#define TIM_CR2_OIS2N_Pos (11U)
15588#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
15589#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
15590#define TIM_CR2_OIS3_Pos (12U)
15591#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
15592#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
15593#define TIM_CR2_OIS3N_Pos (13U)
15594#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
15595#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
15596#define TIM_CR2_OIS4_Pos (14U)
15597#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
15598#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
15599#define TIM_CR2_OIS5_Pos (16U)
15600#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)
15601#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk
15602#define TIM_CR2_OIS6_Pos (18U)
15603#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)
15604#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk
15606#define TIM_CR2_MMS2_Pos (20U)
15607#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)
15608#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk
15609#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)
15610#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)
15611#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)
15612#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)
15614/******************* Bit definition for TIM_SMCR register *******************/
15615#define TIM_SMCR_SMS_Pos (0U)
15616#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)
15617#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
15618#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)
15619#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)
15620#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)
15621#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)
15623#define TIM_SMCR_OCCS_Pos (3U)
15624#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos)
15625#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk
15627#define TIM_SMCR_TS_Pos (4U)
15628#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
15629#define TIM_SMCR_TS TIM_SMCR_TS_Msk
15630#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
15631#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
15632#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
15634#define TIM_SMCR_MSM_Pos (7U)
15635#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
15636#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
15638#define TIM_SMCR_ETF_Pos (8U)
15639#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
15640#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
15641#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
15642#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
15643#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
15644#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
15646#define TIM_SMCR_ETPS_Pos (12U)
15647#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
15648#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
15649#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
15650#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
15652#define TIM_SMCR_ECE_Pos (14U)
15653#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
15654#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
15655#define TIM_SMCR_ETP_Pos (15U)
15656#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
15657#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
15659/******************* Bit definition for TIM_DIER register *******************/
15660#define TIM_DIER_UIE_Pos (0U)
15661#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
15662#define TIM_DIER_UIE TIM_DIER_UIE_Msk
15663#define TIM_DIER_CC1IE_Pos (1U)
15664#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
15665#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
15666#define TIM_DIER_CC2IE_Pos (2U)
15667#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
15668#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
15669#define TIM_DIER_CC3IE_Pos (3U)
15670#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
15671#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
15672#define TIM_DIER_CC4IE_Pos (4U)
15673#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
15674#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
15675#define TIM_DIER_COMIE_Pos (5U)
15676#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
15677#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
15678#define TIM_DIER_TIE_Pos (6U)
15679#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
15680#define TIM_DIER_TIE TIM_DIER_TIE_Msk
15681#define TIM_DIER_BIE_Pos (7U)
15682#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
15683#define TIM_DIER_BIE TIM_DIER_BIE_Msk
15684#define TIM_DIER_UDE_Pos (8U)
15685#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
15686#define TIM_DIER_UDE TIM_DIER_UDE_Msk
15687#define TIM_DIER_CC1DE_Pos (9U)
15688#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
15689#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
15690#define TIM_DIER_CC2DE_Pos (10U)
15691#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
15692#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
15693#define TIM_DIER_CC3DE_Pos (11U)
15694#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
15695#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
15696#define TIM_DIER_CC4DE_Pos (12U)
15697#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
15698#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
15699#define TIM_DIER_COMDE_Pos (13U)
15700#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
15701#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
15702#define TIM_DIER_TDE_Pos (14U)
15703#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
15704#define TIM_DIER_TDE TIM_DIER_TDE_Msk
15706/******************** Bit definition for TIM_SR register ********************/
15707#define TIM_SR_UIF_Pos (0U)
15708#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
15709#define TIM_SR_UIF TIM_SR_UIF_Msk
15710#define TIM_SR_CC1IF_Pos (1U)
15711#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
15712#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
15713#define TIM_SR_CC2IF_Pos (2U)
15714#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
15715#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
15716#define TIM_SR_CC3IF_Pos (3U)
15717#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
15718#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
15719#define TIM_SR_CC4IF_Pos (4U)
15720#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
15721#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
15722#define TIM_SR_COMIF_Pos (5U)
15723#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
15724#define TIM_SR_COMIF TIM_SR_COMIF_Msk
15725#define TIM_SR_TIF_Pos (6U)
15726#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
15727#define TIM_SR_TIF TIM_SR_TIF_Msk
15728#define TIM_SR_BIF_Pos (7U)
15729#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
15730#define TIM_SR_BIF TIM_SR_BIF_Msk
15731#define TIM_SR_B2IF_Pos (8U)
15732#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)
15733#define TIM_SR_B2IF TIM_SR_B2IF_Msk
15734#define TIM_SR_CC1OF_Pos (9U)
15735#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
15736#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
15737#define TIM_SR_CC2OF_Pos (10U)
15738#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
15739#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
15740#define TIM_SR_CC3OF_Pos (11U)
15741#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
15742#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
15743#define TIM_SR_CC4OF_Pos (12U)
15744#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
15745#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
15746#define TIM_SR_SBIF_Pos (13U)
15747#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)
15748#define TIM_SR_SBIF TIM_SR_SBIF_Msk
15749#define TIM_SR_CC5IF_Pos (16U)
15750#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)
15751#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk
15752#define TIM_SR_CC6IF_Pos (17U)
15753#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)
15754#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk
15757/******************* Bit definition for TIM_EGR register ********************/
15758#define TIM_EGR_UG_Pos (0U)
15759#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
15760#define TIM_EGR_UG TIM_EGR_UG_Msk
15761#define TIM_EGR_CC1G_Pos (1U)
15762#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
15763#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
15764#define TIM_EGR_CC2G_Pos (2U)
15765#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
15766#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
15767#define TIM_EGR_CC3G_Pos (3U)
15768#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
15769#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
15770#define TIM_EGR_CC4G_Pos (4U)
15771#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
15772#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
15773#define TIM_EGR_COMG_Pos (5U)
15774#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
15775#define TIM_EGR_COMG TIM_EGR_COMG_Msk
15776#define TIM_EGR_TG_Pos (6U)
15777#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
15778#define TIM_EGR_TG TIM_EGR_TG_Msk
15779#define TIM_EGR_BG_Pos (7U)
15780#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
15781#define TIM_EGR_BG TIM_EGR_BG_Msk
15782#define TIM_EGR_B2G_Pos (8U)
15783#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)
15784#define TIM_EGR_B2G TIM_EGR_B2G_Msk
15787/****************** Bit definition for TIM_CCMR1 register *******************/
15788#define TIM_CCMR1_CC1S_Pos (0U)
15789#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
15790#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
15791#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
15792#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
15794#define TIM_CCMR1_OC1FE_Pos (2U)
15795#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
15796#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
15797#define TIM_CCMR1_OC1PE_Pos (3U)
15798#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
15799#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
15801#define TIM_CCMR1_OC1M_Pos (4U)
15802#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)
15803#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
15804#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)
15805#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)
15806#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)
15807#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)
15809#define TIM_CCMR1_OC1CE_Pos (7U)
15810#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
15811#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
15813#define TIM_CCMR1_CC2S_Pos (8U)
15814#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
15815#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
15816#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
15817#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
15819#define TIM_CCMR1_OC2FE_Pos (10U)
15820#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
15821#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
15822#define TIM_CCMR1_OC2PE_Pos (11U)
15823#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
15824#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
15826#define TIM_CCMR1_OC2M_Pos (12U)
15827#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)
15828#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
15829#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)
15830#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)
15831#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)
15832#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)
15834#define TIM_CCMR1_OC2CE_Pos (15U)
15835#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
15836#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
15838/*----------------------------------------------------------------------------*/
15839#define TIM_CCMR1_IC1PSC_Pos (2U)
15840#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
15841#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
15842#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
15843#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
15845#define TIM_CCMR1_IC1F_Pos (4U)
15846#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
15847#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
15848#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
15849#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
15850#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
15851#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
15853#define TIM_CCMR1_IC2PSC_Pos (10U)
15854#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
15855#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
15856#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
15857#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
15859#define TIM_CCMR1_IC2F_Pos (12U)
15860#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
15861#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
15862#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
15863#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
15864#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
15865#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
15867/****************** Bit definition for TIM_CCMR2 register *******************/
15868#define TIM_CCMR2_CC3S_Pos (0U)
15869#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
15870#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
15871#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
15872#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
15874#define TIM_CCMR2_OC3FE_Pos (2U)
15875#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
15876#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
15877#define TIM_CCMR2_OC3PE_Pos (3U)
15878#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
15879#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
15881#define TIM_CCMR2_OC3M_Pos (4U)
15882#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)
15883#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
15884#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos)
15885#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos)
15886#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos)
15887#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)
15889#define TIM_CCMR2_OC3CE_Pos (7U)
15890#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
15891#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
15893#define TIM_CCMR2_CC4S_Pos (8U)
15894#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
15895#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
15896#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
15897#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
15899#define TIM_CCMR2_OC4FE_Pos (10U)
15900#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
15901#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
15902#define TIM_CCMR2_OC4PE_Pos (11U)
15903#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
15904#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
15906#define TIM_CCMR2_OC4M_Pos (12U)
15907#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)
15908#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
15909#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos)
15910#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos)
15911#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos)
15912#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)
15914#define TIM_CCMR2_OC4CE_Pos (15U)
15915#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
15916#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
15918/*----------------------------------------------------------------------------*/
15919#define TIM_CCMR2_IC3PSC_Pos (2U)
15920#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
15921#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
15922#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
15923#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
15925#define TIM_CCMR2_IC3F_Pos (4U)
15926#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
15927#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
15928#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
15929#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
15930#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
15931#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
15933#define TIM_CCMR2_IC4PSC_Pos (10U)
15934#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
15935#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
15936#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
15937#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
15939#define TIM_CCMR2_IC4F_Pos (12U)
15940#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
15941#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
15942#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
15943#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
15944#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
15945#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
15947/****************** Bit definition for TIM_CCMR3 register *******************/
15948#define TIM_CCMR3_OC5FE_Pos (2U)
15949#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)
15950#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk
15951#define TIM_CCMR3_OC5PE_Pos (3U)
15952#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)
15953#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk
15955#define TIM_CCMR3_OC5M_Pos (4U)
15956#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)
15957#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk
15958#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)
15959#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)
15960#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)
15961#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)
15963#define TIM_CCMR3_OC5CE_Pos (7U)
15964#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)
15965#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk
15967#define TIM_CCMR3_OC6FE_Pos (10U)
15968#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)
15969#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk
15970#define TIM_CCMR3_OC6PE_Pos (11U)
15971#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)
15972#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk
15974#define TIM_CCMR3_OC6M_Pos (12U)
15975#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)
15976#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk
15977#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)
15978#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)
15979#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)
15980#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)
15982#define TIM_CCMR3_OC6CE_Pos (15U)
15983#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)
15984#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk
15986/******************* Bit definition for TIM_CCER register *******************/
15987#define TIM_CCER_CC1E_Pos (0U)
15988#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
15989#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
15990#define TIM_CCER_CC1P_Pos (1U)
15991#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
15992#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
15993#define TIM_CCER_CC1NE_Pos (2U)
15994#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
15995#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
15996#define TIM_CCER_CC1NP_Pos (3U)
15997#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
15998#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
15999#define TIM_CCER_CC2E_Pos (4U)
16000#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
16001#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
16002#define TIM_CCER_CC2P_Pos (5U)
16003#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
16004#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
16005#define TIM_CCER_CC2NE_Pos (6U)
16006#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
16007#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
16008#define TIM_CCER_CC2NP_Pos (7U)
16009#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
16010#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
16011#define TIM_CCER_CC3E_Pos (8U)
16012#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
16013#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
16014#define TIM_CCER_CC3P_Pos (9U)
16015#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
16016#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
16017#define TIM_CCER_CC3NE_Pos (10U)
16018#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
16019#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
16020#define TIM_CCER_CC3NP_Pos (11U)
16021#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
16022#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
16023#define TIM_CCER_CC4E_Pos (12U)
16024#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
16025#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
16026#define TIM_CCER_CC4P_Pos (13U)
16027#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
16028#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
16029#define TIM_CCER_CC4NP_Pos (15U)
16030#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
16031#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
16032#define TIM_CCER_CC5E_Pos (16U)
16033#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)
16034#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk
16035#define TIM_CCER_CC5P_Pos (17U)
16036#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)
16037#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk
16038#define TIM_CCER_CC6E_Pos (20U)
16039#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)
16040#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk
16041#define TIM_CCER_CC6P_Pos (21U)
16042#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)
16043#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk
16045/******************* Bit definition for TIM_CNT register ********************/
16046#define TIM_CNT_CNT_Pos (0U)
16047#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
16048#define TIM_CNT_CNT TIM_CNT_CNT_Msk
16049#define TIM_CNT_UIFCPY_Pos (31U)
16050#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)
16051#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk
16053/******************* Bit definition for TIM_PSC register ********************/
16054#define TIM_PSC_PSC_Pos (0U)
16055#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
16056#define TIM_PSC_PSC TIM_PSC_PSC_Msk
16058/******************* Bit definition for TIM_ARR register ********************/
16059#define TIM_ARR_ARR_Pos (0U)
16060#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
16061#define TIM_ARR_ARR TIM_ARR_ARR_Msk
16063/******************* Bit definition for TIM_RCR register ********************/
16064#define TIM_RCR_REP_Pos (0U)
16065#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)
16066#define TIM_RCR_REP TIM_RCR_REP_Msk
16068/******************* Bit definition for TIM_CCR1 register *******************/
16069#define TIM_CCR1_CCR1_Pos (0U)
16070#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
16071#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
16073/******************* Bit definition for TIM_CCR2 register *******************/
16074#define TIM_CCR2_CCR2_Pos (0U)
16075#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
16076#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
16078/******************* Bit definition for TIM_CCR3 register *******************/
16079#define TIM_CCR3_CCR3_Pos (0U)
16080#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
16081#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
16083/******************* Bit definition for TIM_CCR4 register *******************/
16084#define TIM_CCR4_CCR4_Pos (0U)
16085#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
16086#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
16088/******************* Bit definition for TIM_CCR5 register *******************/
16089#define TIM_CCR5_CCR5_Pos (0U)
16090#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)
16091#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk
16092#define TIM_CCR5_GC5C1_Pos (29U)
16093#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)
16094#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk
16095#define TIM_CCR5_GC5C2_Pos (30U)
16096#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)
16097#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk
16098#define TIM_CCR5_GC5C3_Pos (31U)
16099#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)
16100#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk
16102/******************* Bit definition for TIM_CCR6 register *******************/
16103#define TIM_CCR6_CCR6_Pos (0U)
16104#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)
16105#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk
16107/******************* Bit definition for TIM_BDTR register *******************/
16108#define TIM_BDTR_DTG_Pos (0U)
16109#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
16110#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
16111#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
16112#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
16113#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
16114#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
16115#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
16116#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
16117#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
16118#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
16120#define TIM_BDTR_LOCK_Pos (8U)
16121#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
16122#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
16123#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
16124#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
16126#define TIM_BDTR_OSSI_Pos (10U)
16127#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
16128#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
16129#define TIM_BDTR_OSSR_Pos (11U)
16130#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
16131#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
16132#define TIM_BDTR_BKE_Pos (12U)
16133#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
16134#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
16135#define TIM_BDTR_BKP_Pos (13U)
16136#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
16137#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
16138#define TIM_BDTR_AOE_Pos (14U)
16139#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
16140#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
16141#define TIM_BDTR_MOE_Pos (15U)
16142#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
16143#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
16145#define TIM_BDTR_BKF_Pos (16U)
16146#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)
16147#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
16148#define TIM_BDTR_BK2F_Pos (20U)
16149#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)
16150#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk
16152#define TIM_BDTR_BK2E_Pos (24U)
16153#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)
16154#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk
16155#define TIM_BDTR_BK2P_Pos (25U)
16156#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)
16157#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk
16159/******************* Bit definition for TIM_DCR register ********************/
16160#define TIM_DCR_DBA_Pos (0U)
16161#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
16162#define TIM_DCR_DBA TIM_DCR_DBA_Msk
16163#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
16164#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
16165#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
16166#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
16167#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
16169#define TIM_DCR_DBL_Pos (8U)
16170#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
16171#define TIM_DCR_DBL TIM_DCR_DBL_Msk
16172#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
16173#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
16174#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
16175#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
16176#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
16178/******************* Bit definition for TIM_DMAR register *******************/
16179#define TIM_DMAR_DMAB_Pos (0U)
16180#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
16181#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
16183/******************* Bit definition for TIM1_OR1 register *******************/
16184#define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
16185#define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos)
16186#define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk
16187#define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos)
16188#define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos)
16190#define TIM1_OR1_ETR_ADC3_RMP_Pos (2U)
16191#define TIM1_OR1_ETR_ADC3_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC3_RMP_Pos)
16192#define TIM1_OR1_ETR_ADC3_RMP TIM1_OR1_ETR_ADC3_RMP_Msk
16193#define TIM1_OR1_ETR_ADC3_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC3_RMP_Pos)
16194#define TIM1_OR1_ETR_ADC3_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC3_RMP_Pos)
16196#define TIM1_OR1_TI1_RMP_Pos (4U)
16197#define TIM1_OR1_TI1_RMP_Msk (0x1UL << TIM1_OR1_TI1_RMP_Pos)
16198#define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk
16200/******************* Bit definition for TIM1_OR2 register *******************/
16201#define TIM1_OR2_BKINE_Pos (0U)
16202#define TIM1_OR2_BKINE_Msk (0x1UL << TIM1_OR2_BKINE_Pos)
16203#define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk
16204#define TIM1_OR2_BKCMP1E_Pos (1U)
16205#define TIM1_OR2_BKCMP1E_Msk (0x1UL << TIM1_OR2_BKCMP1E_Pos)
16206#define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk
16207#define TIM1_OR2_BKCMP2E_Pos (2U)
16208#define TIM1_OR2_BKCMP2E_Msk (0x1UL << TIM1_OR2_BKCMP2E_Pos)
16209#define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk
16210#define TIM1_OR2_BKDF1BK0E_Pos (8U)
16211#define TIM1_OR2_BKDF1BK0E_Msk (0x1UL << TIM1_OR2_BKDF1BK0E_Pos)
16212#define TIM1_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E_Msk
16213#define TIM1_OR2_BKINP_Pos (9U)
16214#define TIM1_OR2_BKINP_Msk (0x1UL << TIM1_OR2_BKINP_Pos)
16215#define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk
16216#define TIM1_OR2_BKCMP1P_Pos (10U)
16217#define TIM1_OR2_BKCMP1P_Msk (0x1UL << TIM1_OR2_BKCMP1P_Pos)
16218#define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk
16219#define TIM1_OR2_BKCMP2P_Pos (11U)
16220#define TIM1_OR2_BKCMP2P_Msk (0x1UL << TIM1_OR2_BKCMP2P_Pos)
16221#define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk
16223#define TIM1_OR2_ETRSEL_Pos (14U)
16224#define TIM1_OR2_ETRSEL_Msk (0x7UL << TIM1_OR2_ETRSEL_Pos)
16225#define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk
16226#define TIM1_OR2_ETRSEL_0 (0x1UL << TIM1_OR2_ETRSEL_Pos)
16227#define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos)
16228#define TIM1_OR2_ETRSEL_2 (0x4UL << TIM1_OR2_ETRSEL_Pos)
16230/******************* Bit definition for TIM1_OR3 register *******************/
16231#define TIM1_OR3_BK2INE_Pos (0U)
16232#define TIM1_OR3_BK2INE_Msk (0x1UL << TIM1_OR3_BK2INE_Pos)
16233#define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk
16234#define TIM1_OR3_BK2CMP1E_Pos (1U)
16235#define TIM1_OR3_BK2CMP1E_Msk (0x1UL << TIM1_OR3_BK2CMP1E_Pos)
16236#define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk
16237#define TIM1_OR3_BK2CMP2E_Pos (2U)
16238#define TIM1_OR3_BK2CMP2E_Msk (0x1UL << TIM1_OR3_BK2CMP2E_Pos)
16239#define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk
16240#define TIM1_OR3_BK2DF1BK1E_Pos (8U)
16241#define TIM1_OR3_BK2DF1BK1E_Msk (0x1UL << TIM1_OR3_BK2DF1BK1E_Pos)
16242#define TIM1_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E_Msk
16243#define TIM1_OR3_BK2INP_Pos (9U)
16244#define TIM1_OR3_BK2INP_Msk (0x1UL << TIM1_OR3_BK2INP_Pos)
16245#define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk
16246#define TIM1_OR3_BK2CMP1P_Pos (10U)
16247#define TIM1_OR3_BK2CMP1P_Msk (0x1UL << TIM1_OR3_BK2CMP1P_Pos)
16248#define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk
16249#define TIM1_OR3_BK2CMP2P_Pos (11U)
16250#define TIM1_OR3_BK2CMP2P_Msk (0x1UL << TIM1_OR3_BK2CMP2P_Pos)
16251#define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk
16253/******************* Bit definition for TIM8_OR1 register *******************/
16254#define TIM8_OR1_ETR_ADC2_RMP_Pos (0U)
16255#define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3UL << TIM8_OR1_ETR_ADC2_RMP_Pos)
16256#define TIM8_OR1_ETR_ADC2_RMP TIM8_OR1_ETR_ADC2_RMP_Msk
16257#define TIM8_OR1_ETR_ADC2_RMP_0 (0x1UL << TIM8_OR1_ETR_ADC2_RMP_Pos)
16258#define TIM8_OR1_ETR_ADC2_RMP_1 (0x2UL << TIM8_OR1_ETR_ADC2_RMP_Pos)
16260#define TIM8_OR1_ETR_ADC3_RMP_Pos (2U)
16261#define TIM8_OR1_ETR_ADC3_RMP_Msk (0x3UL << TIM8_OR1_ETR_ADC3_RMP_Pos)
16262#define TIM8_OR1_ETR_ADC3_RMP TIM8_OR1_ETR_ADC3_RMP_Msk
16263#define TIM8_OR1_ETR_ADC3_RMP_0 (0x1UL << TIM8_OR1_ETR_ADC3_RMP_Pos)
16264#define TIM8_OR1_ETR_ADC3_RMP_1 (0x2UL << TIM8_OR1_ETR_ADC3_RMP_Pos)
16266#define TIM8_OR1_TI1_RMP_Pos (4U)
16267#define TIM8_OR1_TI1_RMP_Msk (0x1UL << TIM8_OR1_TI1_RMP_Pos)
16268#define TIM8_OR1_TI1_RMP TIM8_OR1_TI1_RMP_Msk
16270/******************* Bit definition for TIM8_OR2 register *******************/
16271#define TIM8_OR2_BKINE_Pos (0U)
16272#define TIM8_OR2_BKINE_Msk (0x1UL << TIM8_OR2_BKINE_Pos)
16273#define TIM8_OR2_BKINE TIM8_OR2_BKINE_Msk
16274#define TIM8_OR2_BKCMP1E_Pos (1U)
16275#define TIM8_OR2_BKCMP1E_Msk (0x1UL << TIM8_OR2_BKCMP1E_Pos)
16276#define TIM8_OR2_BKCMP1E TIM8_OR2_BKCMP1E_Msk
16277#define TIM8_OR2_BKCMP2E_Pos (2U)
16278#define TIM8_OR2_BKCMP2E_Msk (0x1UL << TIM8_OR2_BKCMP2E_Pos)
16279#define TIM8_OR2_BKCMP2E TIM8_OR2_BKCMP2E_Msk
16280#define TIM8_OR2_BKDF1BK2E_Pos (8U)
16281#define TIM8_OR2_BKDF1BK2E_Msk (0x1UL << TIM8_OR2_BKDF1BK2E_Pos)
16282#define TIM8_OR2_BKDF1BK2E TIM8_OR2_BKDF1BK2E_Msk
16283#define TIM8_OR2_BKINP_Pos (9U)
16284#define TIM8_OR2_BKINP_Msk (0x1UL << TIM8_OR2_BKINP_Pos)
16285#define TIM8_OR2_BKINP TIM8_OR2_BKINP_Msk
16286#define TIM8_OR2_BKCMP1P_Pos (10U)
16287#define TIM8_OR2_BKCMP1P_Msk (0x1UL << TIM8_OR2_BKCMP1P_Pos)
16288#define TIM8_OR2_BKCMP1P TIM8_OR2_BKCMP1P_Msk
16289#define TIM8_OR2_BKCMP2P_Pos (11U)
16290#define TIM8_OR2_BKCMP2P_Msk (0x1UL << TIM8_OR2_BKCMP2P_Pos)
16291#define TIM8_OR2_BKCMP2P TIM8_OR2_BKCMP2P_Msk
16293#define TIM8_OR2_ETRSEL_Pos (14U)
16294#define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos)
16295#define TIM8_OR2_ETRSEL TIM8_OR2_ETRSEL_Msk
16296#define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos)
16297#define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos)
16298#define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos)
16300/******************* Bit definition for TIM8_OR3 register *******************/
16301#define TIM8_OR3_BK2INE_Pos (0U)
16302#define TIM8_OR3_BK2INE_Msk (0x1UL << TIM8_OR3_BK2INE_Pos)
16303#define TIM8_OR3_BK2INE TIM8_OR3_BK2INE_Msk
16304#define TIM8_OR3_BK2CMP1E_Pos (1U)
16305#define TIM8_OR3_BK2CMP1E_Msk (0x1UL << TIM8_OR3_BK2CMP1E_Pos)
16306#define TIM8_OR3_BK2CMP1E TIM8_OR3_BK2CMP1E_Msk
16307#define TIM8_OR3_BK2CMP2E_Pos (2U)
16308#define TIM8_OR3_BK2CMP2E_Msk (0x1UL << TIM8_OR3_BK2CMP2E_Pos)
16309#define TIM8_OR3_BK2CMP2E TIM8_OR3_BK2CMP2E_Msk
16310#define TIM8_OR3_BK2DF1BK3E_Pos (8U)
16311#define TIM8_OR3_BK2DF1BK3E_Msk (0x1UL << TIM8_OR3_BK2DF1BK3E_Pos)
16312#define TIM8_OR3_BK2DF1BK3E TIM8_OR3_BK2DF1BK3E_Msk
16313#define TIM8_OR3_BK2INP_Pos (9U)
16314#define TIM8_OR3_BK2INP_Msk (0x1UL << TIM8_OR3_BK2INP_Pos)
16315#define TIM8_OR3_BK2INP TIM8_OR3_BK2INP_Msk
16316#define TIM8_OR3_BK2CMP1P_Pos (10U)
16317#define TIM8_OR3_BK2CMP1P_Msk (0x1UL << TIM8_OR3_BK2CMP1P_Pos)
16318#define TIM8_OR3_BK2CMP1P TIM8_OR3_BK2CMP1P_Msk
16319#define TIM8_OR3_BK2CMP2P_Pos (11U)
16320#define TIM8_OR3_BK2CMP2P_Msk (0x1UL << TIM8_OR3_BK2CMP2P_Pos)
16321#define TIM8_OR3_BK2CMP2P TIM8_OR3_BK2CMP2P_Msk
16323/******************* Bit definition for TIM2_OR1 register *******************/
16324#define TIM2_OR1_ITR1_RMP_Pos (0U)
16325#define TIM2_OR1_ITR1_RMP_Msk (0x1UL << TIM2_OR1_ITR1_RMP_Pos)
16326#define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk
16327#define TIM2_OR1_ETR1_RMP_Pos (1U)
16328#define TIM2_OR1_ETR1_RMP_Msk (0x1UL << TIM2_OR1_ETR1_RMP_Pos)
16329#define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk
16331#define TIM2_OR1_TI4_RMP_Pos (2U)
16332#define TIM2_OR1_TI4_RMP_Msk (0x3UL << TIM2_OR1_TI4_RMP_Pos)
16333#define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk
16334#define TIM2_OR1_TI4_RMP_0 (0x1UL << TIM2_OR1_TI4_RMP_Pos)
16335#define TIM2_OR1_TI4_RMP_1 (0x2UL << TIM2_OR1_TI4_RMP_Pos)
16337/******************* Bit definition for TIM2_OR2 register *******************/
16338#define TIM2_OR2_ETRSEL_Pos (14U)
16339#define TIM2_OR2_ETRSEL_Msk (0x7UL << TIM2_OR2_ETRSEL_Pos)
16340#define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk
16341#define TIM2_OR2_ETRSEL_0 (0x1UL << TIM2_OR2_ETRSEL_Pos)
16342#define TIM2_OR2_ETRSEL_1 (0x2UL << TIM2_OR2_ETRSEL_Pos)
16343#define TIM2_OR2_ETRSEL_2 (0x4UL << TIM2_OR2_ETRSEL_Pos)
16345/******************* Bit definition for TIM3_OR1 register *******************/
16346#define TIM3_OR1_TI1_RMP_Pos (0U)
16347#define TIM3_OR1_TI1_RMP_Msk (0x3UL << TIM3_OR1_TI1_RMP_Pos)
16348#define TIM3_OR1_TI1_RMP TIM3_OR1_TI1_RMP_Msk
16349#define TIM3_OR1_TI1_RMP_0 (0x1UL << TIM3_OR1_TI1_RMP_Pos)
16350#define TIM3_OR1_TI1_RMP_1 (0x2UL << TIM3_OR1_TI1_RMP_Pos)
16352/******************* Bit definition for TIM3_OR2 register *******************/
16353#define TIM3_OR2_ETRSEL_Pos (14U)
16354#define TIM3_OR2_ETRSEL_Msk (0x7UL << TIM3_OR2_ETRSEL_Pos)
16355#define TIM3_OR2_ETRSEL TIM3_OR2_ETRSEL_Msk
16356#define TIM3_OR2_ETRSEL_0 (0x1UL << TIM3_OR2_ETRSEL_Pos)
16357#define TIM3_OR2_ETRSEL_1 (0x2UL << TIM3_OR2_ETRSEL_Pos)
16358#define TIM3_OR2_ETRSEL_2 (0x4UL << TIM3_OR2_ETRSEL_Pos)
16360/******************* Bit definition for TIM15_OR1 register ******************/
16361#define TIM15_OR1_TI1_RMP_Pos (0U)
16362#define TIM15_OR1_TI1_RMP_Msk (0x1UL << TIM15_OR1_TI1_RMP_Pos)
16363#define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk
16365#define TIM15_OR1_ENCODER_MODE_Pos (1U)
16366#define TIM15_OR1_ENCODER_MODE_Msk (0x3UL << TIM15_OR1_ENCODER_MODE_Pos)
16367#define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk
16368#define TIM15_OR1_ENCODER_MODE_0 (0x1UL << TIM15_OR1_ENCODER_MODE_Pos)
16369#define TIM15_OR1_ENCODER_MODE_1 (0x2UL << TIM15_OR1_ENCODER_MODE_Pos)
16371/******************* Bit definition for TIM15_OR2 register ******************/
16372#define TIM15_OR2_BKINE_Pos (0U)
16373#define TIM15_OR2_BKINE_Msk (0x1UL << TIM15_OR2_BKINE_Pos)
16374#define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk
16375#define TIM15_OR2_BKCMP1E_Pos (1U)
16376#define TIM15_OR2_BKCMP1E_Msk (0x1UL << TIM15_OR2_BKCMP1E_Pos)
16377#define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk
16378#define TIM15_OR2_BKCMP2E_Pos (2U)
16379#define TIM15_OR2_BKCMP2E_Msk (0x1UL << TIM15_OR2_BKCMP2E_Pos)
16380#define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk
16381#define TIM15_OR2_BKDF1BK0E_Pos (8U)
16382#define TIM15_OR2_BKDF1BK0E_Msk (0x1UL << TIM15_OR2_BKDF1BK0E_Pos)
16383#define TIM15_OR2_BKDF1BK0E TIM15_OR2_BKDF1BK0E_Msk
16384#define TIM15_OR2_BKINP_Pos (9U)
16385#define TIM15_OR2_BKINP_Msk (0x1UL << TIM15_OR2_BKINP_Pos)
16386#define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk
16387#define TIM15_OR2_BKCMP1P_Pos (10U)
16388#define TIM15_OR2_BKCMP1P_Msk (0x1UL << TIM15_OR2_BKCMP1P_Pos)
16389#define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk
16390#define TIM15_OR2_BKCMP2P_Pos (11U)
16391#define TIM15_OR2_BKCMP2P_Msk (0x1UL << TIM15_OR2_BKCMP2P_Pos)
16392#define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk
16394/******************* Bit definition for TIM16_OR1 register ******************/
16395#define TIM16_OR1_TI1_RMP_Pos (0U)
16396#define TIM16_OR1_TI1_RMP_Msk (0x7UL << TIM16_OR1_TI1_RMP_Pos)
16397#define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk
16398#define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos)
16399#define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos)
16400#define TIM16_OR1_TI1_RMP_2 (0x4UL << TIM16_OR1_TI1_RMP_Pos)
16402/******************* Bit definition for TIM16_OR2 register ******************/
16403#define TIM16_OR2_BKINE_Pos (0U)
16404#define TIM16_OR2_BKINE_Msk (0x1UL << TIM16_OR2_BKINE_Pos)
16405#define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk
16406#define TIM16_OR2_BKCMP1E_Pos (1U)
16407#define TIM16_OR2_BKCMP1E_Msk (0x1UL << TIM16_OR2_BKCMP1E_Pos)
16408#define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk
16409#define TIM16_OR2_BKCMP2E_Pos (2U)
16410#define TIM16_OR2_BKCMP2E_Msk (0x1UL << TIM16_OR2_BKCMP2E_Pos)
16411#define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk
16412#define TIM16_OR2_BKDF1BK1E_Pos (8U)
16413#define TIM16_OR2_BKDF1BK1E_Msk (0x1UL << TIM16_OR2_BKDF1BK1E_Pos)
16414#define TIM16_OR2_BKDF1BK1E TIM16_OR2_BKDF1BK1E_Msk
16415#define TIM16_OR2_BKINP_Pos (9U)
16416#define TIM16_OR2_BKINP_Msk (0x1UL << TIM16_OR2_BKINP_Pos)
16417#define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk
16418#define TIM16_OR2_BKCMP1P_Pos (10U)
16419#define TIM16_OR2_BKCMP1P_Msk (0x1UL << TIM16_OR2_BKCMP1P_Pos)
16420#define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk
16421#define TIM16_OR2_BKCMP2P_Pos (11U)
16422#define TIM16_OR2_BKCMP2P_Msk (0x1UL << TIM16_OR2_BKCMP2P_Pos)
16423#define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk
16425/******************* Bit definition for TIM17_OR1 register ******************/
16426#define TIM17_OR1_TI1_RMP_Pos (0U)
16427#define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos)
16428#define TIM17_OR1_TI1_RMP TIM17_OR1_TI1_RMP_Msk
16429#define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos)
16430#define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos)
16432/******************* Bit definition for TIM17_OR2 register ******************/
16433#define TIM17_OR2_BKINE_Pos (0U)
16434#define TIM17_OR2_BKINE_Msk (0x1UL << TIM17_OR2_BKINE_Pos)
16435#define TIM17_OR2_BKINE TIM17_OR2_BKINE_Msk
16436#define TIM17_OR2_BKCMP1E_Pos (1U)
16437#define TIM17_OR2_BKCMP1E_Msk (0x1UL << TIM17_OR2_BKCMP1E_Pos)
16438#define TIM17_OR2_BKCMP1E TIM17_OR2_BKCMP1E_Msk
16439#define TIM17_OR2_BKCMP2E_Pos (2U)
16440#define TIM17_OR2_BKCMP2E_Msk (0x1UL << TIM17_OR2_BKCMP2E_Pos)
16441#define TIM17_OR2_BKCMP2E TIM17_OR2_BKCMP2E_Msk
16442#define TIM17_OR2_BKDF1BK2E_Pos (8U)
16443#define TIM17_OR2_BKDF1BK2E_Msk (0x1UL << TIM17_OR2_BKDF1BK2E_Pos)
16444#define TIM17_OR2_BKDF1BK2E TIM17_OR2_BKDF1BK2E_Msk
16445#define TIM17_OR2_BKINP_Pos (9U)
16446#define TIM17_OR2_BKINP_Msk (0x1UL << TIM17_OR2_BKINP_Pos)
16447#define TIM17_OR2_BKINP TIM17_OR2_BKINP_Msk
16448#define TIM17_OR2_BKCMP1P_Pos (10U)
16449#define TIM17_OR2_BKCMP1P_Msk (0x1UL << TIM17_OR2_BKCMP1P_Pos)
16450#define TIM17_OR2_BKCMP1P TIM17_OR2_BKCMP1P_Msk
16451#define TIM17_OR2_BKCMP2P_Pos (11U)
16452#define TIM17_OR2_BKCMP2P_Msk (0x1UL << TIM17_OR2_BKCMP2P_Pos)
16453#define TIM17_OR2_BKCMP2P TIM17_OR2_BKCMP2P_Msk
16455/******************************************************************************/
16456/* */
16457/* Low Power Timer (LPTIM) */
16458/* */
16459/******************************************************************************/
16460/****************** Bit definition for LPTIM_ISR register *******************/
16461#define LPTIM_ISR_CMPM_Pos (0U)
16462#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
16463#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
16464#define LPTIM_ISR_ARRM_Pos (1U)
16465#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
16466#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
16467#define LPTIM_ISR_EXTTRIG_Pos (2U)
16468#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
16469#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
16470#define LPTIM_ISR_CMPOK_Pos (3U)
16471#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
16472#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
16473#define LPTIM_ISR_ARROK_Pos (4U)
16474#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
16475#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
16476#define LPTIM_ISR_UP_Pos (5U)
16477#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
16478#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
16479#define LPTIM_ISR_DOWN_Pos (6U)
16480#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
16481#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
16483/****************** Bit definition for LPTIM_ICR register *******************/
16484#define LPTIM_ICR_CMPMCF_Pos (0U)
16485#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
16486#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
16487#define LPTIM_ICR_ARRMCF_Pos (1U)
16488#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
16489#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
16490#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
16491#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
16492#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
16493#define LPTIM_ICR_CMPOKCF_Pos (3U)
16494#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
16495#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
16496#define LPTIM_ICR_ARROKCF_Pos (4U)
16497#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
16498#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
16499#define LPTIM_ICR_UPCF_Pos (5U)
16500#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
16501#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
16502#define LPTIM_ICR_DOWNCF_Pos (6U)
16503#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
16504#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
16506/****************** Bit definition for LPTIM_IER register ********************/
16507#define LPTIM_IER_CMPMIE_Pos (0U)
16508#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
16509#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
16510#define LPTIM_IER_ARRMIE_Pos (1U)
16511#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
16512#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
16513#define LPTIM_IER_EXTTRIGIE_Pos (2U)
16514#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
16515#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
16516#define LPTIM_IER_CMPOKIE_Pos (3U)
16517#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
16518#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
16519#define LPTIM_IER_ARROKIE_Pos (4U)
16520#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
16521#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
16522#define LPTIM_IER_UPIE_Pos (5U)
16523#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
16524#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
16525#define LPTIM_IER_DOWNIE_Pos (6U)
16526#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
16527#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
16529/****************** Bit definition for LPTIM_CFGR register *******************/
16530#define LPTIM_CFGR_CKSEL_Pos (0U)
16531#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
16532#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
16534#define LPTIM_CFGR_CKPOL_Pos (1U)
16535#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
16536#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
16537#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
16538#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
16540#define LPTIM_CFGR_CKFLT_Pos (3U)
16541#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
16542#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
16543#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
16544#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
16546#define LPTIM_CFGR_TRGFLT_Pos (6U)
16547#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
16548#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
16549#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
16550#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
16552#define LPTIM_CFGR_PRESC_Pos (9U)
16553#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
16554#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
16555#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
16556#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
16557#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
16559#define LPTIM_CFGR_TRIGSEL_Pos (13U)
16560#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
16561#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
16562#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
16563#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
16564#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
16566#define LPTIM_CFGR_TRIGEN_Pos (17U)
16567#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
16568#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
16569#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
16570#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
16572#define LPTIM_CFGR_TIMOUT_Pos (19U)
16573#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
16574#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
16575#define LPTIM_CFGR_WAVE_Pos (20U)
16576#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
16577#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
16578#define LPTIM_CFGR_WAVPOL_Pos (21U)
16579#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
16580#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
16581#define LPTIM_CFGR_PRELOAD_Pos (22U)
16582#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
16583#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
16584#define LPTIM_CFGR_COUNTMODE_Pos (23U)
16585#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
16586#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
16587#define LPTIM_CFGR_ENC_Pos (24U)
16588#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
16589#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
16591/****************** Bit definition for LPTIM_CR register ********************/
16592#define LPTIM_CR_ENABLE_Pos (0U)
16593#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
16594#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
16595#define LPTIM_CR_SNGSTRT_Pos (1U)
16596#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos)
16597#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
16598#define LPTIM_CR_CNTSTRT_Pos (2U)
16599#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
16600#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
16602/****************** Bit definition for LPTIM_CMP register *******************/
16603#define LPTIM_CMP_CMP_Pos (0U)
16604#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
16605#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
16607/****************** Bit definition for LPTIM_ARR register *******************/
16608#define LPTIM_ARR_ARR_Pos (0U)
16609#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
16610#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
16612/****************** Bit definition for LPTIM_CNT register *******************/
16613#define LPTIM_CNT_CNT_Pos (0U)
16614#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
16615#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
16617/****************** Bit definition for LPTIM_OR register ********************/
16618#define LPTIM_OR_OR_Pos (0U)
16619#define LPTIM_OR_OR_Msk (0x3UL << LPTIM_OR_OR_Pos)
16620#define LPTIM_OR_OR LPTIM_OR_OR_Msk
16621#define LPTIM_OR_OR_0 (0x1UL << LPTIM_OR_OR_Pos)
16622#define LPTIM_OR_OR_1 (0x2UL << LPTIM_OR_OR_Pos)
16624/******************************************************************************/
16625/* */
16626/* Analog Comparators (COMP) */
16627/* */
16628/******************************************************************************/
16629/********************** Bit definition for COMP_CSR register ****************/
16630#define COMP_CSR_EN_Pos (0U)
16631#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos)
16632#define COMP_CSR_EN COMP_CSR_EN_Msk
16634#define COMP_CSR_PWRMODE_Pos (2U)
16635#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos)
16636#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk
16637#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos)
16638#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos)
16640#define COMP_CSR_INMSEL_Pos (4U)
16641#define COMP_CSR_INMSEL_Msk (0x7UL << COMP_CSR_INMSEL_Pos)
16642#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk
16643#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos)
16644#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos)
16645#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos)
16647#define COMP_CSR_INPSEL_Pos (7U)
16648#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos)
16649#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk
16650#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos)
16652#define COMP_CSR_WINMODE_Pos (9U)
16653#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos)
16654#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk
16656#define COMP_CSR_POLARITY_Pos (15U)
16657#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos)
16658#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk
16660#define COMP_CSR_HYST_Pos (16U)
16661#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos)
16662#define COMP_CSR_HYST COMP_CSR_HYST_Msk
16663#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos)
16664#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos)
16666#define COMP_CSR_BLANKING_Pos (18U)
16667#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos)
16668#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk
16669#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos)
16670#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos)
16671#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos)
16673#define COMP_CSR_BRGEN_Pos (22U)
16674#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos)
16675#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk
16676#define COMP_CSR_SCALEN_Pos (23U)
16677#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos)
16678#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk
16680#define COMP_CSR_VALUE_Pos (30U)
16681#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos)
16682#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk
16684#define COMP_CSR_LOCK_Pos (31U)
16685#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos)
16686#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk
16688/******************************************************************************/
16689/* */
16690/* Operational Amplifier (OPAMP) */
16691/* */
16692/******************************************************************************/
16693/********************* Bit definition for OPAMPx_CSR register ***************/
16694#define OPAMP_CSR_OPAMPxEN_Pos (0U)
16695#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)
16696#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk
16697#define OPAMP_CSR_OPALPM_Pos (1U)
16698#define OPAMP_CSR_OPALPM_Msk (0x1UL << OPAMP_CSR_OPALPM_Pos)
16699#define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk
16701#define OPAMP_CSR_OPAMODE_Pos (2U)
16702#define OPAMP_CSR_OPAMODE_Msk (0x3UL << OPAMP_CSR_OPAMODE_Pos)
16703#define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk
16704#define OPAMP_CSR_OPAMODE_0 (0x1UL << OPAMP_CSR_OPAMODE_Pos)
16705#define OPAMP_CSR_OPAMODE_1 (0x2UL << OPAMP_CSR_OPAMODE_Pos)
16707#define OPAMP_CSR_PGGAIN_Pos (4U)
16708#define OPAMP_CSR_PGGAIN_Msk (0x3UL << OPAMP_CSR_PGGAIN_Pos)
16709#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk
16710#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)
16711#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)
16713#define OPAMP_CSR_VMSEL_Pos (8U)
16714#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)
16715#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk
16716#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)
16717#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)
16719#define OPAMP_CSR_VPSEL_Pos (10U)
16720#define OPAMP_CSR_VPSEL_Msk (0x1UL << OPAMP_CSR_VPSEL_Pos)
16721#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk
16722#define OPAMP_CSR_CALON_Pos (12U)
16723#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)
16724#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk
16725#define OPAMP_CSR_CALSEL_Pos (13U)
16726#define OPAMP_CSR_CALSEL_Msk (0x1UL << OPAMP_CSR_CALSEL_Pos)
16727#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk
16728#define OPAMP_CSR_USERTRIM_Pos (14U)
16729#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)
16730#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk
16731#define OPAMP_CSR_CALOUT_Pos (15U)
16732#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos)
16733#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk
16735/********************* Bit definition for OPAMP1_CSR register ***************/
16736#define OPAMP1_CSR_OPAEN_Pos (0U)
16737#define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos)
16738#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk
16739#define OPAMP1_CSR_OPALPM_Pos (1U)
16740#define OPAMP1_CSR_OPALPM_Msk (0x1UL << OPAMP1_CSR_OPALPM_Pos)
16741#define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk
16743#define OPAMP1_CSR_OPAMODE_Pos (2U)
16744#define OPAMP1_CSR_OPAMODE_Msk (0x3UL << OPAMP1_CSR_OPAMODE_Pos)
16745#define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk
16746#define OPAMP1_CSR_OPAMODE_0 (0x1UL << OPAMP1_CSR_OPAMODE_Pos)
16747#define OPAMP1_CSR_OPAMODE_1 (0x2UL << OPAMP1_CSR_OPAMODE_Pos)
16749#define OPAMP1_CSR_PGAGAIN_Pos (4U)
16750#define OPAMP1_CSR_PGAGAIN_Msk (0x3UL << OPAMP1_CSR_PGAGAIN_Pos)
16751#define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk
16752#define OPAMP1_CSR_PGAGAIN_0 (0x1UL << OPAMP1_CSR_PGAGAIN_Pos)
16753#define OPAMP1_CSR_PGAGAIN_1 (0x2UL << OPAMP1_CSR_PGAGAIN_Pos)
16755#define OPAMP1_CSR_VMSEL_Pos (8U)
16756#define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos)
16757#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk
16758#define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos)
16759#define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos)
16761#define OPAMP1_CSR_VPSEL_Pos (10U)
16762#define OPAMP1_CSR_VPSEL_Msk (0x1UL << OPAMP1_CSR_VPSEL_Pos)
16763#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk
16764#define OPAMP1_CSR_CALON_Pos (12U)
16765#define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos)
16766#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk
16767#define OPAMP1_CSR_CALSEL_Pos (13U)
16768#define OPAMP1_CSR_CALSEL_Msk (0x1UL << OPAMP1_CSR_CALSEL_Pos)
16769#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk
16770#define OPAMP1_CSR_USERTRIM_Pos (14U)
16771#define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos)
16772#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk
16773#define OPAMP1_CSR_CALOUT_Pos (15U)
16774#define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos)
16775#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk
16777#define OPAMP1_CSR_OPARANGE_Pos (31U)
16778#define OPAMP1_CSR_OPARANGE_Msk (0x1UL << OPAMP1_CSR_OPARANGE_Pos)
16779#define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk
16781/********************* Bit definition for OPAMP2_CSR register ***************/
16782#define OPAMP2_CSR_OPAEN_Pos (0U)
16783#define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos)
16784#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk
16785#define OPAMP2_CSR_OPALPM_Pos (1U)
16786#define OPAMP2_CSR_OPALPM_Msk (0x1UL << OPAMP2_CSR_OPALPM_Pos)
16787#define OPAMP2_CSR_OPALPM OPAMP2_CSR_OPALPM_Msk
16789#define OPAMP2_CSR_OPAMODE_Pos (2U)
16790#define OPAMP2_CSR_OPAMODE_Msk (0x3UL << OPAMP2_CSR_OPAMODE_Pos)
16791#define OPAMP2_CSR_OPAMODE OPAMP2_CSR_OPAMODE_Msk
16792#define OPAMP2_CSR_OPAMODE_0 (0x1UL << OPAMP2_CSR_OPAMODE_Pos)
16793#define OPAMP2_CSR_OPAMODE_1 (0x2UL << OPAMP2_CSR_OPAMODE_Pos)
16795#define OPAMP2_CSR_PGAGAIN_Pos (4U)
16796#define OPAMP2_CSR_PGAGAIN_Msk (0x3UL << OPAMP2_CSR_PGAGAIN_Pos)
16797#define OPAMP2_CSR_PGAGAIN OPAMP2_CSR_PGAGAIN_Msk
16798#define OPAMP2_CSR_PGAGAIN_0 (0x1UL << OPAMP2_CSR_PGAGAIN_Pos)
16799#define OPAMP2_CSR_PGAGAIN_1 (0x2UL << OPAMP2_CSR_PGAGAIN_Pos)
16801#define OPAMP2_CSR_VMSEL_Pos (8U)
16802#define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos)
16803#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk
16804#define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos)
16805#define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos)
16807#define OPAMP2_CSR_VPSEL_Pos (10U)
16808#define OPAMP2_CSR_VPSEL_Msk (0x1UL << OPAMP2_CSR_VPSEL_Pos)
16809#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk
16810#define OPAMP2_CSR_CALON_Pos (12U)
16811#define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos)
16812#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk
16813#define OPAMP2_CSR_CALSEL_Pos (13U)
16814#define OPAMP2_CSR_CALSEL_Msk (0x1UL << OPAMP2_CSR_CALSEL_Pos)
16815#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk
16816#define OPAMP2_CSR_USERTRIM_Pos (14U)
16817#define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos)
16818#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk
16819#define OPAMP2_CSR_CALOUT_Pos (15U)
16820#define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos)
16821#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk
16823/******************* Bit definition for OPAMP_OTR register ******************/
16824#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
16825#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos)
16826#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk
16827#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
16828#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos)
16829#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk
16831/******************* Bit definition for OPAMP1_OTR register ******************/
16832#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
16833#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos)
16834#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk
16835#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
16836#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos)
16837#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk
16839/******************* Bit definition for OPAMP2_OTR register ******************/
16840#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
16841#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos)
16842#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk
16843#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
16844#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos)
16845#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk
16847/******************* Bit definition for OPAMP_LPOTR register ****************/
16848#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U)
16849#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos)
16850#define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk
16851#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U)
16852#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos)
16853#define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk
16855/******************* Bit definition for OPAMP1_LPOTR register ****************/
16856#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U)
16857#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos)
16858#define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk
16859#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U)
16860#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos)
16861#define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk
16863/******************* Bit definition for OPAMP2_LPOTR register ****************/
16864#define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos (0U)
16865#define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos)
16866#define OPAMP2_LPOTR_TRIMLPOFFSETN OPAMP2_LPOTR_TRIMLPOFFSETN_Msk
16867#define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos (8U)
16868#define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos)
16869#define OPAMP2_LPOTR_TRIMLPOFFSETP OPAMP2_LPOTR_TRIMLPOFFSETP_Msk
16871/******************************************************************************/
16872/* */
16873/* Touch Sensing Controller (TSC) */
16874/* */
16875/******************************************************************************/
16876/******************* Bit definition for TSC_CR register *********************/
16877#define TSC_CR_TSCE_Pos (0U)
16878#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos)
16879#define TSC_CR_TSCE TSC_CR_TSCE_Msk
16880#define TSC_CR_START_Pos (1U)
16881#define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos)
16882#define TSC_CR_START TSC_CR_START_Msk
16883#define TSC_CR_AM_Pos (2U)
16884#define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos)
16885#define TSC_CR_AM TSC_CR_AM_Msk
16886#define TSC_CR_SYNCPOL_Pos (3U)
16887#define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos)
16888#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk
16889#define TSC_CR_IODEF_Pos (4U)
16890#define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos)
16891#define TSC_CR_IODEF TSC_CR_IODEF_Msk
16893#define TSC_CR_MCV_Pos (5U)
16894#define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos)
16895#define TSC_CR_MCV TSC_CR_MCV_Msk
16896#define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos)
16897#define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos)
16898#define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos)
16900#define TSC_CR_PGPSC_Pos (12U)
16901#define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos)
16902#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk
16903#define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos)
16904#define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos)
16905#define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos)
16907#define TSC_CR_SSPSC_Pos (15U)
16908#define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos)
16909#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk
16910#define TSC_CR_SSE_Pos (16U)
16911#define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos)
16912#define TSC_CR_SSE TSC_CR_SSE_Msk
16914#define TSC_CR_SSD_Pos (17U)
16915#define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos)
16916#define TSC_CR_SSD TSC_CR_SSD_Msk
16917#define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos)
16918#define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos)
16919#define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos)
16920#define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos)
16921#define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos)
16922#define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos)
16923#define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos)
16925#define TSC_CR_CTPL_Pos (24U)
16926#define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos)
16927#define TSC_CR_CTPL TSC_CR_CTPL_Msk
16928#define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos)
16929#define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos)
16930#define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos)
16931#define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos)
16933#define TSC_CR_CTPH_Pos (28U)
16934#define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos)
16935#define TSC_CR_CTPH TSC_CR_CTPH_Msk
16936#define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos)
16937#define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos)
16938#define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos)
16939#define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos)
16941/******************* Bit definition for TSC_IER register ********************/
16942#define TSC_IER_EOAIE_Pos (0U)
16943#define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos)
16944#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk
16945#define TSC_IER_MCEIE_Pos (1U)
16946#define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos)
16947#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk
16949/******************* Bit definition for TSC_ICR register ********************/
16950#define TSC_ICR_EOAIC_Pos (0U)
16951#define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos)
16952#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk
16953#define TSC_ICR_MCEIC_Pos (1U)
16954#define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos)
16955#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk
16957/******************* Bit definition for TSC_ISR register ********************/
16958#define TSC_ISR_EOAF_Pos (0U)
16959#define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos)
16960#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk
16961#define TSC_ISR_MCEF_Pos (1U)
16962#define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos)
16963#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk
16965/******************* Bit definition for TSC_IOHCR register ******************/
16966#define TSC_IOHCR_G1_IO1_Pos (0U)
16967#define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos)
16968#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk
16969#define TSC_IOHCR_G1_IO2_Pos (1U)
16970#define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos)
16971#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk
16972#define TSC_IOHCR_G1_IO3_Pos (2U)
16973#define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos)
16974#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk
16975#define TSC_IOHCR_G1_IO4_Pos (3U)
16976#define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos)
16977#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk
16978#define TSC_IOHCR_G2_IO1_Pos (4U)
16979#define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos)
16980#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk
16981#define TSC_IOHCR_G2_IO2_Pos (5U)
16982#define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos)
16983#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk
16984#define TSC_IOHCR_G2_IO3_Pos (6U)
16985#define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos)
16986#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk
16987#define TSC_IOHCR_G2_IO4_Pos (7U)
16988#define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos)
16989#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk
16990#define TSC_IOHCR_G3_IO1_Pos (8U)
16991#define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos)
16992#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk
16993#define TSC_IOHCR_G3_IO2_Pos (9U)
16994#define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos)
16995#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk
16996#define TSC_IOHCR_G3_IO3_Pos (10U)
16997#define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos)
16998#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk
16999#define TSC_IOHCR_G3_IO4_Pos (11U)
17000#define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos)
17001#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk
17002#define TSC_IOHCR_G4_IO1_Pos (12U)
17003#define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos)
17004#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk
17005#define TSC_IOHCR_G4_IO2_Pos (13U)
17006#define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos)
17007#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk
17008#define TSC_IOHCR_G4_IO3_Pos (14U)
17009#define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos)
17010#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk
17011#define TSC_IOHCR_G4_IO4_Pos (15U)
17012#define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos)
17013#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk
17014#define TSC_IOHCR_G5_IO1_Pos (16U)
17015#define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos)
17016#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk
17017#define TSC_IOHCR_G5_IO2_Pos (17U)
17018#define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos)
17019#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk
17020#define TSC_IOHCR_G5_IO3_Pos (18U)
17021#define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos)
17022#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk
17023#define TSC_IOHCR_G5_IO4_Pos (19U)
17024#define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos)
17025#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk
17026#define TSC_IOHCR_G6_IO1_Pos (20U)
17027#define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos)
17028#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk
17029#define TSC_IOHCR_G6_IO2_Pos (21U)
17030#define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos)
17031#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk
17032#define TSC_IOHCR_G6_IO3_Pos (22U)
17033#define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos)
17034#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk
17035#define TSC_IOHCR_G6_IO4_Pos (23U)
17036#define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos)
17037#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk
17038#define TSC_IOHCR_G7_IO1_Pos (24U)
17039#define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos)
17040#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk
17041#define TSC_IOHCR_G7_IO2_Pos (25U)
17042#define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos)
17043#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk
17044#define TSC_IOHCR_G7_IO3_Pos (26U)
17045#define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos)
17046#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk
17047#define TSC_IOHCR_G7_IO4_Pos (27U)
17048#define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos)
17049#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk
17050#define TSC_IOHCR_G8_IO1_Pos (28U)
17051#define TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos)
17052#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk
17053#define TSC_IOHCR_G8_IO2_Pos (29U)
17054#define TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos)
17055#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk
17056#define TSC_IOHCR_G8_IO3_Pos (30U)
17057#define TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos)
17058#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk
17059#define TSC_IOHCR_G8_IO4_Pos (31U)
17060#define TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos)
17061#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk
17063/******************* Bit definition for TSC_IOASCR register *****************/
17064#define TSC_IOASCR_G1_IO1_Pos (0U)
17065#define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos)
17066#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk
17067#define TSC_IOASCR_G1_IO2_Pos (1U)
17068#define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos)
17069#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk
17070#define TSC_IOASCR_G1_IO3_Pos (2U)
17071#define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos)
17072#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk
17073#define TSC_IOASCR_G1_IO4_Pos (3U)
17074#define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos)
17075#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk
17076#define TSC_IOASCR_G2_IO1_Pos (4U)
17077#define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos)
17078#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk
17079#define TSC_IOASCR_G2_IO2_Pos (5U)
17080#define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos)
17081#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk
17082#define TSC_IOASCR_G2_IO3_Pos (6U)
17083#define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos)
17084#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk
17085#define TSC_IOASCR_G2_IO4_Pos (7U)
17086#define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos)
17087#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk
17088#define TSC_IOASCR_G3_IO1_Pos (8U)
17089#define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos)
17090#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk
17091#define TSC_IOASCR_G3_IO2_Pos (9U)
17092#define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos)
17093#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk
17094#define TSC_IOASCR_G3_IO3_Pos (10U)
17095#define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos)
17096#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk
17097#define TSC_IOASCR_G3_IO4_Pos (11U)
17098#define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos)
17099#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk
17100#define TSC_IOASCR_G4_IO1_Pos (12U)
17101#define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos)
17102#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk
17103#define TSC_IOASCR_G4_IO2_Pos (13U)
17104#define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos)
17105#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk
17106#define TSC_IOASCR_G4_IO3_Pos (14U)
17107#define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos)
17108#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk
17109#define TSC_IOASCR_G4_IO4_Pos (15U)
17110#define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos)
17111#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk
17112#define TSC_IOASCR_G5_IO1_Pos (16U)
17113#define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos)
17114#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk
17115#define TSC_IOASCR_G5_IO2_Pos (17U)
17116#define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos)
17117#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk
17118#define TSC_IOASCR_G5_IO3_Pos (18U)
17119#define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos)
17120#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk
17121#define TSC_IOASCR_G5_IO4_Pos (19U)
17122#define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos)
17123#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk
17124#define TSC_IOASCR_G6_IO1_Pos (20U)
17125#define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos)
17126#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk
17127#define TSC_IOASCR_G6_IO2_Pos (21U)
17128#define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos)
17129#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk
17130#define TSC_IOASCR_G6_IO3_Pos (22U)
17131#define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos)
17132#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk
17133#define TSC_IOASCR_G6_IO4_Pos (23U)
17134#define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos)
17135#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk
17136#define TSC_IOASCR_G7_IO1_Pos (24U)
17137#define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos)
17138#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk
17139#define TSC_IOASCR_G7_IO2_Pos (25U)
17140#define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos)
17141#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk
17142#define TSC_IOASCR_G7_IO3_Pos (26U)
17143#define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos)
17144#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk
17145#define TSC_IOASCR_G7_IO4_Pos (27U)
17146#define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos)
17147#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk
17148#define TSC_IOASCR_G8_IO1_Pos (28U)
17149#define TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos)
17150#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk
17151#define TSC_IOASCR_G8_IO2_Pos (29U)
17152#define TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos)
17153#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk
17154#define TSC_IOASCR_G8_IO3_Pos (30U)
17155#define TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos)
17156#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk
17157#define TSC_IOASCR_G8_IO4_Pos (31U)
17158#define TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos)
17159#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk
17161/******************* Bit definition for TSC_IOSCR register ******************/
17162#define TSC_IOSCR_G1_IO1_Pos (0U)
17163#define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos)
17164#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk
17165#define TSC_IOSCR_G1_IO2_Pos (1U)
17166#define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos)
17167#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk
17168#define TSC_IOSCR_G1_IO3_Pos (2U)
17169#define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos)
17170#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk
17171#define TSC_IOSCR_G1_IO4_Pos (3U)
17172#define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos)
17173#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk
17174#define TSC_IOSCR_G2_IO1_Pos (4U)
17175#define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos)
17176#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk
17177#define TSC_IOSCR_G2_IO2_Pos (5U)
17178#define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos)
17179#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk
17180#define TSC_IOSCR_G2_IO3_Pos (6U)
17181#define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos)
17182#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk
17183#define TSC_IOSCR_G2_IO4_Pos (7U)
17184#define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos)
17185#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk
17186#define TSC_IOSCR_G3_IO1_Pos (8U)
17187#define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos)
17188#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk
17189#define TSC_IOSCR_G3_IO2_Pos (9U)
17190#define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos)
17191#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk
17192#define TSC_IOSCR_G3_IO3_Pos (10U)
17193#define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos)
17194#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk
17195#define TSC_IOSCR_G3_IO4_Pos (11U)
17196#define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos)
17197#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk
17198#define TSC_IOSCR_G4_IO1_Pos (12U)
17199#define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos)
17200#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk
17201#define TSC_IOSCR_G4_IO2_Pos (13U)
17202#define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos)
17203#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk
17204#define TSC_IOSCR_G4_IO3_Pos (14U)
17205#define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos)
17206#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk
17207#define TSC_IOSCR_G4_IO4_Pos (15U)
17208#define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos)
17209#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk
17210#define TSC_IOSCR_G5_IO1_Pos (16U)
17211#define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos)
17212#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk
17213#define TSC_IOSCR_G5_IO2_Pos (17U)
17214#define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos)
17215#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk
17216#define TSC_IOSCR_G5_IO3_Pos (18U)
17217#define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos)
17218#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk
17219#define TSC_IOSCR_G5_IO4_Pos (19U)
17220#define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos)
17221#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk
17222#define TSC_IOSCR_G6_IO1_Pos (20U)
17223#define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos)
17224#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk
17225#define TSC_IOSCR_G6_IO2_Pos (21U)
17226#define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos)
17227#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk
17228#define TSC_IOSCR_G6_IO3_Pos (22U)
17229#define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos)
17230#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk
17231#define TSC_IOSCR_G6_IO4_Pos (23U)
17232#define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos)
17233#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk
17234#define TSC_IOSCR_G7_IO1_Pos (24U)
17235#define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos)
17236#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk
17237#define TSC_IOSCR_G7_IO2_Pos (25U)
17238#define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos)
17239#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk
17240#define TSC_IOSCR_G7_IO3_Pos (26U)
17241#define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos)
17242#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk
17243#define TSC_IOSCR_G7_IO4_Pos (27U)
17244#define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos)
17245#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk
17246#define TSC_IOSCR_G8_IO1_Pos (28U)
17247#define TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos)
17248#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk
17249#define TSC_IOSCR_G8_IO2_Pos (29U)
17250#define TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos)
17251#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk
17252#define TSC_IOSCR_G8_IO3_Pos (30U)
17253#define TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos)
17254#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk
17255#define TSC_IOSCR_G8_IO4_Pos (31U)
17256#define TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos)
17257#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk
17259/******************* Bit definition for TSC_IOCCR register ******************/
17260#define TSC_IOCCR_G1_IO1_Pos (0U)
17261#define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos)
17262#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk
17263#define TSC_IOCCR_G1_IO2_Pos (1U)
17264#define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos)
17265#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk
17266#define TSC_IOCCR_G1_IO3_Pos (2U)
17267#define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos)
17268#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk
17269#define TSC_IOCCR_G1_IO4_Pos (3U)
17270#define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos)
17271#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk
17272#define TSC_IOCCR_G2_IO1_Pos (4U)
17273#define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos)
17274#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk
17275#define TSC_IOCCR_G2_IO2_Pos (5U)
17276#define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos)
17277#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk
17278#define TSC_IOCCR_G2_IO3_Pos (6U)
17279#define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos)
17280#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk
17281#define TSC_IOCCR_G2_IO4_Pos (7U)
17282#define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos)
17283#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk
17284#define TSC_IOCCR_G3_IO1_Pos (8U)
17285#define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos)
17286#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk
17287#define TSC_IOCCR_G3_IO2_Pos (9U)
17288#define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos)
17289#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk
17290#define TSC_IOCCR_G3_IO3_Pos (10U)
17291#define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos)
17292#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk
17293#define TSC_IOCCR_G3_IO4_Pos (11U)
17294#define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos)
17295#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk
17296#define TSC_IOCCR_G4_IO1_Pos (12U)
17297#define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos)
17298#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk
17299#define TSC_IOCCR_G4_IO2_Pos (13U)
17300#define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos)
17301#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk
17302#define TSC_IOCCR_G4_IO3_Pos (14U)
17303#define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos)
17304#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk
17305#define TSC_IOCCR_G4_IO4_Pos (15U)
17306#define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos)
17307#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk
17308#define TSC_IOCCR_G5_IO1_Pos (16U)
17309#define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos)
17310#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk
17311#define TSC_IOCCR_G5_IO2_Pos (17U)
17312#define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos)
17313#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk
17314#define TSC_IOCCR_G5_IO3_Pos (18U)
17315#define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos)
17316#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk
17317#define TSC_IOCCR_G5_IO4_Pos (19U)
17318#define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos)
17319#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk
17320#define TSC_IOCCR_G6_IO1_Pos (20U)
17321#define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos)
17322#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk
17323#define TSC_IOCCR_G6_IO2_Pos (21U)
17324#define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos)
17325#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk
17326#define TSC_IOCCR_G6_IO3_Pos (22U)
17327#define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos)
17328#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk
17329#define TSC_IOCCR_G6_IO4_Pos (23U)
17330#define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos)
17331#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk
17332#define TSC_IOCCR_G7_IO1_Pos (24U)
17333#define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos)
17334#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk
17335#define TSC_IOCCR_G7_IO2_Pos (25U)
17336#define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos)
17337#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk
17338#define TSC_IOCCR_G7_IO3_Pos (26U)
17339#define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos)
17340#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk
17341#define TSC_IOCCR_G7_IO4_Pos (27U)
17342#define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos)
17343#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk
17344#define TSC_IOCCR_G8_IO1_Pos (28U)
17345#define TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos)
17346#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk
17347#define TSC_IOCCR_G8_IO2_Pos (29U)
17348#define TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos)
17349#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk
17350#define TSC_IOCCR_G8_IO3_Pos (30U)
17351#define TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos)
17352#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk
17353#define TSC_IOCCR_G8_IO4_Pos (31U)
17354#define TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos)
17355#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk
17357/******************* Bit definition for TSC_IOGCSR register *****************/
17358#define TSC_IOGCSR_G1E_Pos (0U)
17359#define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos)
17360#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk
17361#define TSC_IOGCSR_G2E_Pos (1U)
17362#define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos)
17363#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk
17364#define TSC_IOGCSR_G3E_Pos (2U)
17365#define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos)
17366#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk
17367#define TSC_IOGCSR_G4E_Pos (3U)
17368#define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos)
17369#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk
17370#define TSC_IOGCSR_G5E_Pos (4U)
17371#define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos)
17372#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk
17373#define TSC_IOGCSR_G6E_Pos (5U)
17374#define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos)
17375#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk
17376#define TSC_IOGCSR_G7E_Pos (6U)
17377#define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos)
17378#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk
17379#define TSC_IOGCSR_G8E_Pos (7U)
17380#define TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos)
17381#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk
17382#define TSC_IOGCSR_G1S_Pos (16U)
17383#define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos)
17384#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk
17385#define TSC_IOGCSR_G2S_Pos (17U)
17386#define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos)
17387#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk
17388#define TSC_IOGCSR_G3S_Pos (18U)
17389#define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos)
17390#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk
17391#define TSC_IOGCSR_G4S_Pos (19U)
17392#define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos)
17393#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk
17394#define TSC_IOGCSR_G5S_Pos (20U)
17395#define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos)
17396#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk
17397#define TSC_IOGCSR_G6S_Pos (21U)
17398#define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos)
17399#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk
17400#define TSC_IOGCSR_G7S_Pos (22U)
17401#define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos)
17402#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk
17403#define TSC_IOGCSR_G8S_Pos (23U)
17404#define TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos)
17405#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk
17407/******************* Bit definition for TSC_IOGXCR register *****************/
17408#define TSC_IOGXCR_CNT_Pos (0U)
17409#define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos)
17410#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk
17412/******************************************************************************/
17413/* */
17414/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
17415/* */
17416/******************************************************************************/
17417
17418/*
17419* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
17420*/
17421#define USART_TCBGT_SUPPORT
17422
17423/****************** Bit definition for USART_CR1 register *******************/
17424#define USART_CR1_UE_Pos (0U)
17425#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
17426#define USART_CR1_UE USART_CR1_UE_Msk
17427#define USART_CR1_UESM_Pos (1U)
17428#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)
17429#define USART_CR1_UESM USART_CR1_UESM_Msk
17430#define USART_CR1_RE_Pos (2U)
17431#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
17432#define USART_CR1_RE USART_CR1_RE_Msk
17433#define USART_CR1_TE_Pos (3U)
17434#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
17435#define USART_CR1_TE USART_CR1_TE_Msk
17436#define USART_CR1_IDLEIE_Pos (4U)
17437#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
17438#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
17439#define USART_CR1_RXNEIE_Pos (5U)
17440#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
17441#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
17442#define USART_CR1_TCIE_Pos (6U)
17443#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
17444#define USART_CR1_TCIE USART_CR1_TCIE_Msk
17445#define USART_CR1_TXEIE_Pos (7U)
17446#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
17447#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
17448#define USART_CR1_PEIE_Pos (8U)
17449#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
17450#define USART_CR1_PEIE USART_CR1_PEIE_Msk
17451#define USART_CR1_PS_Pos (9U)
17452#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
17453#define USART_CR1_PS USART_CR1_PS_Msk
17454#define USART_CR1_PCE_Pos (10U)
17455#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
17456#define USART_CR1_PCE USART_CR1_PCE_Msk
17457#define USART_CR1_WAKE_Pos (11U)
17458#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
17459#define USART_CR1_WAKE USART_CR1_WAKE_Msk
17460#define USART_CR1_M_Pos (12U)
17461#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
17462#define USART_CR1_M USART_CR1_M_Msk
17463#define USART_CR1_M0_Pos (12U)
17464#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)
17465#define USART_CR1_M0 USART_CR1_M0_Msk
17466#define USART_CR1_MME_Pos (13U)
17467#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
17468#define USART_CR1_MME USART_CR1_MME_Msk
17469#define USART_CR1_CMIE_Pos (14U)
17470#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
17471#define USART_CR1_CMIE USART_CR1_CMIE_Msk
17472#define USART_CR1_OVER8_Pos (15U)
17473#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
17474#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
17475#define USART_CR1_DEDT_Pos (16U)
17476#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
17477#define USART_CR1_DEDT USART_CR1_DEDT_Msk
17478#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
17479#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
17480#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
17481#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
17482#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
17483#define USART_CR1_DEAT_Pos (21U)
17484#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
17485#define USART_CR1_DEAT USART_CR1_DEAT_Msk
17486#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
17487#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
17488#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
17489#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
17490#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
17491#define USART_CR1_RTOIE_Pos (26U)
17492#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
17493#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
17494#define USART_CR1_EOBIE_Pos (27U)
17495#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
17496#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
17497#define USART_CR1_M1_Pos (28U)
17498#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)
17499#define USART_CR1_M1 USART_CR1_M1_Msk
17501/****************** Bit definition for USART_CR2 register *******************/
17502#define USART_CR2_ADDM7_Pos (4U)
17503#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
17504#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
17505#define USART_CR2_LBDL_Pos (5U)
17506#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
17507#define USART_CR2_LBDL USART_CR2_LBDL_Msk
17508#define USART_CR2_LBDIE_Pos (6U)
17509#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
17510#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
17511#define USART_CR2_LBCL_Pos (8U)
17512#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
17513#define USART_CR2_LBCL USART_CR2_LBCL_Msk
17514#define USART_CR2_CPHA_Pos (9U)
17515#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
17516#define USART_CR2_CPHA USART_CR2_CPHA_Msk
17517#define USART_CR2_CPOL_Pos (10U)
17518#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
17519#define USART_CR2_CPOL USART_CR2_CPOL_Msk
17520#define USART_CR2_CLKEN_Pos (11U)
17521#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
17522#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
17523#define USART_CR2_STOP_Pos (12U)
17524#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
17525#define USART_CR2_STOP USART_CR2_STOP_Msk
17526#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
17527#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
17528#define USART_CR2_LINEN_Pos (14U)
17529#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
17530#define USART_CR2_LINEN USART_CR2_LINEN_Msk
17531#define USART_CR2_SWAP_Pos (15U)
17532#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
17533#define USART_CR2_SWAP USART_CR2_SWAP_Msk
17534#define USART_CR2_RXINV_Pos (16U)
17535#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
17536#define USART_CR2_RXINV USART_CR2_RXINV_Msk
17537#define USART_CR2_TXINV_Pos (17U)
17538#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
17539#define USART_CR2_TXINV USART_CR2_TXINV_Msk
17540#define USART_CR2_DATAINV_Pos (18U)
17541#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
17542#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
17543#define USART_CR2_MSBFIRST_Pos (19U)
17544#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
17545#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
17546#define USART_CR2_ABREN_Pos (20U)
17547#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
17548#define USART_CR2_ABREN USART_CR2_ABREN_Msk
17549#define USART_CR2_ABRMODE_Pos (21U)
17550#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
17551#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
17552#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
17553#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
17554#define USART_CR2_RTOEN_Pos (23U)
17555#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
17556#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
17557#define USART_CR2_ADD_Pos (24U)
17558#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
17559#define USART_CR2_ADD USART_CR2_ADD_Msk
17561/****************** Bit definition for USART_CR3 register *******************/
17562#define USART_CR3_EIE_Pos (0U)
17563#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
17564#define USART_CR3_EIE USART_CR3_EIE_Msk
17565#define USART_CR3_IREN_Pos (1U)
17566#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
17567#define USART_CR3_IREN USART_CR3_IREN_Msk
17568#define USART_CR3_IRLP_Pos (2U)
17569#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
17570#define USART_CR3_IRLP USART_CR3_IRLP_Msk
17571#define USART_CR3_HDSEL_Pos (3U)
17572#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
17573#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
17574#define USART_CR3_NACK_Pos (4U)
17575#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
17576#define USART_CR3_NACK USART_CR3_NACK_Msk
17577#define USART_CR3_SCEN_Pos (5U)
17578#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
17579#define USART_CR3_SCEN USART_CR3_SCEN_Msk
17580#define USART_CR3_DMAR_Pos (6U)
17581#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
17582#define USART_CR3_DMAR USART_CR3_DMAR_Msk
17583#define USART_CR3_DMAT_Pos (7U)
17584#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
17585#define USART_CR3_DMAT USART_CR3_DMAT_Msk
17586#define USART_CR3_RTSE_Pos (8U)
17587#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
17588#define USART_CR3_RTSE USART_CR3_RTSE_Msk
17589#define USART_CR3_CTSE_Pos (9U)
17590#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
17591#define USART_CR3_CTSE USART_CR3_CTSE_Msk
17592#define USART_CR3_CTSIE_Pos (10U)
17593#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
17594#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
17595#define USART_CR3_ONEBIT_Pos (11U)
17596#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
17597#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
17598#define USART_CR3_OVRDIS_Pos (12U)
17599#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
17600#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
17601#define USART_CR3_DDRE_Pos (13U)
17602#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
17603#define USART_CR3_DDRE USART_CR3_DDRE_Msk
17604#define USART_CR3_DEM_Pos (14U)
17605#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
17606#define USART_CR3_DEM USART_CR3_DEM_Msk
17607#define USART_CR3_DEP_Pos (15U)
17608#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
17609#define USART_CR3_DEP USART_CR3_DEP_Msk
17610#define USART_CR3_SCARCNT_Pos (17U)
17611#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
17612#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
17613#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
17614#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
17615#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
17616#define USART_CR3_WUS_Pos (20U)
17617#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)
17618#define USART_CR3_WUS USART_CR3_WUS_Msk
17619#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)
17620#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)
17621#define USART_CR3_WUFIE_Pos (22U)
17622#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)
17623#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk
17624#define USART_CR3_UCESM_Pos (23U)
17625#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos)
17626#define USART_CR3_UCESM USART_CR3_UCESM_Msk
17627#define USART_CR3_TCBGTIE_Pos (24U)
17628#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos)
17629#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk
17631/****************** Bit definition for USART_BRR register *******************/
17632#define USART_BRR_DIV_FRACTION_Pos (0U)
17633#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
17634#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
17635#define USART_BRR_DIV_MANTISSA_Pos (4U)
17636#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
17637#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
17639/****************** Bit definition for USART_GTPR register ******************/
17640#define USART_GTPR_PSC_Pos (0U)
17641#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
17642#define USART_GTPR_PSC USART_GTPR_PSC_Msk
17643#define USART_GTPR_GT_Pos (8U)
17644#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
17645#define USART_GTPR_GT USART_GTPR_GT_Msk
17647/******************* Bit definition for USART_RTOR register *****************/
17648#define USART_RTOR_RTO_Pos (0U)
17649#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
17650#define USART_RTOR_RTO USART_RTOR_RTO_Msk
17651#define USART_RTOR_BLEN_Pos (24U)
17652#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
17653#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
17655/******************* Bit definition for USART_RQR register ******************/
17656#define USART_RQR_ABRRQ_Pos (0U)
17657#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
17658#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
17659#define USART_RQR_SBKRQ_Pos (1U)
17660#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
17661#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
17662#define USART_RQR_MMRQ_Pos (2U)
17663#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
17664#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
17665#define USART_RQR_RXFRQ_Pos (3U)
17666#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
17667#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
17668#define USART_RQR_TXFRQ_Pos (4U)
17669#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
17670#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
17672/******************* Bit definition for USART_ISR register ******************/
17673#define USART_ISR_PE_Pos (0U)
17674#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
17675#define USART_ISR_PE USART_ISR_PE_Msk
17676#define USART_ISR_FE_Pos (1U)
17677#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
17678#define USART_ISR_FE USART_ISR_FE_Msk
17679#define USART_ISR_NE_Pos (2U)
17680#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
17681#define USART_ISR_NE USART_ISR_NE_Msk
17682#define USART_ISR_ORE_Pos (3U)
17683#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
17684#define USART_ISR_ORE USART_ISR_ORE_Msk
17685#define USART_ISR_IDLE_Pos (4U)
17686#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
17687#define USART_ISR_IDLE USART_ISR_IDLE_Msk
17688#define USART_ISR_RXNE_Pos (5U)
17689#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)
17690#define USART_ISR_RXNE USART_ISR_RXNE_Msk
17691#define USART_ISR_TC_Pos (6U)
17692#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
17693#define USART_ISR_TC USART_ISR_TC_Msk
17694#define USART_ISR_TXE_Pos (7U)
17695#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)
17696#define USART_ISR_TXE USART_ISR_TXE_Msk
17697#define USART_ISR_LBDF_Pos (8U)
17698#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
17699#define USART_ISR_LBDF USART_ISR_LBDF_Msk
17700#define USART_ISR_CTSIF_Pos (9U)
17701#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
17702#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
17703#define USART_ISR_CTS_Pos (10U)
17704#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
17705#define USART_ISR_CTS USART_ISR_CTS_Msk
17706#define USART_ISR_RTOF_Pos (11U)
17707#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
17708#define USART_ISR_RTOF USART_ISR_RTOF_Msk
17709#define USART_ISR_EOBF_Pos (12U)
17710#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
17711#define USART_ISR_EOBF USART_ISR_EOBF_Msk
17712#define USART_ISR_ABRE_Pos (14U)
17713#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
17714#define USART_ISR_ABRE USART_ISR_ABRE_Msk
17715#define USART_ISR_ABRF_Pos (15U)
17716#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
17717#define USART_ISR_ABRF USART_ISR_ABRF_Msk
17718#define USART_ISR_BUSY_Pos (16U)
17719#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
17720#define USART_ISR_BUSY USART_ISR_BUSY_Msk
17721#define USART_ISR_CMF_Pos (17U)
17722#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
17723#define USART_ISR_CMF USART_ISR_CMF_Msk
17724#define USART_ISR_SBKF_Pos (18U)
17725#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
17726#define USART_ISR_SBKF USART_ISR_SBKF_Msk
17727#define USART_ISR_RWU_Pos (19U)
17728#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
17729#define USART_ISR_RWU USART_ISR_RWU_Msk
17730#define USART_ISR_WUF_Pos (20U)
17731#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)
17732#define USART_ISR_WUF USART_ISR_WUF_Msk
17733#define USART_ISR_TEACK_Pos (21U)
17734#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
17735#define USART_ISR_TEACK USART_ISR_TEACK_Msk
17736#define USART_ISR_REACK_Pos (22U)
17737#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)
17738#define USART_ISR_REACK USART_ISR_REACK_Msk
17739#define USART_ISR_TCBGT_Pos (25U)
17740#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos)
17741#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk
17743/******************* Bit definition for USART_ICR register ******************/
17744#define USART_ICR_PECF_Pos (0U)
17745#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
17746#define USART_ICR_PECF USART_ICR_PECF_Msk
17747#define USART_ICR_FECF_Pos (1U)
17748#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
17749#define USART_ICR_FECF USART_ICR_FECF_Msk
17750#define USART_ICR_NECF_Pos (2U)
17751#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos)
17752#define USART_ICR_NECF USART_ICR_NECF_Msk
17753#define USART_ICR_ORECF_Pos (3U)
17754#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
17755#define USART_ICR_ORECF USART_ICR_ORECF_Msk
17756#define USART_ICR_IDLECF_Pos (4U)
17757#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
17758#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
17759#define USART_ICR_TCCF_Pos (6U)
17760#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
17761#define USART_ICR_TCCF USART_ICR_TCCF_Msk
17762#define USART_ICR_TCBGTCF_Pos (7U)
17763#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos)
17764#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk
17765#define USART_ICR_LBDCF_Pos (8U)
17766#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
17767#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk
17768#define USART_ICR_CTSCF_Pos (9U)
17769#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
17770#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
17771#define USART_ICR_RTOCF_Pos (11U)
17772#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
17773#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
17774#define USART_ICR_EOBCF_Pos (12U)
17775#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
17776#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk
17777#define USART_ICR_CMCF_Pos (17U)
17778#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
17779#define USART_ICR_CMCF USART_ICR_CMCF_Msk
17780#define USART_ICR_WUCF_Pos (20U)
17781#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)
17782#define USART_ICR_WUCF USART_ICR_WUCF_Msk
17784/* Legacy defines */
17785#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
17786#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
17787#define USART_ICR_NCF USART_ICR_NECF
17788
17789/******************* Bit definition for USART_RDR register ******************/
17790#define USART_RDR_RDR_Pos (0U)
17791#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
17792#define USART_RDR_RDR USART_RDR_RDR_Msk
17794/******************* Bit definition for USART_TDR register ******************/
17795#define USART_TDR_TDR_Pos (0U)
17796#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
17797#define USART_TDR_TDR USART_TDR_TDR_Msk
17799/******************************************************************************/
17800/* */
17801/* Single Wire Protocol Master Interface (SWPMI) */
17802/* */
17803/******************************************************************************/
17804
17805/******************* Bit definition for SWPMI_CR register ********************/
17806#define SWPMI_CR_RXDMA_Pos (0U)
17807#define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos)
17808#define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk
17809#define SWPMI_CR_TXDMA_Pos (1U)
17810#define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos)
17811#define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk
17812#define SWPMI_CR_RXMODE_Pos (2U)
17813#define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos)
17814#define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk
17815#define SWPMI_CR_TXMODE_Pos (3U)
17816#define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos)
17817#define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk
17818#define SWPMI_CR_LPBK_Pos (4U)
17819#define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos)
17820#define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk
17821#define SWPMI_CR_SWPACT_Pos (5U)
17822#define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos)
17823#define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk
17824#define SWPMI_CR_DEACT_Pos (10U)
17825#define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos)
17826#define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk
17828/******************* Bit definition for SWPMI_BRR register ********************/
17829#define SWPMI_BRR_BR_Pos (0U)
17830#define SWPMI_BRR_BR_Msk (0x3FUL << SWPMI_BRR_BR_Pos)
17831#define SWPMI_BRR_BR SWPMI_BRR_BR_Msk
17833/******************* Bit definition for SWPMI_ISR register ********************/
17834#define SWPMI_ISR_RXBFF_Pos (0U)
17835#define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos)
17836#define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk
17837#define SWPMI_ISR_TXBEF_Pos (1U)
17838#define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos)
17839#define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk
17840#define SWPMI_ISR_RXBERF_Pos (2U)
17841#define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos)
17842#define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk
17843#define SWPMI_ISR_RXOVRF_Pos (3U)
17844#define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos)
17845#define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk
17846#define SWPMI_ISR_TXUNRF_Pos (4U)
17847#define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos)
17848#define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk
17849#define SWPMI_ISR_RXNE_Pos (5U)
17850#define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos)
17851#define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk
17852#define SWPMI_ISR_TXE_Pos (6U)
17853#define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos)
17854#define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk
17855#define SWPMI_ISR_TCF_Pos (7U)
17856#define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos)
17857#define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk
17858#define SWPMI_ISR_SRF_Pos (8U)
17859#define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos)
17860#define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk
17861#define SWPMI_ISR_SUSP_Pos (9U)
17862#define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos)
17863#define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk
17864#define SWPMI_ISR_DEACTF_Pos (10U)
17865#define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos)
17866#define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk
17868/******************* Bit definition for SWPMI_ICR register ********************/
17869#define SWPMI_ICR_CRXBFF_Pos (0U)
17870#define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos)
17871#define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk
17872#define SWPMI_ICR_CTXBEF_Pos (1U)
17873#define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos)
17874#define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk
17875#define SWPMI_ICR_CRXBERF_Pos (2U)
17876#define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos)
17877#define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk
17878#define SWPMI_ICR_CRXOVRF_Pos (3U)
17879#define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos)
17880#define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk
17881#define SWPMI_ICR_CTXUNRF_Pos (4U)
17882#define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos)
17883#define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk
17884#define SWPMI_ICR_CTCF_Pos (7U)
17885#define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos)
17886#define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk
17887#define SWPMI_ICR_CSRF_Pos (8U)
17888#define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos)
17889#define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk
17891/******************* Bit definition for SWPMI_IER register ********************/
17892#define SWPMI_IER_SRIE_Pos (8U)
17893#define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos)
17894#define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk
17895#define SWPMI_IER_TCIE_Pos (7U)
17896#define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos)
17897#define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk
17898#define SWPMI_IER_TIE_Pos (6U)
17899#define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos)
17900#define SWPMI_IER_TIE SWPMI_IER_TIE_Msk
17901#define SWPMI_IER_RIE_Pos (5U)
17902#define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos)
17903#define SWPMI_IER_RIE SWPMI_IER_RIE_Msk
17904#define SWPMI_IER_TXUNRIE_Pos (4U)
17905#define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos)
17906#define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk
17907#define SWPMI_IER_RXOVRIE_Pos (3U)
17908#define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos)
17909#define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk
17910#define SWPMI_IER_RXBERIE_Pos (2U)
17911#define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos)
17912#define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk
17913#define SWPMI_IER_TXBEIE_Pos (1U)
17914#define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos)
17915#define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk
17916#define SWPMI_IER_RXBFIE_Pos (0U)
17917#define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos)
17918#define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk
17920/******************* Bit definition for SWPMI_RFL register ********************/
17921#define SWPMI_RFL_RFL_Pos (0U)
17922#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos)
17923#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk
17924#define SWPMI_RFL_RFL_0_1_Pos (0U)
17925#define SWPMI_RFL_RFL_0_1_Msk (0x3UL << SWPMI_RFL_RFL_0_1_Pos)
17926#define SWPMI_RFL_RFL_0_1 SWPMI_RFL_RFL_0_1_Msk
17928/******************* Bit definition for SWPMI_TDR register ********************/
17929#define SWPMI_TDR_TD_Pos (0U)
17930#define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)
17931#define SWPMI_TDR_TD SWPMI_TDR_TD_Msk
17933/******************* Bit definition for SWPMI_RDR register ********************/
17934#define SWPMI_RDR_RD_Pos (0U)
17935#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)
17936#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk
17938/******************* Bit definition for SWPMI_OR register ********************/
17939#define SWPMI_OR_TBYP_Pos (0U)
17940#define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos)
17941#define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk
17942#define SWPMI_OR_CLASS_Pos (1U)
17943#define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos)
17944#define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk
17946/******************************************************************************/
17947/* */
17948/* VREFBUF */
17949/* */
17950/******************************************************************************/
17951/******************* Bit definition for VREFBUF_CSR register ****************/
17952#define VREFBUF_CSR_ENVR_Pos (0U)
17953#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos)
17954#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk
17955#define VREFBUF_CSR_HIZ_Pos (1U)
17956#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos)
17957#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk
17958#define VREFBUF_CSR_VRS_Pos (2U)
17959#define VREFBUF_CSR_VRS_Msk (0x1UL << VREFBUF_CSR_VRS_Pos)
17960#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk
17961#define VREFBUF_CSR_VRR_Pos (3U)
17962#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos)
17963#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk
17965/******************* Bit definition for VREFBUF_CCR register ******************/
17966#define VREFBUF_CCR_TRIM_Pos (0U)
17967#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos)
17968#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk
17970/******************************************************************************/
17971/* */
17972/* Window WATCHDOG */
17973/* */
17974/******************************************************************************/
17975/******************* Bit definition for WWDG_CR register ********************/
17976#define WWDG_CR_T_Pos (0U)
17977#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
17978#define WWDG_CR_T WWDG_CR_T_Msk
17979#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
17980#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
17981#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
17982#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
17983#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
17984#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
17985#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
17987#define WWDG_CR_WDGA_Pos (7U)
17988#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
17989#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
17991/******************* Bit definition for WWDG_CFR register *******************/
17992#define WWDG_CFR_W_Pos (0U)
17993#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
17994#define WWDG_CFR_W WWDG_CFR_W_Msk
17995#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
17996#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
17997#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
17998#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
17999#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
18000#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
18001#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
18003#define WWDG_CFR_WDGTB_Pos (7U)
18004#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
18005#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
18006#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
18007#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
18009#define WWDG_CFR_EWI_Pos (9U)
18010#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
18011#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
18013/******************* Bit definition for WWDG_SR register ********************/
18014#define WWDG_SR_EWIF_Pos (0U)
18015#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
18016#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
18019/******************************************************************************/
18020/* */
18021/* Debug MCU */
18022/* */
18023/******************************************************************************/
18024/******************** Bit definition for DBGMCU_IDCODE register *************/
18025#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
18026#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
18027#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
18028#define DBGMCU_IDCODE_REV_ID_Pos (16U)
18029#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
18030#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
18031
18032/******************** Bit definition for DBGMCU_CR register *****************/
18033#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
18034#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
18035#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
18036#define DBGMCU_CR_DBG_STOP_Pos (1U)
18037#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
18038#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
18039#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
18040#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
18041#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
18042#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
18043#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
18044#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
18045
18046#define DBGMCU_CR_TRACE_MODE_Pos (6U)
18047#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
18048#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
18049#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
18050#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
18052/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
18053#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
18054#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)
18055#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
18056#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
18057#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)
18058#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
18059#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
18060#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)
18061#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
18062#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
18063#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)
18064#define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
18065#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
18066#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)
18067#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
18068#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
18069#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)
18070#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
18071#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
18072#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)
18073#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
18074#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
18075#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)
18076#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
18077#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
18078#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)
18079#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
18080#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
18081#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)
18082#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
18083#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
18084#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)
18085#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
18086#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)
18087#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)
18088#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
18089#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U)
18090#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos)
18091#define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
18092#define DBGMCU_APB1FZR1_DBG_CAN2_STOP_Pos (26U)
18093#define DBGMCU_APB1FZR1_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_CAN2_STOP_Pos)
18094#define DBGMCU_APB1FZR1_DBG_CAN2_STOP DBGMCU_APB1FZR1_DBG_CAN2_STOP_Msk
18095#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
18096#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)
18097#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
18098
18099/******************** Bit definition for DBGMCU_APB1FZR2 register **********/
18100#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos (1U)
18101#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos)
18102#define DBGMCU_APB1FZR2_DBG_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk
18103#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
18104#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos)
18105#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
18106
18107/******************** Bit definition for DBGMCU_APB2FZ register ************/
18108#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
18109#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)
18110#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
18111#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
18112#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)
18113#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
18114#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
18115#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)
18116#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
18117#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
18118#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)
18119#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
18120#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
18121#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)
18122#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
18123
18124/******************************************************************************/
18125/* */
18126/* USB_OTG */
18127/* */
18128/******************************************************************************/
18129/******************** Bit definition for USB_OTG_GOTGCTL register ********************/
18130#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
18131#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
18132#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
18133#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
18134#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
18135#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
18136#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
18137#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
18138#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
18139#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
18140#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
18141#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
18142#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
18143#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
18144#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
18145#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
18146#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
18147#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
18148#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
18149#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
18150#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
18151#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
18152#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
18153#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
18154#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
18155#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
18156#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
18158/******************** Bit definition for USB_OTG_GOTGINT register ********************/
18159#define USB_OTG_GOTGINT_SEDET_Pos (2U)
18160#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
18161#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
18162#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
18163#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
18164#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
18165#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
18166#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
18167#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
18168#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
18169#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
18170#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
18171#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
18172#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
18173#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
18174#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
18175#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
18176#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
18178/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
18179#define USB_OTG_GAHBCFG_GINT_Pos (0U)
18180#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
18181#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
18182#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
18183#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18184#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
18185#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18186#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18187#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18188#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18189#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
18190#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
18191#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
18192#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
18193#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
18194#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
18195#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
18196#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
18197#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
18199/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
18200#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
18201#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
18202#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
18203#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
18204#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
18205#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
18206#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
18207#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
18208#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
18209#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
18210#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
18211#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
18212#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
18213#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
18214#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
18215#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
18216#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
18217#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
18218#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
18219#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
18220#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
18221#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
18222#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
18223#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
18224#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
18225#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
18226#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
18227#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
18228#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
18229#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
18230#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
18231#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
18232#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
18233#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
18234#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
18235#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
18236#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
18237#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
18238#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
18239#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
18240#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
18241#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
18242#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
18243#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
18244#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
18245#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
18246#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
18247#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
18248#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
18249#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
18250#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
18251#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
18252#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
18253#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
18254#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
18255#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
18256#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
18257#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
18258#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
18259#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
18260#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
18262/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
18263#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
18264#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
18265#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
18266#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
18267#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
18268#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
18269#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
18270#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
18271#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
18272#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
18273#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
18274#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
18275#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
18276#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
18277#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
18278#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
18279#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18280#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
18281#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18282#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18283#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18284#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18285#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18286#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
18287#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
18288#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
18289#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
18290#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
18291#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
18293/******************** Bit definition for USB_OTG_GINTSTS register ********************/
18294#define USB_OTG_GINTSTS_CMOD_Pos (0U)
18295#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
18296#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
18297#define USB_OTG_GINTSTS_MMIS_Pos (1U)
18298#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
18299#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
18300#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
18301#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
18302#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
18303#define USB_OTG_GINTSTS_SOF_Pos (3U)
18304#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
18305#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
18306#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
18307#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
18308#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
18309#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
18310#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
18311#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
18312#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
18313#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
18314#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
18315#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
18316#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
18317#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
18318#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
18319#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
18320#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
18321#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
18322#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
18323#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
18324#define USB_OTG_GINTSTS_USBRST_Pos (12U)
18325#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
18326#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
18327#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
18328#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
18329#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
18330#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
18331#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
18332#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
18333#define USB_OTG_GINTSTS_EOPF_Pos (15U)
18334#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
18335#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
18336#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
18337#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
18338#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
18339#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
18340#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
18341#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
18342#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
18343#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
18344#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
18345#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
18346#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
18347#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
18348#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
18349#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
18350#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
18351#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
18352#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
18353#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
18354#define USB_OTG_GINTSTS_HCINT_Pos (25U)
18355#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
18356#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
18357#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
18358#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
18359#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
18360#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
18361#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
18362#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
18363#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
18364#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
18365#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
18366#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
18367#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
18368#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
18369#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
18370#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
18371#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
18372#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
18373#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
18374#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
18376/******************** Bit definition for USB_OTG_GINTMSK register ********************/
18377#define USB_OTG_GINTMSK_MMISM_Pos (1U)
18378#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
18379#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
18380#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
18381#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
18382#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
18383#define USB_OTG_GINTMSK_SOFM_Pos (3U)
18384#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
18385#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
18386#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
18387#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
18388#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
18389#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
18390#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
18391#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
18392#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
18393#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
18394#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
18395#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
18396#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
18397#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
18398#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
18399#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
18400#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
18401#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
18402#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
18403#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
18404#define USB_OTG_GINTMSK_USBRST_Pos (12U)
18405#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
18406#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
18407#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
18408#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
18409#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
18410#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
18411#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
18412#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
18413#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
18414#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
18415#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
18416#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
18417#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
18418#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
18419#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
18420#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
18421#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
18422#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
18423#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
18424#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
18425#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
18426#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
18427#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
18428#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
18429#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
18430#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
18431#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
18432#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
18433#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
18434#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
18435#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
18436#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
18437#define USB_OTG_GINTMSK_HCIM_Pos (25U)
18438#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
18439#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
18440#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
18441#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
18442#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
18443#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
18444#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
18445#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
18446#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
18447#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
18448#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
18449#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
18450#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
18451#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
18452#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
18453#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
18454#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
18455#define USB_OTG_GINTMSK_WUIM_Pos (31U)
18456#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
18457#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
18459/******************** Bit definition for USB_OTG_GRXSTSR/GRXSTSP registers ***********/
18460/* Host mode */
18461#define USB_OTG_CHNUM_Pos (0U)
18462#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
18463#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
18464#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
18465#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
18466#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
18467#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
18468/* Device mode */
18469#define USB_OTG_EPNUM_Pos (0U)
18470#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
18471#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
18472#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
18473#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
18474#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
18475#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
18476#define USB_OTG_FRMNUM_Pos (21U)
18477#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
18478#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
18479#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
18480#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
18481#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
18482#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
18483/* Host/Device mode */
18484#define USB_OTG_BCNT_Pos (4U)
18485#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
18486#define USB_OTG_BCNT USB_OTG_BCNT_Msk
18487#define USB_OTG_DPID_Pos (15U)
18488#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
18489#define USB_OTG_DPID USB_OTG_DPID_Msk
18490#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
18491#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
18492#define USB_OTG_PKTSTS_Pos (17U)
18493#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
18494#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
18495#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
18496#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
18497#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
18498#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
18500/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
18501#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
18502#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
18503#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
18504#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
18505#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
18506#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
18507#define USB_OTG_GRXSTSP_DPID_Pos (15U)
18508#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
18509#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
18510#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
18511#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
18512#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
18514/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
18515#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
18516#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
18517#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
18519/******************** Bit definition for USB_OTG_HNPTXFSIZ/DIEPTXF0 register *********/
18520#define USB_OTG_NPTXFSA_Pos (0U)
18521#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
18522#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
18523#define USB_OTG_NPTXFD_Pos (16U)
18524#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
18525#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
18526#define USB_OTG_TX0FSA_Pos (0U)
18527#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
18528#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
18529#define USB_OTG_TX0FD_Pos (16U)
18530#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
18531#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
18533/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
18534#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
18535#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
18536#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
18537#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
18538#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
18539#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
18540#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
18541#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
18542#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
18543#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
18544#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
18545#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
18546#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
18547#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
18549#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
18550#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
18551#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
18552#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
18553#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
18554#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
18555#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
18556#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
18557#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
18558#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
18560/******************** Bit definition for USB_OTG_GCCFG register ********************/
18561#define USB_OTG_GCCFG_DCDET_Pos (0U)
18562#define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos)
18563#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk
18564#define USB_OTG_GCCFG_PDET_Pos (1U)
18565#define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos)
18566#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk
18567#define USB_OTG_GCCFG_SDET_Pos (2U)
18568#define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos)
18569#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk
18570#define USB_OTG_GCCFG_PS2DET_Pos (3U)
18571#define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos)
18572#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk
18573#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
18574#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
18575#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
18576#define USB_OTG_GCCFG_BCDEN_Pos (17U)
18577#define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos)
18578#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk
18579#define USB_OTG_GCCFG_DCDEN_Pos (18U)
18580#define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos)
18581#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk
18582#define USB_OTG_GCCFG_PDEN_Pos (19U)
18583#define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos)
18584#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk
18585#define USB_OTG_GCCFG_SDEN_Pos (20U)
18586#define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos)
18587#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk
18588#define USB_OTG_GCCFG_VBDEN_Pos (21U)
18589#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
18590#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
18592/******************** Bit definition for USB_OTG_CID register ********************/
18593#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
18594#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
18595#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
18597/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
18598#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
18599#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
18600#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */
18601#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
18602#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
18603#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */
18604#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
18605#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
18606#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */
18607#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
18608#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
18609#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */
18610#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
18611#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
18612#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */
18613#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
18614#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
18615#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */
18616#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
18617#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
18618#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */
18619#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
18620#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
18621#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */
18622#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
18623#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
18624#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */
18625#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
18626#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
18627#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */
18628#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
18629#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
18630#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */
18631#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
18632#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
18633#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */
18634#define USB_OTG_GLPMCFG_BESL_Pos (2U)
18635#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
18636#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */
18637#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
18638#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
18639#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/
18640#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
18641#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
18642#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */
18643
18644/* Legacy defines */
18645#define USB_OTG_GLPMCFG_L1ResumeOK_Pos USB_OTG_GLPMCFG_L1RSMOK_Pos
18646#define USB_OTG_GLPMCFG_L1ResumeOK_Msk USB_OTG_GLPMCFG_L1RSMOK_Msk
18647#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK
18648
18649/******************** Bit definition for USB_OTG_GPWRDN register **********************/
18650#define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U)
18651#define USB_OTG_GPWRDN_DISABLEVBUS_Msk (0x1UL << USB_OTG_GPWRDN_DISABLEVBUS_Pos)
18652#define USB_OTG_GPWRDN_DISABLEVBUS USB_OTG_GPWRDN_DISABLEVBUS_Msk
18654/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
18655#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
18656#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
18657#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
18658#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
18659#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
18660#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
18662/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
18663#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
18664#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
18665#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
18666#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
18667#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
18668#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
18670/******************** Bit definition for USB_OTG_HCFG register ********************/
18671#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
18672#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
18673#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
18674#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
18675#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
18676#define USB_OTG_HCFG_FSLSS_Pos (2U)
18677#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
18678#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
18680/******************** Bit definition for USB_OTG_HFIR register ********************/
18681#define USB_OTG_HFIR_FRIVL_Pos (0U)
18682#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
18683#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
18685/******************** Bit definition for USB_OTG_HFNUM register ********************/
18686#define USB_OTG_HFNUM_FRNUM_Pos (0U)
18687#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
18688#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
18689#define USB_OTG_HFNUM_FTREM_Pos (16U)
18690#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
18691#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
18693/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
18694#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
18695#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
18696#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
18697#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
18698#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18699#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
18700#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18701#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18702#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18703#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18704#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18705#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18706#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18707#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18709#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
18710#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18711#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
18712#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18713#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18714#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18715#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18716#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18717#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18718#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18719#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18721/******************** Bit definition for USB_OTG_HAINT register ********************/
18722#define USB_OTG_HAINT_HAINT_Pos (0U)
18723#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
18724#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
18726/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
18727#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
18728#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
18729#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
18731/******************** Bit definition for USB_OTG_HPRT register ********************/
18732#define USB_OTG_HPRT_PCSTS_Pos (0U)
18733#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
18734#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
18735#define USB_OTG_HPRT_PCDET_Pos (1U)
18736#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
18737#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
18738#define USB_OTG_HPRT_PENA_Pos (2U)
18739#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
18740#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
18741#define USB_OTG_HPRT_PENCHNG_Pos (3U)
18742#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
18743#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
18744#define USB_OTG_HPRT_POCA_Pos (4U)
18745#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
18746#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
18747#define USB_OTG_HPRT_POCCHNG_Pos (5U)
18748#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
18749#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
18750#define USB_OTG_HPRT_PRES_Pos (6U)
18751#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
18752#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
18753#define USB_OTG_HPRT_PSUSP_Pos (7U)
18754#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
18755#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
18756#define USB_OTG_HPRT_PRST_Pos (8U)
18757#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
18758#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
18760#define USB_OTG_HPRT_PLSTS_Pos (10U)
18761#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
18762#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
18763#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
18764#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
18765#define USB_OTG_HPRT_PPWR_Pos (12U)
18766#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
18767#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
18769#define USB_OTG_HPRT_PTCTL_Pos (13U)
18770#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
18771#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
18772#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
18773#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
18774#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
18775#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
18777#define USB_OTG_HPRT_PSPD_Pos (17U)
18778#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
18779#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
18780#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
18781#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
18783/******************** Bit definition for USB_OTG_HCCHAR register ********************/
18784#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
18785#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
18786#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
18788#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
18789#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
18790#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
18791#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
18792#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
18793#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
18794#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
18795#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
18796#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
18797#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
18798#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
18799#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
18800#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
18802#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
18803#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
18804#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
18805#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
18806#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
18808#define USB_OTG_HCCHAR_MC_Pos (20U)
18809#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
18810#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
18811#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
18812#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
18814#define USB_OTG_HCCHAR_DAD_Pos (22U)
18815#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
18816#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
18817#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
18818#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
18819#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
18820#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
18821#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
18822#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
18823#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
18824#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
18825#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
18826#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
18827#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
18828#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
18829#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
18830#define USB_OTG_HCCHAR_CHENA_Pos (31U)
18831#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
18832#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
18834/******************** Bit definition for USB_OTG_HCINT register ********************/
18835#define USB_OTG_HCINT_XFRC_Pos (0U)
18836#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
18837#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
18838#define USB_OTG_HCINT_CHH_Pos (1U)
18839#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
18840#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
18841#define USB_OTG_HCINT_AHBERR_Pos (2U)
18842#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
18843#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
18844#define USB_OTG_HCINT_STALL_Pos (3U)
18845#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
18846#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
18847#define USB_OTG_HCINT_NAK_Pos (4U)
18848#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
18849#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
18850#define USB_OTG_HCINT_ACK_Pos (5U)
18851#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
18852#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
18853#define USB_OTG_HCINT_NYET_Pos (6U)
18854#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
18855#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
18856#define USB_OTG_HCINT_TXERR_Pos (7U)
18857#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
18858#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
18859#define USB_OTG_HCINT_BBERR_Pos (8U)
18860#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
18861#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
18862#define USB_OTG_HCINT_FRMOR_Pos (9U)
18863#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
18864#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
18865#define USB_OTG_HCINT_DTERR_Pos (10U)
18866#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
18867#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
18869/******************** Bit definition for USB_OTG_HCINTMSK register ********************/
18870#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
18871#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
18872#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
18873#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
18874#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
18875#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
18876#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
18877#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
18878#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
18879#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
18880#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
18881#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
18882#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
18883#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
18884#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
18885#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
18886#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
18887#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
18888#define USB_OTG_HCINTMSK_NYET_Pos (6U)
18889#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
18890#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
18891#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
18892#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
18893#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
18894#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
18895#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
18896#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
18897#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
18898#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
18899#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
18900#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
18901#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
18902#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
18904/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
18905#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
18906#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
18907#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
18908#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
18909#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
18910#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
18911#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
18912#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
18913#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
18914#define USB_OTG_HCTSIZ_DPID_Pos (29U)
18915#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
18916#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
18917#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
18918#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
18920/******************** Bit definition for USB_OTG_HCDMA register *********************/
18921#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
18922#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
18923#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
18925/******************** Bit definition for USB_OTG_DCFG register ********************/
18926#define USB_OTG_DCFG_DSPD_Pos (0U)
18927#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
18928#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
18929#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
18930#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
18931#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
18932#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
18933#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
18934#define USB_OTG_DCFG_DAD_Pos (4U)
18935#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
18936#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
18937#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
18938#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
18939#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
18940#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
18941#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
18942#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
18943#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
18944#define USB_OTG_DCFG_PFIVL_Pos (11U)
18945#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
18946#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
18947#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
18948#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
18949#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
18950#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
18951#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
18952#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
18953#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
18955/******************** Bit definition for USB_OTG_DCTL register ********************/
18956#define USB_OTG_DCTL_RWUSIG_Pos (0U)
18957#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
18958#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
18959#define USB_OTG_DCTL_SDIS_Pos (1U)
18960#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
18961#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
18962#define USB_OTG_DCTL_GINSTS_Pos (2U)
18963#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
18964#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
18965#define USB_OTG_DCTL_GONSTS_Pos (3U)
18966#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
18967#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
18968#define USB_OTG_DCTL_TCTL_Pos (4U)
18969#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
18970#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
18971#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
18972#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
18973#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
18974#define USB_OTG_DCTL_SGINAK_Pos (7U)
18975#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
18976#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
18977#define USB_OTG_DCTL_CGINAK_Pos (8U)
18978#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
18979#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
18980#define USB_OTG_DCTL_SGONAK_Pos (9U)
18981#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
18982#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
18983#define USB_OTG_DCTL_CGONAK_Pos (10U)
18984#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
18985#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
18986#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
18987#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
18988#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
18990/******************** Bit definition for USB_OTG_DSTS register ********************/
18991#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
18992#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
18993#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
18994#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
18995#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
18996#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
18997#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
18998#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
18999#define USB_OTG_DSTS_EERR_Pos (3U)
19000#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
19001#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
19002#define USB_OTG_DSTS_FNSOF_Pos (8U)
19003#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
19004#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
19006/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
19007#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
19008#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
19009#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
19010#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
19011#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
19012#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
19013#define USB_OTG_DIEPMSK_TOM_Pos (3U)
19014#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
19015#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
19016#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
19017#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
19018#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
19019#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
19020#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
19021#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
19022#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
19023#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
19024#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
19025#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
19026#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
19027#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
19028#define USB_OTG_DIEPMSK_BIM_Pos (9U)
19029#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
19030#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
19032/* Legacy defines */
19033#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos USB_OTG_DIEPMSK_XFRCM_Pos
19034#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk USB_OTG_DIEPMSK_XFRCM_Msk
19035#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPMSK_XFRCM
19036#define USB_OTG_DIEPEACHMSK1_EPDM_Pos USB_OTG_DIEPMSK_EPDM_Pos
19037#define USB_OTG_DIEPEACHMSK1_EPDM_Msk USB_OTG_DIEPMSK_EPDM_Msk
19038#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPMSK_EPDM
19039#define USB_OTG_DIEPEACHMSK1_TOM_Pos USB_OTG_DIEPMSK_TOM_Pos
19040#define USB_OTG_DIEPEACHMSK1_TOM_Msk USB_OTG_DIEPMSK_TOM_Msk
19041#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPMSK_TOM
19042#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos USB_OTG_DIEPMSK_ITTXFEMSK_Pos
19043#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk USB_OTG_DIEPMSK_ITTXFEMSK_Msk
19044#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK
19045#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos USB_OTG_DIEPMSK_INEPNMM_Pos
19046#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk USB_OTG_DIEPMSK_INEPNMM_Msk
19047#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPMSK_INEPNMM
19048#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos USB_OTG_DIEPMSK_INEPNEM_Pos
19049#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk USB_OTG_DIEPMSK_INEPNEM_Pos
19050#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPMSK_INEPNEM
19051#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos USB_OTG_DIEPMSK_TXFURM_Pos
19052#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk USB_OTG_DIEPMSK_TXFURM_Msk
19053#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPMSK_TXFURM
19054#define USB_OTG_DIEPEACHMSK1_BIM_Pos USB_OTG_DIEPMSK_BIM_Pos
19055#define USB_OTG_DIEPEACHMSK1_BIM_Msk USB_OTG_DIEPMSK_BIM_Msk
19056#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPMSK_BIM
19057#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
19058#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
19059#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
19061/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
19062#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
19063#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
19064#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
19065#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
19066#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
19067#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
19068#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
19069#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
19070#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
19071#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
19072#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
19073#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
19074#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
19075#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
19076#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
19077#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
19078#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
19079#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
19080#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
19081#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
19082#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
19084/* Legacy defines */
19085#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos USB_OTG_DOEPMSK_XFRCM_Pos
19086#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk USB_OTG_DOEPMSK_XFRCM_Msk
19087#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPMSK_XFRCM
19088#define USB_OTG_DOEPEACHMSK1_EPDM_Pos USB_OTG_DOEPMSK_EPDM_Pos
19089#define USB_OTG_DOEPEACHMSK1_EPDM_Msk USB_OTG_DOEPMSK_EPDM_Msk
19090#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPMSK_EPDM
19091#define USB_OTG_DOEPEACHMSK1_TOM_Pos USB_OTG_DOEPMSK_STUPM_Pos
19092#define USB_OTG_DOEPEACHMSK1_TOM_Msk USB_OTG_DOEPMSK_STUPM_Msk
19093#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPMSK_STUPM
19094#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos USB_OTG_DOEPMSK_OTEPDM_Pos
19095#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk USB_OTG_DOEPMSK_OTEPDM_Msk
19096#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPMSK_OTEPDM
19097#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
19098#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
19099#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
19100#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos USB_OTG_DOEPMSK_B2BSTUP_Pos
19101#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk USB_OTG_DOEPMSK_B2BSTUP_Msk
19102#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPMSK_B2BSTUP
19103#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos USB_OTG_DOEPMSK_OPEM_Pos
19104#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk USB_OTG_DOEPMSK_OPEM_Msk
19105#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPMSK_OPEM
19106#define USB_OTG_DOEPEACHMSK1_BIM_Pos USB_OTG_DOEPMSK_BOIM_Pos
19107#define USB_OTG_DOEPEACHMSK1_BIM_Msk USB_OTG_DOEPMSK_BOIM_Msk
19108#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPMSK_BOIM
19109#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
19110#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
19111#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
19112#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
19113#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
19114#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
19115#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
19116#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
19117#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
19119/******************** Bit definition for USB_OTG_DAINT register ********************/
19120#define USB_OTG_DAINT_IEPINT_Pos (0U)
19121#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
19122#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
19123#define USB_OTG_DAINT_OEPINT_Pos (16U)
19124#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
19125#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
19127/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
19128#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
19129#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
19130#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
19131#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
19132#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
19133#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
19135/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
19136#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
19137#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
19138#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
19140/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
19141#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
19142#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
19143#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
19145/******************** Bit definition for USB_OTG_DTHRCTL register ***************/
19146#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
19147#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
19148#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
19149#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
19150#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
19151#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
19152#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
19153#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19154#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
19155#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19156#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19157#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19158#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19159#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19160#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19161#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19162#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19163#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19164#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
19165#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
19166#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
19167#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
19168#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19169#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
19170#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19171#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19172#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19173#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19174#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19175#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19176#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19177#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19178#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19179#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
19180#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
19181#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
19183/******************** Bit definition for USB_OTG_DIEPEMPMSK register ***************/
19184#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
19185#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
19186#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
19188/******************** Bit definition for USB_OTG_DEACHINT register ********************/
19189#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
19190#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
19191#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
19192#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
19193#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
19194#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
19196/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
19197#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
19198#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
19199#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
19200#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
19201#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
19202#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
19204/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
19205#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
19206#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
19207#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
19208#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
19209#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
19210#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
19211#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
19212#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
19213#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
19214#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
19215#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
19216#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
19217#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
19218#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
19219#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
19220#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
19221#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
19222#define USB_OTG_DIEPCTL_STALL_Pos (21U)
19223#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
19224#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
19225#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
19226#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
19227#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
19228#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
19229#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
19230#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
19231#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
19232#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
19233#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
19234#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
19235#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
19236#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
19237#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
19238#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
19239#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
19240#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
19241#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
19242#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
19243#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
19244#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
19245#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
19246#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
19247#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
19248#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
19249#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
19251/******************** Bit definition for USB_OTG_DIEPINT register ********************/
19252#define USB_OTG_DIEPINT_XFRC_Pos (0U)
19253#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
19254#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
19255#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
19256#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
19257#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
19258#define USB_OTG_DIEPINT_TOC_Pos (3U)
19259#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
19260#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
19261#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
19262#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
19263#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
19264#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
19265#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
19266#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
19267#define USB_OTG_DIEPINT_TXFE_Pos (7U)
19268#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
19269#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
19270#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
19271#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
19272#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
19273#define USB_OTG_DIEPINT_BNA_Pos (9U)
19274#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
19275#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
19276#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
19277#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
19278#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
19279#define USB_OTG_DIEPINT_BERR_Pos (12U)
19280#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
19281#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
19282#define USB_OTG_DIEPINT_NAK_Pos (13U)
19283#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
19284#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
19286/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
19287#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
19288#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
19289#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
19290#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
19291#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
19292#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
19293#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
19294#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
19295#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
19297/******************** Bit definition for USB_OTG_DIEPDMA register *********************/
19298#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
19299#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
19300#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
19302/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
19303#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
19304#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
19305#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
19307/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
19308#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
19309#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
19310#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
19311#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
19312#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
19313#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
19314#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
19315#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
19316#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
19317#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
19318#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
19319#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
19320#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
19321#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
19322#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
19323#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
19324#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
19325#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
19326#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
19327#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
19328#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
19329#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
19330#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
19331#define USB_OTG_DOEPCTL_STALL_Pos (21U)
19332#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
19333#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
19334#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
19335#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
19336#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
19337#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
19338#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
19339#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
19340#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
19341#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
19342#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
19343#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
19344#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
19345#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
19347/******************** Bit definition for USB_OTG_DOEPINT register ********************/
19348#define USB_OTG_DOEPINT_XFRC_Pos (0U)
19349#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
19350#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
19351#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
19352#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
19353#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
19354#define USB_OTG_DOEPINT_STUP_Pos (3U)
19355#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
19356#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
19357#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
19358#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
19359#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
19360#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
19361#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
19362#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
19363#define USB_OTG_DOEPINT_NYET_Pos (14U)
19364#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
19365#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
19367/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
19368#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
19369#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
19370#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
19371#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
19372#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
19373#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
19374#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
19375#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
19376#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
19377#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
19378#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
19380/******************** Bit definition for USB_OTG_PCGCCTL register ********************/
19381#define USB_OTG_PCGCCTL_STPPCLK_Pos (0U)
19382#define USB_OTG_PCGCCTL_STPPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STPPCLK_Pos)
19383#define USB_OTG_PCGCCTL_STPPCLK USB_OTG_PCGCCTL_STPPCLK_Msk
19384#define USB_OTG_PCGCCTL_GATEHCLK_Pos (1U)
19385#define USB_OTG_PCGCCTL_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATEHCLK_Pos)
19386#define USB_OTG_PCGCCTL_GATEHCLK USB_OTG_PCGCCTL_GATEHCLK_Msk
19387#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
19388#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
19389#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
19391/* Legacy defines */
19392#define USB_OTG_PCGCCTL_STOPCLK_Pos USB_OTG_PCGCCTL_STPPCLK_Pos
19393#define USB_OTG_PCGCCTL_STOPCLK_Msk USB_OTG_PCGCCTL_STPPCLK_Msk
19394#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
19395#define USB_OTG_PCGCCTL_GATECLK_Pos USB_OTG_PCGCCTL_GATEHCLK_Pos
19396#define USB_OTG_PCGCCTL_GATECLK_Msk USB_OTG_PCGCCTL_GATEHCLK_Msk
19397#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
19398#define USB_OTG_PCGCR_STPPCLK_Pos USB_OTG_PCGCCTL_STPPCLK_Pos
19399#define USB_OTG_PCGCR_STPPCLK_Msk USB_OTG_PCGCCTL_STPPCLK_Msk
19400#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCCTL_STPPCLK
19401#define USB_OTG_PCGCR_GATEHCLK_Pos USB_OTG_PCGCCTL_GATEHCLK_Pos
19402#define USB_OTG_PCGCR_GATEHCLK_Msk USB_OTG_PCGCCTL_GATEHCLK_Msk
19403#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCCTL_GATEHCLK
19404#define USB_OTG_PCGCR_PHYSUSP_Pos USB_OTG_PCGCCTL_PHYSUSP_Pos
19405#define USB_OTG_PCGCR_PHYSUSP_Msk USB_OTG_PCGCCTL_PHYSUSP_Msk
19406#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP
19407#define USB_OTG_GHWCFG3_LPMMode_Pos (14U)
19408#define USB_OTG_GHWCFG3_LPMMode_Msk (0x1UL << USB_OTG_GHWCFG3_LPMMode_Pos)
19409#define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */
19410#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
19411#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
19412#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
19413#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19414#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19415#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19416#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19417#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19418#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19419#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19420#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
19421#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
19422#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
19423#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19424#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19425#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19426#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19427#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19428#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19429#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19430#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
19431#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
19432#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
19433#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
19434#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
19435#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
19436#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
19437#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
19438#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
19439#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
19440#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
19455/******************************* ADC Instances ********************************/
19456#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
19457 ((INSTANCE) == ADC2) || \
19458 ((INSTANCE) == ADC3))
19459
19460#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
19461
19462#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
19463
19464/******************************* AES Instances ********************************/
19465#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
19466
19467/******************************** CAN Instances ******************************/
19468#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
19469 ((INSTANCE) == CAN2))
19470
19471/******************************** COMP Instances ******************************/
19472#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
19473 ((INSTANCE) == COMP2))
19474
19475#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
19476
19477/******************** COMP Instances with window mode capability **************/
19478#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
19479
19480/******************************* CRC Instances ********************************/
19481#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
19482
19483/******************************* DAC Instances ********************************/
19484#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
19485
19486/****************************** DFSDM Instances *******************************/
19487#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
19488 ((INSTANCE) == DFSDM1_Filter1) || \
19489 ((INSTANCE) == DFSDM1_Filter2) || \
19490 ((INSTANCE) == DFSDM1_Filter3))
19491
19492#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
19493 ((INSTANCE) == DFSDM1_Channel1) || \
19494 ((INSTANCE) == DFSDM1_Channel2) || \
19495 ((INSTANCE) == DFSDM1_Channel3) || \
19496 ((INSTANCE) == DFSDM1_Channel4) || \
19497 ((INSTANCE) == DFSDM1_Channel5) || \
19498 ((INSTANCE) == DFSDM1_Channel6) || \
19499 ((INSTANCE) == DFSDM1_Channel7))
19500
19501/******************************* DCMI Instances *******************************/
19502#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
19503
19504/******************************* DMA2D Instances *******************************/
19505#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
19506
19507/******************************** DMA Instances *******************************/
19508#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
19509 ((INSTANCE) == DMA1_Channel2) || \
19510 ((INSTANCE) == DMA1_Channel3) || \
19511 ((INSTANCE) == DMA1_Channel4) || \
19512 ((INSTANCE) == DMA1_Channel5) || \
19513 ((INSTANCE) == DMA1_Channel6) || \
19514 ((INSTANCE) == DMA1_Channel7) || \
19515 ((INSTANCE) == DMA2_Channel1) || \
19516 ((INSTANCE) == DMA2_Channel2) || \
19517 ((INSTANCE) == DMA2_Channel3) || \
19518 ((INSTANCE) == DMA2_Channel4) || \
19519 ((INSTANCE) == DMA2_Channel5) || \
19520 ((INSTANCE) == DMA2_Channel6) || \
19521 ((INSTANCE) == DMA2_Channel7))
19522
19523/******************************* GPIO Instances *******************************/
19524#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
19525 ((INSTANCE) == GPIOB) || \
19526 ((INSTANCE) == GPIOC) || \
19527 ((INSTANCE) == GPIOD) || \
19528 ((INSTANCE) == GPIOE) || \
19529 ((INSTANCE) == GPIOF) || \
19530 ((INSTANCE) == GPIOG) || \
19531 ((INSTANCE) == GPIOH) || \
19532 ((INSTANCE) == GPIOI))
19533
19534/******************************* GPIO AF Instances ****************************/
19535/* On L4, all GPIO Bank support AF */
19536#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
19537
19538/**************************** GPIO Lock Instances *****************************/
19539/* On L4, all GPIO Bank support the Lock mechanism */
19540#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
19541
19542/******************************** I2C Instances *******************************/
19543#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
19544 ((INSTANCE) == I2C2) || \
19545 ((INSTANCE) == I2C3) || \
19546 ((INSTANCE) == I2C4))
19547
19548/****************** I2C Instances : wakeup capability from stop modes *********/
19549#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
19550
19551/******************************* LCD Instances ********************************/
19552#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
19553
19554/******************************* HCD Instances *******************************/
19555#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
19556
19557/****************************** OPAMP Instances *******************************/
19558#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
19559 ((INSTANCE) == OPAMP2))
19560
19561#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
19562
19563/******************************* PCD Instances *******************************/
19564#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
19565
19566/******************************* QSPI Instances *******************************/
19567#define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
19568
19569/******************************* RNG Instances ********************************/
19570#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
19571
19572/****************************** RTC Instances *********************************/
19573#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
19574
19575/******************************** SAI Instances *******************************/
19576#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
19577 ((INSTANCE) == SAI1_Block_B) || \
19578 ((INSTANCE) == SAI2_Block_A) || \
19579 ((INSTANCE) == SAI2_Block_B))
19580
19581/****************************** SDMMC Instances *******************************/
19582#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
19583
19584/****************************** SMBUS Instances *******************************/
19585#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
19586 ((INSTANCE) == I2C2) || \
19587 ((INSTANCE) == I2C3) || \
19588 ((INSTANCE) == I2C4))
19589
19590/******************************** SPI Instances *******************************/
19591#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
19592 ((INSTANCE) == SPI2) || \
19593 ((INSTANCE) == SPI3))
19594
19595/******************************** SWPMI Instances *****************************/
19596#define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
19597
19598/****************** LPTIM Instances : All supported instances *****************/
19599#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
19600 ((INSTANCE) == LPTIM2))
19601
19602/****************** LPTIM Instances : supporting the encoder mode *************/
19603#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
19604
19605/****************** TIM Instances : All supported instances *******************/
19606#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19607 ((INSTANCE) == TIM2) || \
19608 ((INSTANCE) == TIM3) || \
19609 ((INSTANCE) == TIM4) || \
19610 ((INSTANCE) == TIM5) || \
19611 ((INSTANCE) == TIM6) || \
19612 ((INSTANCE) == TIM7) || \
19613 ((INSTANCE) == TIM8) || \
19614 ((INSTANCE) == TIM15) || \
19615 ((INSTANCE) == TIM16) || \
19616 ((INSTANCE) == TIM17))
19617
19618/****************** TIM Instances : supporting 32 bits counter ****************/
19619#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
19620 ((INSTANCE) == TIM5))
19621
19622/****************** TIM Instances : supporting the break function *************/
19623#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19624 ((INSTANCE) == TIM8) || \
19625 ((INSTANCE) == TIM15) || \
19626 ((INSTANCE) == TIM16) || \
19627 ((INSTANCE) == TIM17))
19628
19629/************** TIM Instances : supporting Break source selection *************/
19630#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19631 ((INSTANCE) == TIM8) || \
19632 ((INSTANCE) == TIM15) || \
19633 ((INSTANCE) == TIM16) || \
19634 ((INSTANCE) == TIM17))
19635
19636/****************** TIM Instances : supporting 2 break inputs *****************/
19637#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19638 ((INSTANCE) == TIM8))
19639
19640/************* TIM Instances : at least 1 capture/compare channel *************/
19641#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19642 ((INSTANCE) == TIM2) || \
19643 ((INSTANCE) == TIM3) || \
19644 ((INSTANCE) == TIM4) || \
19645 ((INSTANCE) == TIM5) || \
19646 ((INSTANCE) == TIM8) || \
19647 ((INSTANCE) == TIM15) || \
19648 ((INSTANCE) == TIM16) || \
19649 ((INSTANCE) == TIM17))
19650
19651/************ TIM Instances : at least 2 capture/compare channels *************/
19652#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19653 ((INSTANCE) == TIM2) || \
19654 ((INSTANCE) == TIM3) || \
19655 ((INSTANCE) == TIM4) || \
19656 ((INSTANCE) == TIM5) || \
19657 ((INSTANCE) == TIM8) || \
19658 ((INSTANCE) == TIM15))
19659
19660/************ TIM Instances : at least 3 capture/compare channels *************/
19661#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19662 ((INSTANCE) == TIM2) || \
19663 ((INSTANCE) == TIM3) || \
19664 ((INSTANCE) == TIM4) || \
19665 ((INSTANCE) == TIM5) || \
19666 ((INSTANCE) == TIM8))
19667
19668/************ TIM Instances : at least 4 capture/compare channels *************/
19669#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19670 ((INSTANCE) == TIM2) || \
19671 ((INSTANCE) == TIM3) || \
19672 ((INSTANCE) == TIM4) || \
19673 ((INSTANCE) == TIM5) || \
19674 ((INSTANCE) == TIM8))
19675
19676/****************** TIM Instances : at least 5 capture/compare channels *******/
19677#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19678 ((INSTANCE) == TIM8))
19679
19680/****************** TIM Instances : at least 6 capture/compare channels *******/
19681#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19682 ((INSTANCE) == TIM8))
19683
19684/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
19685#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19686 ((INSTANCE) == TIM8) || \
19687 ((INSTANCE) == TIM15) || \
19688 ((INSTANCE) == TIM16) || \
19689 ((INSTANCE) == TIM17))
19690
19691/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
19692#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19693 ((INSTANCE) == TIM2) || \
19694 ((INSTANCE) == TIM3) || \
19695 ((INSTANCE) == TIM4) || \
19696 ((INSTANCE) == TIM5) || \
19697 ((INSTANCE) == TIM6) || \
19698 ((INSTANCE) == TIM7) || \
19699 ((INSTANCE) == TIM8) || \
19700 ((INSTANCE) == TIM15) || \
19701 ((INSTANCE) == TIM16) || \
19702 ((INSTANCE) == TIM17))
19703
19704/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
19705#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19706 ((INSTANCE) == TIM2) || \
19707 ((INSTANCE) == TIM3) || \
19708 ((INSTANCE) == TIM4) || \
19709 ((INSTANCE) == TIM5) || \
19710 ((INSTANCE) == TIM8) || \
19711 ((INSTANCE) == TIM15) || \
19712 ((INSTANCE) == TIM16) || \
19713 ((INSTANCE) == TIM17))
19714
19715/******************** TIM Instances : DMA burst feature ***********************/
19716#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19717 ((INSTANCE) == TIM2) || \
19718 ((INSTANCE) == TIM3) || \
19719 ((INSTANCE) == TIM4) || \
19720 ((INSTANCE) == TIM5) || \
19721 ((INSTANCE) == TIM8) || \
19722 ((INSTANCE) == TIM15) || \
19723 ((INSTANCE) == TIM16) || \
19724 ((INSTANCE) == TIM17))
19725
19726/******************* TIM Instances : output(s) available **********************/
19727#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
19728 ((((INSTANCE) == TIM1) && \
19729 (((CHANNEL) == TIM_CHANNEL_1) || \
19730 ((CHANNEL) == TIM_CHANNEL_2) || \
19731 ((CHANNEL) == TIM_CHANNEL_3) || \
19732 ((CHANNEL) == TIM_CHANNEL_4) || \
19733 ((CHANNEL) == TIM_CHANNEL_5) || \
19734 ((CHANNEL) == TIM_CHANNEL_6))) \
19735 || \
19736 (((INSTANCE) == TIM2) && \
19737 (((CHANNEL) == TIM_CHANNEL_1) || \
19738 ((CHANNEL) == TIM_CHANNEL_2) || \
19739 ((CHANNEL) == TIM_CHANNEL_3) || \
19740 ((CHANNEL) == TIM_CHANNEL_4))) \
19741 || \
19742 (((INSTANCE) == TIM3) && \
19743 (((CHANNEL) == TIM_CHANNEL_1) || \
19744 ((CHANNEL) == TIM_CHANNEL_2) || \
19745 ((CHANNEL) == TIM_CHANNEL_3) || \
19746 ((CHANNEL) == TIM_CHANNEL_4))) \
19747 || \
19748 (((INSTANCE) == TIM4) && \
19749 (((CHANNEL) == TIM_CHANNEL_1) || \
19750 ((CHANNEL) == TIM_CHANNEL_2) || \
19751 ((CHANNEL) == TIM_CHANNEL_3) || \
19752 ((CHANNEL) == TIM_CHANNEL_4))) \
19753 || \
19754 (((INSTANCE) == TIM5) && \
19755 (((CHANNEL) == TIM_CHANNEL_1) || \
19756 ((CHANNEL) == TIM_CHANNEL_2) || \
19757 ((CHANNEL) == TIM_CHANNEL_3) || \
19758 ((CHANNEL) == TIM_CHANNEL_4))) \
19759 || \
19760 (((INSTANCE) == TIM8) && \
19761 (((CHANNEL) == TIM_CHANNEL_1) || \
19762 ((CHANNEL) == TIM_CHANNEL_2) || \
19763 ((CHANNEL) == TIM_CHANNEL_3) || \
19764 ((CHANNEL) == TIM_CHANNEL_4) || \
19765 ((CHANNEL) == TIM_CHANNEL_5) || \
19766 ((CHANNEL) == TIM_CHANNEL_6))) \
19767 || \
19768 (((INSTANCE) == TIM15) && \
19769 (((CHANNEL) == TIM_CHANNEL_1) || \
19770 ((CHANNEL) == TIM_CHANNEL_2))) \
19771 || \
19772 (((INSTANCE) == TIM16) && \
19773 (((CHANNEL) == TIM_CHANNEL_1))) \
19774 || \
19775 (((INSTANCE) == TIM17) && \
19776 (((CHANNEL) == TIM_CHANNEL_1))))
19777
19778/****************** TIM Instances : supporting complementary output(s) ********/
19779#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
19780 ((((INSTANCE) == TIM1) && \
19781 (((CHANNEL) == TIM_CHANNEL_1) || \
19782 ((CHANNEL) == TIM_CHANNEL_2) || \
19783 ((CHANNEL) == TIM_CHANNEL_3))) \
19784 || \
19785 (((INSTANCE) == TIM8) && \
19786 (((CHANNEL) == TIM_CHANNEL_1) || \
19787 ((CHANNEL) == TIM_CHANNEL_2) || \
19788 ((CHANNEL) == TIM_CHANNEL_3))) \
19789 || \
19790 (((INSTANCE) == TIM15) && \
19791 ((CHANNEL) == TIM_CHANNEL_1)) \
19792 || \
19793 (((INSTANCE) == TIM16) && \
19794 ((CHANNEL) == TIM_CHANNEL_1)) \
19795 || \
19796 (((INSTANCE) == TIM17) && \
19797 ((CHANNEL) == TIM_CHANNEL_1)))
19798
19799/****************** TIM Instances : supporting clock division *****************/
19800#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19801 ((INSTANCE) == TIM2) || \
19802 ((INSTANCE) == TIM3) || \
19803 ((INSTANCE) == TIM4) || \
19804 ((INSTANCE) == TIM5) || \
19805 ((INSTANCE) == TIM8) || \
19806 ((INSTANCE) == TIM15) || \
19807 ((INSTANCE) == TIM16) || \
19808 ((INSTANCE) == TIM17))
19809
19810/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
19811#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19812 ((INSTANCE) == TIM2) || \
19813 ((INSTANCE) == TIM3) || \
19814 ((INSTANCE) == TIM4) || \
19815 ((INSTANCE) == TIM5) || \
19816 ((INSTANCE) == TIM8) || \
19817 ((INSTANCE) == TIM15))
19818
19819/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
19820#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19821 ((INSTANCE) == TIM2) || \
19822 ((INSTANCE) == TIM3) || \
19823 ((INSTANCE) == TIM4) || \
19824 ((INSTANCE) == TIM5) || \
19825 ((INSTANCE) == TIM8))
19826
19827/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
19828#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19829 ((INSTANCE) == TIM2) || \
19830 ((INSTANCE) == TIM3) || \
19831 ((INSTANCE) == TIM4) || \
19832 ((INSTANCE) == TIM5) || \
19833 ((INSTANCE) == TIM8) || \
19834 ((INSTANCE) == TIM15))
19835
19836/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
19837#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19838 ((INSTANCE) == TIM2) || \
19839 ((INSTANCE) == TIM3) || \
19840 ((INSTANCE) == TIM4) || \
19841 ((INSTANCE) == TIM5) || \
19842 ((INSTANCE) == TIM8) || \
19843 ((INSTANCE) == TIM15))
19844
19845/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
19846#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19847 ((INSTANCE) == TIM8))
19848
19849/****************** TIM Instances : supporting commutation event generation ***/
19850#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19851 ((INSTANCE) == TIM8) || \
19852 ((INSTANCE) == TIM15) || \
19853 ((INSTANCE) == TIM16) || \
19854 ((INSTANCE) == TIM17))
19855
19856/****************** TIM Instances : supporting counting mode selection ********/
19857#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19858 ((INSTANCE) == TIM2) || \
19859 ((INSTANCE) == TIM3) || \
19860 ((INSTANCE) == TIM4) || \
19861 ((INSTANCE) == TIM5) || \
19862 ((INSTANCE) == TIM8))
19863
19864/****************** TIM Instances : supporting encoder interface **************/
19865#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19866 ((INSTANCE) == TIM2) || \
19867 ((INSTANCE) == TIM3) || \
19868 ((INSTANCE) == TIM4) || \
19869 ((INSTANCE) == TIM5) || \
19870 ((INSTANCE) == TIM8))
19871
19872/****************** TIM Instances : supporting Hall sensor interface **********/
19873#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19874 ((INSTANCE) == TIM2) || \
19875 ((INSTANCE) == TIM3) || \
19876 ((INSTANCE) == TIM4) || \
19877 ((INSTANCE) == TIM5) || \
19878 ((INSTANCE) == TIM8))
19879
19880/**************** TIM Instances : external trigger input available ************/
19881#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19882 ((INSTANCE) == TIM2) || \
19883 ((INSTANCE) == TIM3) || \
19884 ((INSTANCE) == TIM4) || \
19885 ((INSTANCE) == TIM5) || \
19886 ((INSTANCE) == TIM8))
19887
19888/************* TIM Instances : supporting ETR source selection ***************/
19889#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19890 ((INSTANCE) == TIM2) || \
19891 ((INSTANCE) == TIM3) || \
19892 ((INSTANCE) == TIM8))
19893
19894/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
19895#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19896 ((INSTANCE) == TIM2) || \
19897 ((INSTANCE) == TIM3) || \
19898 ((INSTANCE) == TIM4) || \
19899 ((INSTANCE) == TIM5) || \
19900 ((INSTANCE) == TIM6) || \
19901 ((INSTANCE) == TIM7) || \
19902 ((INSTANCE) == TIM8) || \
19903 ((INSTANCE) == TIM15))
19904
19905/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
19906#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19907 ((INSTANCE) == TIM2) || \
19908 ((INSTANCE) == TIM3) || \
19909 ((INSTANCE) == TIM4) || \
19910 ((INSTANCE) == TIM5) || \
19911 ((INSTANCE) == TIM8) || \
19912 ((INSTANCE) == TIM15))
19913
19914/****************** TIM Instances : supporting OCxREF clear *******************/
19915#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19916 ((INSTANCE) == TIM2) || \
19917 ((INSTANCE) == TIM3) || \
19918 ((INSTANCE) == TIM4) || \
19919 ((INSTANCE) == TIM5) || \
19920 ((INSTANCE) == TIM8))
19921
19922/****************** TIM Instances : remapping capability **********************/
19923#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19924 ((INSTANCE) == TIM2) || \
19925 ((INSTANCE) == TIM3) || \
19926 ((INSTANCE) == TIM8) || \
19927 ((INSTANCE) == TIM15) || \
19928 ((INSTANCE) == TIM16) || \
19929 ((INSTANCE) == TIM17))
19930
19931/****************** TIM Instances : supporting repetition counter *************/
19932#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19933 ((INSTANCE) == TIM8) || \
19934 ((INSTANCE) == TIM15) || \
19935 ((INSTANCE) == TIM16) || \
19936 ((INSTANCE) == TIM17))
19937
19938/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
19939#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19940 ((INSTANCE) == TIM8))
19941
19942/******************* TIM Instances : Timer input XOR function *****************/
19943#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19944 ((INSTANCE) == TIM2) || \
19945 ((INSTANCE) == TIM3) || \
19946 ((INSTANCE) == TIM4) || \
19947 ((INSTANCE) == TIM5) || \
19948 ((INSTANCE) == TIM8) || \
19949 ((INSTANCE) == TIM15))
19950
19951/****************** TIM Instances : Advanced timer instances *******************/
19952#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19953 ((INSTANCE) == TIM8))
19954
19955/****************************** TSC Instances *********************************/
19956#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
19957
19958/******************** USART Instances : Synchronous mode **********************/
19959#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
19960 ((INSTANCE) == USART2) || \
19961 ((INSTANCE) == USART3))
19962
19963/******************** UART Instances : Asynchronous mode **********************/
19964#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
19965 ((INSTANCE) == USART2) || \
19966 ((INSTANCE) == USART3) || \
19967 ((INSTANCE) == UART4) || \
19968 ((INSTANCE) == UART5))
19969
19970/****************** UART Instances : Auto Baud Rate detection ****************/
19971#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
19972 ((INSTANCE) == USART2) || \
19973 ((INSTANCE) == USART3) || \
19974 ((INSTANCE) == UART4) || \
19975 ((INSTANCE) == UART5))
19976
19977/****************** UART Instances : Driver Enable *****************/
19978#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
19979 ((INSTANCE) == USART2) || \
19980 ((INSTANCE) == USART3) || \
19981 ((INSTANCE) == UART4) || \
19982 ((INSTANCE) == UART5) || \
19983 ((INSTANCE) == LPUART1))
19984
19985/******************** UART Instances : Half-Duplex mode **********************/
19986#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
19987 ((INSTANCE) == USART2) || \
19988 ((INSTANCE) == USART3) || \
19989 ((INSTANCE) == UART4) || \
19990 ((INSTANCE) == UART5) || \
19991 ((INSTANCE) == LPUART1))
19992
19993/****************** UART Instances : Hardware Flow control ********************/
19994#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
19995 ((INSTANCE) == USART2) || \
19996 ((INSTANCE) == USART3) || \
19997 ((INSTANCE) == UART4) || \
19998 ((INSTANCE) == UART5) || \
19999 ((INSTANCE) == LPUART1))
20000
20001/******************** UART Instances : LIN mode **********************/
20002#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20003 ((INSTANCE) == USART2) || \
20004 ((INSTANCE) == USART3) || \
20005 ((INSTANCE) == UART4) || \
20006 ((INSTANCE) == UART5))
20007
20008/******************** UART Instances : Wake-up from Stop mode **********************/
20009#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20010 ((INSTANCE) == USART2) || \
20011 ((INSTANCE) == USART3) || \
20012 ((INSTANCE) == UART4) || \
20013 ((INSTANCE) == UART5) || \
20014 ((INSTANCE) == LPUART1))
20015
20016/*********************** UART Instances : IRDA mode ***************************/
20017#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20018 ((INSTANCE) == USART2) || \
20019 ((INSTANCE) == USART3) || \
20020 ((INSTANCE) == UART4) || \
20021 ((INSTANCE) == UART5))
20022
20023/********************* USART Instances : Smard card mode ***********************/
20024#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20025 ((INSTANCE) == USART2) || \
20026 ((INSTANCE) == USART3))
20027
20028/******************** LPUART Instance *****************************************/
20029#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
20030
20031/****************************** IWDG Instances ********************************/
20032#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
20033
20034/****************************** WWDG Instances ********************************/
20035#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
20036
20042/******************************************************************************/
20043/* For a painless codes migration between the STM32L4xx device product */
20044/* lines, the aliases defined below are put in place to overcome the */
20045/* differences in the interrupt handlers and IRQn definitions. */
20046/* No need to update developed interrupt code when moving across */
20047/* product lines within the same STM32L4 Family */
20048/******************************************************************************/
20049
20050/* Aliases for __IRQn */
20051#define TIM6_IRQn TIM6_DAC_IRQn
20052#define ADC1_IRQn ADC1_2_IRQn
20053#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
20054#define TIM8_IRQn TIM8_UP_IRQn
20055#define DCMI_PSSI_IRQn DCMI_IRQn
20056#define RNG_IRQn HASH_RNG_IRQn
20057#define HASH_CRS_IRQn CRS_IRQn
20058#define DFSDM0_IRQn DFSDM1_FLT0_IRQn
20059#define DFSDM1_IRQn DFSDM1_FLT1_IRQn
20060#define DFSDM2_IRQn DFSDM1_FLT2_IRQn
20061#define DFSDM3_IRQn DFSDM1_FLT3_IRQn
20062
20063/* Aliases for __IRQHandler */
20064#define TIM6_IRQHandler TIM6_DAC_IRQHandler
20065#define ADC1_IRQHandler ADC1_2_IRQHandler
20066#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
20067#define TIM8_IRQHandler TIM8_UP_IRQHandler
20068#define DCMI_PSSI_IRQHandler DCMI_IRQHandler
20069#define RNG_IRQHandler HASH_RNG_IRQHandler
20070#define HASH_CRS_IRQHandler CRS_IRQHandler
20071#define DFSDM0_IRQHandler DFSDM1_FLT0_IRQHandler
20072#define DFSDM1_IRQHandler DFSDM1_FLT1_IRQHandler
20073#define DFSDM2_IRQHandler DFSDM1_FLT2_IRQHandler
20074#define DFSDM3_IRQHandler DFSDM1_FLT3_IRQHandler
20075
20076#ifdef __cplusplus
20077}
20078#endif /* __cplusplus */
20079
20080#endif /* __STM32L4A6xx_H */
20081
__IO
#define __IO
Definition: core_armv81mml.h:277
__I
#define __I
Definition: core_armv81mml.h:274
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
IRQn_Type
IRQn_Type
STM32L4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32l4a6xx.h:66
CRS_IRQn
@ CRS_IRQn
Definition: stm32l4a6xx.h:160
TIM8_TRG_COM_IRQn
@ TIM8_TRG_COM_IRQn
Definition: stm32l4a6xx.h:123
PendSV_IRQn
@ PendSV_IRQn
Definition: stm32l4a6xx.h:75
EXTI2_IRQn
@ EXTI2_IRQn
Definition: stm32l4a6xx.h:86
DMA2_Channel4_IRQn
@ DMA2_Channel4_IRQn
Definition: stm32l4a6xx.h:137
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition: stm32l4a6xx.h:100
LCD_IRQn
@ LCD_IRQn
Definition: stm32l4a6xx.h:156
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition: stm32l4a6xx.h:81
ADC1_2_IRQn
@ ADC1_2_IRQn
Definition: stm32l4a6xx.h:96
DMA1_Channel2_IRQn
@ DMA1_Channel2_IRQn
Definition: stm32l4a6xx.h:90
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition: stm32l4a6xx.h:110
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition: stm32l4a6xx.h:111
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: stm32l4a6xx.h:70
SAI1_IRQn
@ SAI1_IRQn
Definition: stm32l4a6xx.h:152
TIM4_IRQn
@ TIM4_IRQn
Definition: stm32l4a6xx.h:108
TIM2_IRQn
@ TIM2_IRQn
Definition: stm32l4a6xx.h:106
DMA1_Channel1_IRQn
@ DMA1_Channel1_IRQn
Definition: stm32l4a6xx.h:89
DMA1_Channel3_IRQn
@ DMA1_Channel3_IRQn
Definition: stm32l4a6xx.h:91
USART2_IRQn
@ USART2_IRQn
Definition: stm32l4a6xx.h:116
DMA2_Channel7_IRQn
@ DMA2_Channel7_IRQn
Definition: stm32l4a6xx.h:147
SVCall_IRQn
@ SVCall_IRQn
Definition: stm32l4a6xx.h:73
SPI3_IRQn
@ SPI3_IRQn
Definition: stm32l4a6xx.h:129
SPI2_IRQn
@ SPI2_IRQn
Definition: stm32l4a6xx.h:114
TIM7_IRQn
@ TIM7_IRQn
Definition: stm32l4a6xx.h:133
CAN2_SCE_IRQn
@ CAN2_SCE_IRQn
Definition: stm32l4a6xx.h:167
RCC_IRQn
@ RCC_IRQn
Definition: stm32l4a6xx.h:83
ADC3_IRQn
@ ADC3_IRQn
Definition: stm32l4a6xx.h:125
LPTIM2_IRQn
@ LPTIM2_IRQn
Definition: stm32l4a6xx.h:144
TIM1_TRG_COM_TIM17_IRQn
@ TIM1_TRG_COM_TIM17_IRQn
Definition: stm32l4a6xx.h:104
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition: stm32l4a6xx.h:132
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition: stm32l4a6xx.h:112
QUADSPI_IRQn
@ QUADSPI_IRQn
Definition: stm32l4a6xx.h:149
DFSDM1_FLT0_IRQn
@ DFSDM1_FLT0_IRQn
Definition: stm32l4a6xx.h:139
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition: stm32l4a6xx.h:124
DMA1_Channel7_IRQn
@ DMA1_Channel7_IRQn
Definition: stm32l4a6xx.h:95
UsageFault_IRQn
@ UsageFault_IRQn
Definition: stm32l4a6xx.h:72
I2C4_ER_IRQn
@ I2C4_ER_IRQn
Definition: stm32l4a6xx.h:162
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32l4a6xx.h:76
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition: stm32l4a6xx.h:151
DFSDM1_FLT3_IRQn
@ DFSDM1_FLT3_IRQn
Definition: stm32l4a6xx.h:120
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition: stm32l4a6xx.h:150
AES_IRQn
@ AES_IRQn
Definition: stm32l4a6xx.h:157
CAN2_RX0_IRQn
@ CAN2_RX0_IRQn
Definition: stm32l4a6xx.h:165
BusFault_IRQn
@ BusFault_IRQn
Definition: stm32l4a6xx.h:71
HASH_RNG_IRQn
@ HASH_RNG_IRQn
Definition: stm32l4a6xx.h:158
DMA2_Channel6_IRQn
@ DMA2_Channel6_IRQn
Definition: stm32l4a6xx.h:146
TIM1_BRK_TIM15_IRQn
@ TIM1_BRK_TIM15_IRQn
Definition: stm32l4a6xx.h:102
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: stm32l4a6xx.h:74
FLASH_IRQn
@ FLASH_IRQn
Definition: stm32l4a6xx.h:82
SWPMI1_IRQn
@ SWPMI1_IRQn
Definition: stm32l4a6xx.h:154
WWDG_IRQn
@ WWDG_IRQn
Definition: stm32l4a6xx.h:78
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition: stm32l4a6xx.h:109
TIM3_IRQn
@ TIM3_IRQn
Definition: stm32l4a6xx.h:107
CAN1_TX_IRQn
@ CAN1_TX_IRQn
Definition: stm32l4a6xx.h:97
SDMMC1_IRQn
@ SDMMC1_IRQn
Definition: stm32l4a6xx.h:127
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition: stm32l4a6xx.h:118
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition: stm32l4a6xx.h:101
LPTIM1_IRQn
@ LPTIM1_IRQn
Definition: stm32l4a6xx.h:143
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition: stm32l4a6xx.h:145
FPU_IRQn
@ FPU_IRQn
Definition: stm32l4a6xx.h:159
DMA1_Channel6_IRQn
@ DMA1_Channel6_IRQn
Definition: stm32l4a6xx.h:94
SPI1_IRQn
@ SPI1_IRQn
Definition: stm32l4a6xx.h:113
DFSDM1_FLT2_IRQn
@ DFSDM1_FLT2_IRQn
Definition: stm32l4a6xx.h:141
HardFault_IRQn
@ HardFault_IRQn
Definition: stm32l4a6xx.h:69
CAN2_RX1_IRQn
@ CAN2_RX1_IRQn
Definition: stm32l4a6xx.h:166
FMC_IRQn
@ FMC_IRQn
Definition: stm32l4a6xx.h:126
EXTI0_IRQn
@ EXTI0_IRQn
Definition: stm32l4a6xx.h:84
CAN1_RX0_IRQn
@ CAN1_RX0_IRQn
Definition: stm32l4a6xx.h:98
EXTI4_IRQn
@ EXTI4_IRQn
Definition: stm32l4a6xx.h:88
SAI2_IRQn
@ SAI2_IRQn
Definition: stm32l4a6xx.h:153
DMA2_Channel1_IRQn
@ DMA2_Channel1_IRQn
Definition: stm32l4a6xx.h:134
DMA1_Channel5_IRQn
@ DMA1_Channel5_IRQn
Definition: stm32l4a6xx.h:93
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition: stm32l4a6xx.h:80
TIM8_BRK_IRQn
@ TIM8_BRK_IRQn
Definition: stm32l4a6xx.h:121
DMA2_Channel5_IRQn
@ DMA2_Channel5_IRQn
Definition: stm32l4a6xx.h:138
UART5_IRQn
@ UART5_IRQn
Definition: stm32l4a6xx.h:131
DMA2_Channel2_IRQn
@ DMA2_Channel2_IRQn
Definition: stm32l4a6xx.h:135
DMA2D_IRQn
@ DMA2D_IRQn
Definition: stm32l4a6xx.h:168
DCMI_IRQn
@ DCMI_IRQn
Definition: stm32l4a6xx.h:163
TIM1_UP_TIM16_IRQn
@ TIM1_UP_TIM16_IRQn
Definition: stm32l4a6xx.h:103
I2C4_EV_IRQn
@ I2C4_EV_IRQn
Definition: stm32l4a6xx.h:161
USART1_IRQn
@ USART1_IRQn
Definition: stm32l4a6xx.h:115
COMP_IRQn
@ COMP_IRQn
Definition: stm32l4a6xx.h:142
DMA2_Channel3_IRQn
@ DMA2_Channel3_IRQn
Definition: stm32l4a6xx.h:136
EXTI3_IRQn
@ EXTI3_IRQn
Definition: stm32l4a6xx.h:87
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: stm32l4a6xx.h:68
UART4_IRQn
@ UART4_IRQn
Definition: stm32l4a6xx.h:130
PVD_PVM_IRQn
@ PVD_PVM_IRQn
Definition: stm32l4a6xx.h:79
DMA1_Channel4_IRQn
@ DMA1_Channel4_IRQn
Definition: stm32l4a6xx.h:92
EXTI1_IRQn
@ EXTI1_IRQn
Definition: stm32l4a6xx.h:85
TIM5_IRQn
@ TIM5_IRQn
Definition: stm32l4a6xx.h:128
TIM8_UP_IRQn
@ TIM8_UP_IRQn
Definition: stm32l4a6xx.h:122
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition: stm32l4a6xx.h:105
LPUART1_IRQn
@ LPUART1_IRQn
Definition: stm32l4a6xx.h:148
CAN2_TX_IRQn
@ CAN2_TX_IRQn
Definition: stm32l4a6xx.h:164
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition: stm32l4a6xx.h:99
USART3_IRQn
@ USART3_IRQn
Definition: stm32l4a6xx.h:117
TSC_IRQn
@ TSC_IRQn
Definition: stm32l4a6xx.h:155
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition: stm32l4a6xx.h:119
DFSDM1_FLT1_IRQn
@ DFSDM1_FLT1_IRQn
Definition: stm32l4a6xx.h:140
ADC_Common_TypeDef
Definition: stm32l4a6xx.h:230
ADC_Common_TypeDef::RESERVED
uint32_t RESERVED
Definition: stm32l4a6xx.h:232
ADC_Common_TypeDef::CDR
__IO uint32_t CDR
Definition: stm32l4a6xx.h:234
ADC_Common_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32l4a6xx.h:231
ADC_Common_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32l4a6xx.h:233
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32l4a6xx.h:188
ADC_TypeDef::SQR1
__IO uint32_t SQR1
Definition: stm32l4a6xx.h:201
ADC_TypeDef::AWD2CR
__IO uint32_t AWD2CR
Definition: stm32l4a6xx.h:220
ADC_TypeDef::TR1
__IO uint32_t TR1
Definition: stm32l4a6xx.h:197
ADC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32l4a6xx.h:207
ADC_TypeDef::CFGR2
__IO uint32_t CFGR2
Definition: stm32l4a6xx.h:193
ADC_TypeDef::RESERVED8
uint32_t RESERVED8
Definition: stm32l4a6xx.h:222
ADC_TypeDef::OFR3
__IO uint32_t OFR3
Definition: stm32l4a6xx.h:212
ADC_TypeDef::OFR4
__IO uint32_t OFR4
Definition: stm32l4a6xx.h:213
ADC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32l4a6xx.h:200
ADC_TypeDef::RESERVED9
uint32_t RESERVED9
Definition: stm32l4a6xx.h:223
ADC_TypeDef::AWD3CR
__IO uint32_t AWD3CR
Definition: stm32l4a6xx.h:221
ADC_TypeDef::JDR3
__IO uint32_t JDR3
Definition: stm32l4a6xx.h:217
ADC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32l4a6xx.h:192
ADC_TypeDef::SQR3
__IO uint32_t SQR3
Definition: stm32l4a6xx.h:203
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition: stm32l4a6xx.h:208
ADC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32l4a6xx.h:196
ADC_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:191
ADC_TypeDef::CALFACT
__IO uint32_t CALFACT
Definition: stm32l4a6xx.h:225
ADC_TypeDef::SQR2
__IO uint32_t SQR2
Definition: stm32l4a6xx.h:202
ADC_TypeDef::DIFSEL
__IO uint32_t DIFSEL
Definition: stm32l4a6xx.h:224
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition: stm32l4a6xx.h:194
ADC_TypeDef::IER
__IO uint32_t IER
Definition: stm32l4a6xx.h:190
ADC_TypeDef::DR
__IO uint32_t DR
Definition: stm32l4a6xx.h:205
ADC_TypeDef::JDR2
__IO uint32_t JDR2
Definition: stm32l4a6xx.h:216
ADC_TypeDef::OFR1
__IO uint32_t OFR1
Definition: stm32l4a6xx.h:210
ADC_TypeDef::SMPR2
__IO uint32_t SMPR2
Definition: stm32l4a6xx.h:195
ADC_TypeDef::TR3
__IO uint32_t TR3
Definition: stm32l4a6xx.h:199
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition: stm32l4a6xx.h:215
ADC_TypeDef::SQR4
__IO uint32_t SQR4
Definition: stm32l4a6xx.h:204
ADC_TypeDef::JDR4
__IO uint32_t JDR4
Definition: stm32l4a6xx.h:218
ADC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32l4a6xx.h:206
ADC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l4a6xx.h:189
ADC_TypeDef::OFR2
__IO uint32_t OFR2
Definition: stm32l4a6xx.h:211
ADC_TypeDef::TR2
__IO uint32_t TR2
Definition: stm32l4a6xx.h:198
AES_TypeDef
AES hardware accelerator.
Definition: stm32l4a6xx.h:1069
AES_TypeDef::SUSP3R
__IO uint32_t SUSP3R
Definition: stm32l4a6xx.h:1089
AES_TypeDef::IVR3
__IO uint32_t IVR3
Definition: stm32l4a6xx.h:1081
AES_TypeDef::KEYR1
__IO uint32_t KEYR1
Definition: stm32l4a6xx.h:1075
AES_TypeDef::KEYR2
__IO uint32_t KEYR2
Definition: stm32l4a6xx.h:1076
AES_TypeDef::KEYR6
__IO uint32_t KEYR6
Definition: stm32l4a6xx.h:1084
AES_TypeDef::KEYR0
__IO uint32_t KEYR0
Definition: stm32l4a6xx.h:1074
AES_TypeDef::SR
__IO uint32_t SR
Definition: stm32l4a6xx.h:1071
AES_TypeDef::IVR0
__IO uint32_t IVR0
Definition: stm32l4a6xx.h:1078
AES_TypeDef::IVR1
__IO uint32_t IVR1
Definition: stm32l4a6xx.h:1079
AES_TypeDef::KEYR7
__IO uint32_t KEYR7
Definition: stm32l4a6xx.h:1085
AES_TypeDef::DINR
__IO uint32_t DINR
Definition: stm32l4a6xx.h:1072
AES_TypeDef::DOUTR
__IO uint32_t DOUTR
Definition: stm32l4a6xx.h:1073
AES_TypeDef::SUSP5R
__IO uint32_t SUSP5R
Definition: stm32l4a6xx.h:1091
AES_TypeDef::SUSP7R
__IO uint32_t SUSP7R
Definition: stm32l4a6xx.h:1093
AES_TypeDef::SUSP4R
__IO uint32_t SUSP4R
Definition: stm32l4a6xx.h:1090
AES_TypeDef::SUSP2R
__IO uint32_t SUSP2R
Definition: stm32l4a6xx.h:1088
AES_TypeDef::SUSP6R
__IO uint32_t SUSP6R
Definition: stm32l4a6xx.h:1092
AES_TypeDef::IVR2
__IO uint32_t IVR2
Definition: stm32l4a6xx.h:1080
AES_TypeDef::KEYR5
__IO uint32_t KEYR5
Definition: stm32l4a6xx.h:1083
AES_TypeDef::KEYR3
__IO uint32_t KEYR3
Definition: stm32l4a6xx.h:1077
AES_TypeDef::KEYR4
__IO uint32_t KEYR4
Definition: stm32l4a6xx.h:1082
AES_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:1070
AES_TypeDef::SUSP0R
__IO uint32_t SUSP0R
Definition: stm32l4a6xx.h:1086
AES_TypeDef::SUSP1R
__IO uint32_t SUSP1R
Definition: stm32l4a6xx.h:1087
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32l4a6xx.h:273
CAN_FIFOMailBox_TypeDef::RIR
__IO uint32_t RIR
Definition: stm32l4a6xx.h:274
CAN_FIFOMailBox_TypeDef::RDTR
__IO uint32_t RDTR
Definition: stm32l4a6xx.h:275
CAN_FIFOMailBox_TypeDef::RDHR
__IO uint32_t RDHR
Definition: stm32l4a6xx.h:277
CAN_FIFOMailBox_TypeDef::RDLR
__IO uint32_t RDLR
Definition: stm32l4a6xx.h:276
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32l4a6xx.h:285
CAN_FilterRegister_TypeDef::FR2
__IO uint32_t FR2
Definition: stm32l4a6xx.h:287
CAN_FilterRegister_TypeDef::FR1
__IO uint32_t FR1
Definition: stm32l4a6xx.h:286
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32l4a6xx.h:261
CAN_TxMailBox_TypeDef::TIR
__IO uint32_t TIR
Definition: stm32l4a6xx.h:262
CAN_TxMailBox_TypeDef::TDTR
__IO uint32_t TDTR
Definition: stm32l4a6xx.h:263
CAN_TxMailBox_TypeDef::TDLR
__IO uint32_t TDLR
Definition: stm32l4a6xx.h:264
CAN_TxMailBox_TypeDef::TDHR
__IO uint32_t TDHR
Definition: stm32l4a6xx.h:265
CAN_TypeDef
Controller Area Network.
Definition: stm32l4a6xx.h:295
CAN_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32l4a6xx.h:296
CAN_TypeDef::FMR
__IO uint32_t FMR
Definition: stm32l4a6xx.h:308
CAN_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32l4a6xx.h:314
CAN_TypeDef::IER
__IO uint32_t IER
Definition: stm32l4a6xx.h:301
CAN_TypeDef::RF1R
__IO uint32_t RF1R
Definition: stm32l4a6xx.h:300
CAN_TypeDef::ESR
__IO uint32_t ESR
Definition: stm32l4a6xx.h:302
CAN_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32l4a6xx.h:310
CAN_TypeDef::FA1R
__IO uint32_t FA1R
Definition: stm32l4a6xx.h:315
CAN_TypeDef::FS1R
__IO uint32_t FS1R
Definition: stm32l4a6xx.h:311
CAN_TypeDef::TSR
__IO uint32_t TSR
Definition: stm32l4a6xx.h:298
CAN_TypeDef::BTR
__IO uint32_t BTR
Definition: stm32l4a6xx.h:303
CAN_TypeDef::RF0R
__IO uint32_t RF0R
Definition: stm32l4a6xx.h:299
CAN_TypeDef::FFA1R
__IO uint32_t FFA1R
Definition: stm32l4a6xx.h:313
CAN_TypeDef::FM1R
__IO uint32_t FM1R
Definition: stm32l4a6xx.h:309
CAN_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32l4a6xx.h:312
CAN_TypeDef::MSR
__IO uint32_t MSR
Definition: stm32l4a6xx.h:297
COMP_Common_TypeDef
Definition: stm32l4a6xx.h:331
COMP_Common_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32l4a6xx.h:332
COMP_TypeDef
Comparator.
Definition: stm32l4a6xx.h:326
COMP_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32l4a6xx.h:327
CRC_TypeDef
CRC calculation unit.
Definition: stm32l4a6xx.h:340
CRC_TypeDef::POL
__IO uint32_t POL
Definition: stm32l4a6xx.h:348
CRC_TypeDef::INIT
__IO uint32_t INIT
Definition: stm32l4a6xx.h:347
CRC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32l4a6xx.h:346
CRC_TypeDef::DR
__IO uint32_t DR
Definition: stm32l4a6xx.h:341
CRC_TypeDef::RESERVED0
uint8_t RESERVED0
Definition: stm32l4a6xx.h:343
CRC_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32l4a6xx.h:344
CRC_TypeDef::IDR
__IO uint8_t IDR
Definition: stm32l4a6xx.h:342
CRC_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:345
CRS_TypeDef
Clock Recovery System.
Definition: stm32l4a6xx.h:355
CRS_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l4a6xx.h:358
CRS_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32l4a6xx.h:359
CRS_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:356
CRS_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32l4a6xx.h:357
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32l4a6xx.h:367
DAC_TypeDef::DHR8RD
__IO uint32_t DHR8RD
Definition: stm32l4a6xx.h:378
DAC_TypeDef::DOR2
__IO uint32_t DOR2
Definition: stm32l4a6xx.h:380
DAC_TypeDef::SR
__IO uint32_t SR
Definition: stm32l4a6xx.h:381
DAC_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:368
DAC_TypeDef::DHR8R1
__IO uint32_t DHR8R1
Definition: stm32l4a6xx.h:372
DAC_TypeDef::DHR8R2
__IO uint32_t DHR8R2
Definition: stm32l4a6xx.h:375
DAC_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32l4a6xx.h:383
DAC_TypeDef::SWTRIGR
__IO uint32_t SWTRIGR
Definition: stm32l4a6xx.h:369
DAC_TypeDef::DOR1
__IO uint32_t DOR1
Definition: stm32l4a6xx.h:379
DAC_TypeDef::DHR12L1
__IO uint32_t DHR12L1
Definition: stm32l4a6xx.h:371
DAC_TypeDef::SHHR
__IO uint32_t SHHR
Definition: stm32l4a6xx.h:386
DAC_TypeDef::SHSR2
__IO uint32_t SHSR2
Definition: stm32l4a6xx.h:385
DAC_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32l4a6xx.h:382
DAC_TypeDef::DHR12L2
__IO uint32_t DHR12L2
Definition: stm32l4a6xx.h:374
DAC_TypeDef::SHSR1
__IO uint32_t SHSR1
Definition: stm32l4a6xx.h:384
DAC_TypeDef::DHR12R2
__IO uint32_t DHR12R2
Definition: stm32l4a6xx.h:373
DAC_TypeDef::SHRR
__IO uint32_t SHRR
Definition: stm32l4a6xx.h:387
DAC_TypeDef::DHR12LD
__IO uint32_t DHR12LD
Definition: stm32l4a6xx.h:377
DAC_TypeDef::DHR12R1
__IO uint32_t DHR12R1
Definition: stm32l4a6xx.h:370
DAC_TypeDef::DHR12RD
__IO uint32_t DHR12RD
Definition: stm32l4a6xx.h:376
DBGMCU_TypeDef
Debug MCU.
Definition: stm32l4a6xx.h:430
DBGMCU_TypeDef::APB2FZ
__IO uint32_t APB2FZ
Definition: stm32l4a6xx.h:435
DBGMCU_TypeDef::APB1FZR2
__IO uint32_t APB1FZR2
Definition: stm32l4a6xx.h:434
DBGMCU_TypeDef::IDCODE
__IO uint32_t IDCODE
Definition: stm32l4a6xx.h:431
DBGMCU_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:432
DBGMCU_TypeDef::APB1FZR1
__IO uint32_t APB1FZR1
Definition: stm32l4a6xx.h:433
DCMI_TypeDef
DCMI.
Definition: stm32l4a6xx.h:242
DCMI_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32l4a6xx.h:248
DCMI_TypeDef::CWSIZER
__IO uint32_t CWSIZER
Definition: stm32l4a6xx.h:252
DCMI_TypeDef::SR
__IO uint32_t SR
Definition: stm32l4a6xx.h:244
DCMI_TypeDef::DR
__IO uint32_t DR
Definition: stm32l4a6xx.h:253
DCMI_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:243
DCMI_TypeDef::CWSTRTR
__IO uint32_t CWSTRTR
Definition: stm32l4a6xx.h:251
DCMI_TypeDef::ESCR
__IO uint32_t ESCR
Definition: stm32l4a6xx.h:249
DCMI_TypeDef::IER
__IO uint32_t IER
Definition: stm32l4a6xx.h:246
DCMI_TypeDef::MISR
__IO uint32_t MISR
Definition: stm32l4a6xx.h:247
DCMI_TypeDef::RISR
__IO uint32_t RISR
Definition: stm32l4a6xx.h:245
DCMI_TypeDef::ESUR
__IO uint32_t ESUR
Definition: stm32l4a6xx.h:250
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition: stm32l4a6xx.h:416
DFSDM_Channel_TypeDef::CHCFGR2
__IO uint32_t CHCFGR2
Definition: stm32l4a6xx.h:418
DFSDM_Channel_TypeDef::CHAWSCDR
__IO uint32_t CHAWSCDR
Definition: stm32l4a6xx.h:419
DFSDM_Channel_TypeDef::CHWDATAR
__IO uint32_t CHWDATAR
Definition: stm32l4a6xx.h:421
DFSDM_Channel_TypeDef::CHDATINR
__IO uint32_t CHDATINR
Definition: stm32l4a6xx.h:422
DFSDM_Channel_TypeDef::CHCFGR1
__IO uint32_t CHCFGR1
Definition: stm32l4a6xx.h:417
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition: stm32l4a6xx.h:394
DFSDM_Filter_TypeDef::FLTEXMAX
__IO uint32_t FLTEXMAX
Definition: stm32l4a6xx.h:407
DFSDM_Filter_TypeDef::FLTAWSR
__IO uint32_t FLTAWSR
Definition: stm32l4a6xx.h:405
DFSDM_Filter_TypeDef::FLTAWCFR
__IO uint32_t FLTAWCFR
Definition: stm32l4a6xx.h:406
DFSDM_Filter_TypeDef::FLTJDATAR
__IO uint32_t FLTJDATAR
Definition: stm32l4a6xx.h:401
DFSDM_Filter_TypeDef::FLTISR
__IO uint32_t FLTISR
Definition: stm32l4a6xx.h:397
DFSDM_Filter_TypeDef::FLTAWLTR
__IO uint32_t FLTAWLTR
Definition: stm32l4a6xx.h:404
DFSDM_Filter_TypeDef::FLTRDATAR
__IO uint32_t FLTRDATAR
Definition: stm32l4a6xx.h:402
DFSDM_Filter_TypeDef::FLTFCR
__IO uint32_t FLTFCR
Definition: stm32l4a6xx.h:400
DFSDM_Filter_TypeDef::FLTJCHGR
__IO uint32_t FLTJCHGR
Definition: stm32l4a6xx.h:399
DFSDM_Filter_TypeDef::FLTEXMIN
__IO uint32_t FLTEXMIN
Definition: stm32l4a6xx.h:408
DFSDM_Filter_TypeDef::FLTCR2
__IO uint32_t FLTCR2
Definition: stm32l4a6xx.h:396
DFSDM_Filter_TypeDef::FLTICR
__IO uint32_t FLTICR
Definition: stm32l4a6xx.h:398
DFSDM_Filter_TypeDef::FLTCR1
__IO uint32_t FLTCR1
Definition: stm32l4a6xx.h:395
DFSDM_Filter_TypeDef::FLTCNVTIMR
__IO uint32_t FLTCNVTIMR
Definition: stm32l4a6xx.h:409
DFSDM_Filter_TypeDef::FLTAWHTR
__IO uint32_t FLTAWHTR
Definition: stm32l4a6xx.h:403
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32l4a6xx.h:471
DMA2D_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l4a6xx.h:473
DMA2D_TypeDef::OCOLR
__IO uint32_t OCOLR
Definition: stm32l4a6xx.h:486
DMA2D_TypeDef::OOR
__IO uint32_t OOR
Definition: stm32l4a6xx.h:488
DMA2D_TypeDef::BGPFCCR
__IO uint32_t BGPFCCR
Definition: stm32l4a6xx.h:481
DMA2D_TypeDef::OMAR
__IO uint32_t OMAR
Definition: stm32l4a6xx.h:487
DMA2D_TypeDef::OPFCCR
__IO uint32_t OPFCCR
Definition: stm32l4a6xx.h:485
DMA2D_TypeDef::AMTCR
__IO uint32_t AMTCR
Definition: stm32l4a6xx.h:491
DMA2D_TypeDef::BGCMAR
__IO uint32_t BGCMAR
Definition: stm32l4a6xx.h:484
DMA2D_TypeDef::FGCOLR
__IO uint32_t FGCOLR
Definition: stm32l4a6xx.h:480
DMA2D_TypeDef::FGMAR
__IO uint32_t FGMAR
Definition: stm32l4a6xx.h:475
DMA2D_TypeDef::BGOR
__IO uint32_t BGOR
Definition: stm32l4a6xx.h:478
DMA2D_TypeDef::NLR
__IO uint32_t NLR
Definition: stm32l4a6xx.h:489
DMA2D_TypeDef::FGOR
__IO uint32_t FGOR
Definition: stm32l4a6xx.h:476
DMA2D_TypeDef::BGMAR
__IO uint32_t BGMAR
Definition: stm32l4a6xx.h:477
DMA2D_TypeDef::BGCOLR
__IO uint32_t BGCOLR
Definition: stm32l4a6xx.h:482
DMA2D_TypeDef::LWR
__IO uint32_t LWR
Definition: stm32l4a6xx.h:490
DMA2D_TypeDef::FGPFCCR
__IO uint32_t FGPFCCR
Definition: stm32l4a6xx.h:479
DMA2D_TypeDef::IFCR
__IO uint32_t IFCR
Definition: stm32l4a6xx.h:474
DMA2D_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:472
DMA2D_TypeDef::FGCMAR
__IO uint32_t FGCMAR
Definition: stm32l4a6xx.h:483
DMA_Channel_TypeDef
DMA Controller.
Definition: stm32l4a6xx.h:444
DMA_Channel_TypeDef::CMAR
__IO uint32_t CMAR
Definition: stm32l4a6xx.h:448
DMA_Channel_TypeDef::CPAR
__IO uint32_t CPAR
Definition: stm32l4a6xx.h:447
DMA_Channel_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32l4a6xx.h:445
DMA_Channel_TypeDef::CNDTR
__IO uint32_t CNDTR
Definition: stm32l4a6xx.h:446
DMA_Request_TypeDef
Definition: stm32l4a6xx.h:458
DMA_Request_TypeDef::CSELR
__IO uint32_t CSELR
Definition: stm32l4a6xx.h:459
DMA_TypeDef
Definition: stm32l4a6xx.h:452
DMA_TypeDef::IFCR
__IO uint32_t IFCR
Definition: stm32l4a6xx.h:454
DMA_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l4a6xx.h:453
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32l4a6xx.h:502
EXTI_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32l4a6xx.h:509
EXTI_TypeDef::IMR2
__IO uint32_t IMR2
Definition: stm32l4a6xx.h:511
EXTI_TypeDef::EMR2
__IO uint32_t EMR2
Definition: stm32l4a6xx.h:512
EXTI_TypeDef::FTSR1
__IO uint32_t FTSR1
Definition: stm32l4a6xx.h:506
EXTI_TypeDef::EMR1
__IO uint32_t EMR1
Definition: stm32l4a6xx.h:504
EXTI_TypeDef::PR1
__IO uint32_t PR1
Definition: stm32l4a6xx.h:508
EXTI_TypeDef::FTSR2
__IO uint32_t FTSR2
Definition: stm32l4a6xx.h:514
EXTI_TypeDef::IMR1
__IO uint32_t IMR1
Definition: stm32l4a6xx.h:503
EXTI_TypeDef::PR2
__IO uint32_t PR2
Definition: stm32l4a6xx.h:516
EXTI_TypeDef::RTSR2
__IO uint32_t RTSR2
Definition: stm32l4a6xx.h:513
EXTI_TypeDef::SWIER2
__IO uint32_t SWIER2
Definition: stm32l4a6xx.h:515
EXTI_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32l4a6xx.h:510
EXTI_TypeDef::SWIER1
__IO uint32_t SWIER1
Definition: stm32l4a6xx.h:507
EXTI_TypeDef::RTSR1
__IO uint32_t RTSR1
Definition: stm32l4a6xx.h:505
FIREWALL_TypeDef
Firewall.
Definition: stm32l4a6xx.h:525
FIREWALL_TypeDef::NVDSSA
__IO uint32_t NVDSSA
Definition: stm32l4a6xx.h:528
FIREWALL_TypeDef::NVDSL
__IO uint32_t NVDSL
Definition: stm32l4a6xx.h:529
FIREWALL_TypeDef::VDSSA
__IO uint32_t VDSSA
Definition: stm32l4a6xx.h:530
FIREWALL_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32l4a6xx.h:533
FIREWALL_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:534
FIREWALL_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32l4a6xx.h:532
FIREWALL_TypeDef::CSL
__IO uint32_t CSL
Definition: stm32l4a6xx.h:527
FIREWALL_TypeDef::VDSL
__IO uint32_t VDSL
Definition: stm32l4a6xx.h:531
FIREWALL_TypeDef::CSSA
__IO uint32_t CSSA
Definition: stm32l4a6xx.h:526
FLASH_TypeDef
FLASH Registers.
Definition: stm32l4a6xx.h:543
FLASH_TypeDef::RESERVED1
__IO uint32_t RESERVED1
Definition: stm32l4a6xx.h:551
FLASH_TypeDef::PCROP2SR
__IO uint32_t PCROP2SR
Definition: stm32l4a6xx.h:558
FLASH_TypeDef::PDKEYR
__IO uint32_t PDKEYR
Definition: stm32l4a6xx.h:545
FLASH_TypeDef::WRP1BR
__IO uint32_t WRP1BR
Definition: stm32l4a6xx.h:556
FLASH_TypeDef::ECCR
__IO uint32_t ECCR
Definition: stm32l4a6xx.h:550
FLASH_TypeDef::WRP2BR
__IO uint32_t WRP2BR
Definition: stm32l4a6xx.h:561
FLASH_TypeDef::PCROP1ER
__IO uint32_t PCROP1ER
Definition: stm32l4a6xx.h:554
FLASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32l4a6xx.h:548
FLASH_TypeDef::PCROP1SR
__IO uint32_t PCROP1SR
Definition: stm32l4a6xx.h:553
FLASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:549
FLASH_TypeDef::OPTKEYR
__IO uint32_t OPTKEYR
Definition: stm32l4a6xx.h:547
FLASH_TypeDef::KEYR
__IO uint32_t KEYR
Definition: stm32l4a6xx.h:546
FLASH_TypeDef::WRP1AR
__IO uint32_t WRP1AR
Definition: stm32l4a6xx.h:555
FLASH_TypeDef::PCROP2ER
__IO uint32_t PCROP2ER
Definition: stm32l4a6xx.h:559
FLASH_TypeDef::ACR
__IO uint32_t ACR
Definition: stm32l4a6xx.h:544
FLASH_TypeDef::OPTR
__IO uint32_t OPTR
Definition: stm32l4a6xx.h:552
FLASH_TypeDef::WRP2AR
__IO uint32_t WRP2AR
Definition: stm32l4a6xx.h:560
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32l4a6xx.h:570
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32l4a6xx.h:579
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32l4a6xx.h:588
FMC_Bank3_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32l4a6xx.h:593
FMC_Bank3_TypeDef::SR
__IO uint32_t SR
Definition: stm32l4a6xx.h:590
FMC_Bank3_TypeDef::PATT
__IO uint32_t PATT
Definition: stm32l4a6xx.h:592
FMC_Bank3_TypeDef::ECCR
__IO uint32_t ECCR
Definition: stm32l4a6xx.h:594
FMC_Bank3_TypeDef::PCR
__IO uint32_t PCR
Definition: stm32l4a6xx.h:589
FMC_Bank3_TypeDef::PMEM
__IO uint32_t PMEM
Definition: stm32l4a6xx.h:591
GPIO_TypeDef
General Purpose I/O.
Definition: stm32l4a6xx.h:602
GPIO_TypeDef::OSPEEDR
__IO uint32_t OSPEEDR
Definition: stm32l4a6xx.h:605
GPIO_TypeDef::PUPDR
__IO uint32_t PUPDR
Definition: stm32l4a6xx.h:606
GPIO_TypeDef::ODR
__IO uint32_t ODR
Definition: stm32l4a6xx.h:608
GPIO_TypeDef::OTYPER
__IO uint32_t OTYPER
Definition: stm32l4a6xx.h:604
GPIO_TypeDef::LCKR
__IO uint32_t LCKR
Definition: stm32l4a6xx.h:610
GPIO_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32l4a6xx.h:612
GPIO_TypeDef::MODER
__IO uint32_t MODER
Definition: stm32l4a6xx.h:603
GPIO_TypeDef::BSRR
__IO uint32_t BSRR
Definition: stm32l4a6xx.h:609
GPIO_TypeDef::IDR
__IO uint32_t IDR
Definition: stm32l4a6xx.h:607
HASH_DIGEST_TypeDef
HASH_DIGEST.
Definition: stm32l4a6xx.h:1117
HASH_TypeDef
HASH.
Definition: stm32l4a6xx.h:1101
HASH_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32l4a6xx.h:1106
HASH_TypeDef::STR
__IO uint32_t STR
Definition: stm32l4a6xx.h:1104
HASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32l4a6xx.h:1107
HASH_TypeDef::DIN
__IO uint32_t DIN
Definition: stm32l4a6xx.h:1103
HASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:1102
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32l4a6xx.h:622
I2C_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l4a6xx.h:629
I2C_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32l4a6xx.h:624
I2C_TypeDef::RXDR
__IO uint32_t RXDR
Definition: stm32l4a6xx.h:632
I2C_TypeDef::PECR
__IO uint32_t PECR
Definition: stm32l4a6xx.h:631
I2C_TypeDef::OAR2
__IO uint32_t OAR2
Definition: stm32l4a6xx.h:626
I2C_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32l4a6xx.h:630
I2C_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32l4a6xx.h:623
I2C_TypeDef::TIMINGR
__IO uint32_t TIMINGR
Definition: stm32l4a6xx.h:627
I2C_TypeDef::TIMEOUTR
__IO uint32_t TIMEOUTR
Definition: stm32l4a6xx.h:628
I2C_TypeDef::TXDR
__IO uint32_t TXDR
Definition: stm32l4a6xx.h:633
I2C_TypeDef::OAR1
__IO uint32_t OAR1
Definition: stm32l4a6xx.h:625
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32l4a6xx.h:641
IWDG_TypeDef::PR
__IO uint32_t PR
Definition: stm32l4a6xx.h:643
IWDG_TypeDef::KR
__IO uint32_t KR
Definition: stm32l4a6xx.h:642
IWDG_TypeDef::WINR
__IO uint32_t WINR
Definition: stm32l4a6xx.h:646
IWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32l4a6xx.h:645
IWDG_TypeDef::RLR
__IO uint32_t RLR
Definition: stm32l4a6xx.h:644
LCD_TypeDef
LCD.
Definition: stm32l4a6xx.h:654
LCD_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:655
LCD_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32l4a6xx.h:656
LCD_TypeDef::CLR
__IO uint32_t CLR
Definition: stm32l4a6xx.h:658
LCD_TypeDef::RESERVED
uint32_t RESERVED
Definition: stm32l4a6xx.h:659
LCD_TypeDef::SR
__IO uint32_t SR
Definition: stm32l4a6xx.h:657
LPTIM_TypeDef
LPTIMER.
Definition: stm32l4a6xx.h:667
LPTIM_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32l4a6xx.h:669
LPTIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32l4a6xx.h:674
LPTIM_TypeDef::CMP
__IO uint32_t CMP
Definition: stm32l4a6xx.h:673
LPTIM_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32l4a6xx.h:671
LPTIM_TypeDef::OR
__IO uint32_t OR
Definition: stm32l4a6xx.h:676
LPTIM_TypeDef::IER
__IO uint32_t IER
Definition: stm32l4a6xx.h:670
LPTIM_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l4a6xx.h:668
LPTIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32l4a6xx.h:675
LPTIM_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:672
OPAMP_Common_TypeDef
Definition: stm32l4a6xx.h:691
OPAMP_Common_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32l4a6xx.h:692
OPAMP_TypeDef
Operational Amplifier (OPAMP)
Definition: stm32l4a6xx.h:684
OPAMP_TypeDef::LPOTR
__IO uint32_t LPOTR
Definition: stm32l4a6xx.h:687
OPAMP_TypeDef::OTR
__IO uint32_t OTR
Definition: stm32l4a6xx.h:686
OPAMP_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32l4a6xx.h:685
PWR_TypeDef
Power Control.
Definition: stm32l4a6xx.h:700
PWR_TypeDef::PUCRG
__IO uint32_t PUCRG
Definition: stm32l4a6xx.h:721
PWR_TypeDef::SCR
__IO uint32_t SCR
Definition: stm32l4a6xx.h:707
PWR_TypeDef::SR2
__IO uint32_t SR2
Definition: stm32l4a6xx.h:706
PWR_TypeDef::PUCRF
__IO uint32_t PUCRF
Definition: stm32l4a6xx.h:719
PWR_TypeDef::SR1
__IO uint32_t SR1
Definition: stm32l4a6xx.h:705
PWR_TypeDef::CR4
__IO uint32_t CR4
Definition: stm32l4a6xx.h:704
PWR_TypeDef::PUCRC
__IO uint32_t PUCRC
Definition: stm32l4a6xx.h:713
PWR_TypeDef::PUCRB
__IO uint32_t PUCRB
Definition: stm32l4a6xx.h:711
PWR_TypeDef::PDCRH
__IO uint32_t PDCRH
Definition: stm32l4a6xx.h:724
PWR_TypeDef::PDCRF
__IO uint32_t PDCRF
Definition: stm32l4a6xx.h:720
PWR_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32l4a6xx.h:701
PWR_TypeDef::PUCRI
__IO uint32_t PUCRI
Definition: stm32l4a6xx.h:725
PWR_TypeDef::CR3
__IO uint32_t CR3
Definition: stm32l4a6xx.h:703
PWR_TypeDef::PUCRE
__IO uint32_t PUCRE
Definition: stm32l4a6xx.h:717
PWR_TypeDef::PDCRG
__IO uint32_t PDCRG
Definition: stm32l4a6xx.h:722
PWR_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32l4a6xx.h:702
PWR_TypeDef::PDCRI
__IO uint32_t PDCRI
Definition: stm32l4a6xx.h:726
PWR_TypeDef::PUCRH
__IO uint32_t PUCRH
Definition: stm32l4a6xx.h:723
PWR_TypeDef::PDCRB
__IO uint32_t PDCRB
Definition: stm32l4a6xx.h:712
PWR_TypeDef::RESERVED
uint32_t RESERVED
Definition: stm32l4a6xx.h:708
PWR_TypeDef::PUCRD
__IO uint32_t PUCRD
Definition: stm32l4a6xx.h:715
PWR_TypeDef::PDCRE
__IO uint32_t PDCRE
Definition: stm32l4a6xx.h:718
PWR_TypeDef::PDCRA
__IO uint32_t PDCRA
Definition: stm32l4a6xx.h:710
PWR_TypeDef::PUCRA
__IO uint32_t PUCRA
Definition: stm32l4a6xx.h:709
PWR_TypeDef::PDCRC
__IO uint32_t PDCRC
Definition: stm32l4a6xx.h:714
PWR_TypeDef::PDCRD
__IO uint32_t PDCRD
Definition: stm32l4a6xx.h:716
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32l4a6xx.h:735
QUADSPI_TypeDef::PSMAR
__IO uint32_t PSMAR
Definition: stm32l4a6xx.h:746
QUADSPI_TypeDef::DLR
__IO uint32_t DLR
Definition: stm32l4a6xx.h:740
QUADSPI_TypeDef::PIR
__IO uint32_t PIR
Definition: stm32l4a6xx.h:747
QUADSPI_TypeDef::PSMKR
__IO uint32_t PSMKR
Definition: stm32l4a6xx.h:745
QUADSPI_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32l4a6xx.h:737
QUADSPI_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32l4a6xx.h:741
QUADSPI_TypeDef::LPTR
__IO uint32_t LPTR
Definition: stm32l4a6xx.h:748
QUADSPI_TypeDef::AR
__IO uint32_t AR
Definition: stm32l4a6xx.h:742
QUADSPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32l4a6xx.h:738
QUADSPI_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32l4a6xx.h:739
QUADSPI_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:736
QUADSPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32l4a6xx.h:744
QUADSPI_TypeDef::ABR
__IO uint32_t ABR
Definition: stm32l4a6xx.h:743
RCC_TypeDef
Reset and Clock Control.
Definition: stm32l4a6xx.h:757
RCC_TypeDef::APB1RSTR2
__IO uint32_t APB1RSTR2
Definition: stm32l4a6xx.h:773
RCC_TypeDef::BDCR
__IO uint32_t BDCR
Definition: stm32l4a6xx.h:794
RCC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32l4a6xx.h:760
RCC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32l4a6xx.h:783
RCC_TypeDef::AHB3SMENR
__IO uint32_t AHB3SMENR
Definition: stm32l4a6xx.h:786
RCC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32l4a6xx.h:779
RCC_TypeDef::CRRCR
__IO uint32_t CRRCR
Definition: stm32l4a6xx.h:796
RCC_TypeDef::CICR
__IO uint32_t CICR
Definition: stm32l4a6xx.h:766
RCC_TypeDef::PLLCFGR
__IO uint32_t PLLCFGR
Definition: stm32l4a6xx.h:761
RCC_TypeDef::APB2SMENR
__IO uint32_t APB2SMENR
Definition: stm32l4a6xx.h:790
RCC_TypeDef::AHB1SMENR
__IO uint32_t AHB1SMENR
Definition: stm32l4a6xx.h:784
RCC_TypeDef::CCIPR2
__IO uint32_t CCIPR2
Definition: stm32l4a6xx.h:797
RCC_TypeDef::AHB2RSTR
__IO uint32_t AHB2RSTR
Definition: stm32l4a6xx.h:769
RCC_TypeDef::RESERVED7
uint32_t RESERVED7
Definition: stm32l4a6xx.h:793
RCC_TypeDef::AHB3RSTR
__IO uint32_t AHB3RSTR
Definition: stm32l4a6xx.h:770
RCC_TypeDef::APB2RSTR
__IO uint32_t APB2RSTR
Definition: stm32l4a6xx.h:774
RCC_TypeDef::ICSCR
__IO uint32_t ICSCR
Definition: stm32l4a6xx.h:759
RCC_TypeDef::APB2ENR
__IO uint32_t APB2ENR
Definition: stm32l4a6xx.h:782
RCC_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32l4a6xx.h:767
RCC_TypeDef::CIER
__IO uint32_t CIER
Definition: stm32l4a6xx.h:764
RCC_TypeDef::APB1SMENR2
__IO uint32_t APB1SMENR2
Definition: stm32l4a6xx.h:789
RCC_TypeDef::PLLSAI2CFGR
__IO uint32_t PLLSAI2CFGR
Definition: stm32l4a6xx.h:763
RCC_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32l4a6xx.h:795
RCC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32l4a6xx.h:775
RCC_TypeDef::PLLSAI1CFGR
__IO uint32_t PLLSAI1CFGR
Definition: stm32l4a6xx.h:762
RCC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32l4a6xx.h:771
RCC_TypeDef::RESERVED5
uint32_t RESERVED5
Definition: stm32l4a6xx.h:787
RCC_TypeDef::APB1ENR2
__IO uint32_t APB1ENR2
Definition: stm32l4a6xx.h:781
RCC_TypeDef::CCIPR
__IO uint32_t CCIPR
Definition: stm32l4a6xx.h:792
RCC_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:758
RCC_TypeDef::RESERVED6
uint32_t RESERVED6
Definition: stm32l4a6xx.h:791
RCC_TypeDef::AHB3ENR
__IO uint32_t AHB3ENR
Definition: stm32l4a6xx.h:778
RCC_TypeDef::AHB1RSTR
__IO uint32_t AHB1RSTR
Definition: stm32l4a6xx.h:768
RCC_TypeDef::APB1RSTR1
__IO uint32_t APB1RSTR1
Definition: stm32l4a6xx.h:772
RCC_TypeDef::APB1SMENR1
__IO uint32_t APB1SMENR1
Definition: stm32l4a6xx.h:788
RCC_TypeDef::APB1ENR1
__IO uint32_t APB1ENR1
Definition: stm32l4a6xx.h:780
RCC_TypeDef::AHB2SMENR
__IO uint32_t AHB2SMENR
Definition: stm32l4a6xx.h:785
RCC_TypeDef::AHB2ENR
__IO uint32_t AHB2ENR
Definition: stm32l4a6xx.h:777
RCC_TypeDef::AHB1ENR
__IO uint32_t AHB1ENR
Definition: stm32l4a6xx.h:776
RCC_TypeDef::CIFR
__IO uint32_t CIFR
Definition: stm32l4a6xx.h:765
RNG_TypeDef
RNG.
Definition: stm32l4a6xx.h:1126
RNG_TypeDef::SR
__IO uint32_t SR
Definition: stm32l4a6xx.h:1128
RNG_TypeDef::DR
__IO uint32_t DR
Definition: stm32l4a6xx.h:1129
RNG_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:1127
RTC_TypeDef
Real-Time Clock.
Definition: stm32l4a6xx.h:805
RTC_TypeDef::BKP25R
__IO uint32_t BKP25R
Definition: stm32l4a6xx.h:851
RTC_TypeDef::BKP8R
__IO uint32_t BKP8R
Definition: stm32l4a6xx.h:834
RTC_TypeDef::BKP5R
__IO uint32_t BKP5R
Definition: stm32l4a6xx.h:831
RTC_TypeDef::BKP13R
__IO uint32_t BKP13R
Definition: stm32l4a6xx.h:839
RTC_TypeDef::BKP21R
__IO uint32_t BKP21R
Definition: stm32l4a6xx.h:847
RTC_TypeDef::BKP18R
__IO uint32_t BKP18R
Definition: stm32l4a6xx.h:844
RTC_TypeDef::BKP16R
__IO uint32_t BKP16R
Definition: stm32l4a6xx.h:842
RTC_TypeDef::TSTR
__IO uint32_t TSTR
Definition: stm32l4a6xx.h:818
RTC_TypeDef::TSSSR
__IO uint32_t TSSSR
Definition: stm32l4a6xx.h:820
RTC_TypeDef::ALRMBSSR
__IO uint32_t ALRMBSSR
Definition: stm32l4a6xx.h:824
RTC_TypeDef::TR
__IO uint32_t TR
Definition: stm32l4a6xx.h:806
RTC_TypeDef::BKP30R
__IO uint32_t BKP30R
Definition: stm32l4a6xx.h:856
RTC_TypeDef::reserved
uint32_t reserved
Definition: stm32l4a6xx.h:812
RTC_TypeDef::BKP20R
__IO uint32_t BKP20R
Definition: stm32l4a6xx.h:846
RTC_TypeDef::BKP31R
__IO uint32_t BKP31R
Definition: stm32l4a6xx.h:857
RTC_TypeDef::BKP1R
__IO uint32_t BKP1R
Definition: stm32l4a6xx.h:827
RTC_TypeDef::BKP27R
__IO uint32_t BKP27R
Definition: stm32l4a6xx.h:853
RTC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l4a6xx.h:809
RTC_TypeDef::PRER
__IO uint32_t PRER
Definition: stm32l4a6xx.h:810
RTC_TypeDef::BKP10R
__IO uint32_t BKP10R
Definition: stm32l4a6xx.h:836
RTC_TypeDef::SHIFTR
__IO uint32_t SHIFTR
Definition: stm32l4a6xx.h:817
RTC_TypeDef::BKP4R
__IO uint32_t BKP4R
Definition: stm32l4a6xx.h:830
RTC_TypeDef::BKP12R
__IO uint32_t BKP12R
Definition: stm32l4a6xx.h:838
RTC_TypeDef::BKP22R
__IO uint32_t BKP22R
Definition: stm32l4a6xx.h:848
RTC_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:808
RTC_TypeDef::BKP6R
__IO uint32_t BKP6R
Definition: stm32l4a6xx.h:832
RTC_TypeDef::BKP23R
__IO uint32_t BKP23R
Definition: stm32l4a6xx.h:849
RTC_TypeDef::BKP15R
__IO uint32_t BKP15R
Definition: stm32l4a6xx.h:841
RTC_TypeDef::DR
__IO uint32_t DR
Definition: stm32l4a6xx.h:807
RTC_TypeDef::BKP11R
__IO uint32_t BKP11R
Definition: stm32l4a6xx.h:837
RTC_TypeDef::BKP17R
__IO uint32_t BKP17R
Definition: stm32l4a6xx.h:843
RTC_TypeDef::ALRMBR
__IO uint32_t ALRMBR
Definition: stm32l4a6xx.h:814
RTC_TypeDef::BKP7R
__IO uint32_t BKP7R
Definition: stm32l4a6xx.h:833
RTC_TypeDef::BKP19R
__IO uint32_t BKP19R
Definition: stm32l4a6xx.h:845
RTC_TypeDef::BKP29R
__IO uint32_t BKP29R
Definition: stm32l4a6xx.h:855
RTC_TypeDef::TSDR
__IO uint32_t TSDR
Definition: stm32l4a6xx.h:819
RTC_TypeDef::BKP2R
__IO uint32_t BKP2R
Definition: stm32l4a6xx.h:828
RTC_TypeDef::BKP26R
__IO uint32_t BKP26R
Definition: stm32l4a6xx.h:852
RTC_TypeDef::BKP0R
__IO uint32_t BKP0R
Definition: stm32l4a6xx.h:826
RTC_TypeDef::BKP9R
__IO uint32_t BKP9R
Definition: stm32l4a6xx.h:835
RTC_TypeDef::BKP28R
__IO uint32_t BKP28R
Definition: stm32l4a6xx.h:854
RTC_TypeDef::BKP24R
__IO uint32_t BKP24R
Definition: stm32l4a6xx.h:850
RTC_TypeDef::TAMPCR
__IO uint32_t TAMPCR
Definition: stm32l4a6xx.h:822
RTC_TypeDef::BKP3R
__IO uint32_t BKP3R
Definition: stm32l4a6xx.h:829
RTC_TypeDef::OR
__IO uint32_t OR
Definition: stm32l4a6xx.h:825
RTC_TypeDef::ALRMASSR
__IO uint32_t ALRMASSR
Definition: stm32l4a6xx.h:823
RTC_TypeDef::WPR
__IO uint32_t WPR
Definition: stm32l4a6xx.h:815
RTC_TypeDef::ALRMAR
__IO uint32_t ALRMAR
Definition: stm32l4a6xx.h:813
RTC_TypeDef::WUTR
__IO uint32_t WUTR
Definition: stm32l4a6xx.h:811
RTC_TypeDef::BKP14R
__IO uint32_t BKP14R
Definition: stm32l4a6xx.h:840
RTC_TypeDef::CALR
__IO uint32_t CALR
Definition: stm32l4a6xx.h:821
RTC_TypeDef::SSR
__IO uint32_t SSR
Definition: stm32l4a6xx.h:816
SAI_Block_TypeDef
Definition: stm32l4a6xx.h:870
SAI_Block_TypeDef::CLRFR
__IO uint32_t CLRFR
Definition: stm32l4a6xx.h:877
SAI_Block_TypeDef::FRCR
__IO uint32_t FRCR
Definition: stm32l4a6xx.h:873
SAI_Block_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32l4a6xx.h:871
SAI_Block_TypeDef::DR
__IO uint32_t DR
Definition: stm32l4a6xx.h:878
SAI_Block_TypeDef::SLOTR
__IO uint32_t SLOTR
Definition: stm32l4a6xx.h:874
SAI_Block_TypeDef::SR
__IO uint32_t SR
Definition: stm32l4a6xx.h:876
SAI_Block_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32l4a6xx.h:872
SAI_Block_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32l4a6xx.h:875
SAI_TypeDef
Serial Audio Interface.
Definition: stm32l4a6xx.h:865
SAI_TypeDef::GCR
__IO uint32_t GCR
Definition: stm32l4a6xx.h:866
SDMMC_TypeDef
Secure digital input/output Interface.
Definition: stm32l4a6xx.h:887
SDMMC_TypeDef::FIFOCNT
__I uint32_t FIFOCNT
Definition: stm32l4a6xx.h:905
SDMMC_TypeDef::RESPCMD
__I uint32_t RESPCMD
Definition: stm32l4a6xx.h:892
SDMMC_TypeDef::RESP2
__I uint32_t RESP2
Definition: stm32l4a6xx.h:894
SDMMC_TypeDef::DLEN
__IO uint32_t DLEN
Definition: stm32l4a6xx.h:898
SDMMC_TypeDef::MASK
__IO uint32_t MASK
Definition: stm32l4a6xx.h:903
SDMMC_TypeDef::DCOUNT
__I uint32_t DCOUNT
Definition: stm32l4a6xx.h:900
SDMMC_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32l4a6xx.h:902
SDMMC_TypeDef::STA
__I uint32_t STA
Definition: stm32l4a6xx.h:901
SDMMC_TypeDef::DCTRL
__IO uint32_t DCTRL
Definition: stm32l4a6xx.h:899
SDMMC_TypeDef::ARG
__IO uint32_t ARG
Definition: stm32l4a6xx.h:890
SDMMC_TypeDef::POWER
__IO uint32_t POWER
Definition: stm32l4a6xx.h:888
SDMMC_TypeDef::DTIMER
__IO uint32_t DTIMER
Definition: stm32l4a6xx.h:897
SDMMC_TypeDef::FIFO
__IO uint32_t FIFO
Definition: stm32l4a6xx.h:907
SDMMC_TypeDef::CLKCR
__IO uint32_t CLKCR
Definition: stm32l4a6xx.h:889
SDMMC_TypeDef::RESP1
__I uint32_t RESP1
Definition: stm32l4a6xx.h:893
SDMMC_TypeDef::CMD
__IO uint32_t CMD
Definition: stm32l4a6xx.h:891
SDMMC_TypeDef::RESP3
__I uint32_t RESP3
Definition: stm32l4a6xx.h:895
SDMMC_TypeDef::RESP4
__I uint32_t RESP4
Definition: stm32l4a6xx.h:896
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32l4a6xx.h:916
SPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32l4a6xx.h:920
SPI_TypeDef::TXCRCR
__IO uint32_t TXCRCR
Definition: stm32l4a6xx.h:923
SPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32l4a6xx.h:919
SPI_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32l4a6xx.h:918
SPI_TypeDef::CRCPR
__IO uint32_t CRCPR
Definition: stm32l4a6xx.h:921
SPI_TypeDef::RXCRCR
__IO uint32_t RXCRCR
Definition: stm32l4a6xx.h:922
SPI_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32l4a6xx.h:917
SWPMI_TypeDef
Single Wire Protocol Master Interface SPWMI.
Definition: stm32l4a6xx.h:932
SWPMI_TypeDef::RFL
__IO uint32_t RFL
Definition: stm32l4a6xx.h:939
SWPMI_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32l4a6xx.h:934
SWPMI_TypeDef::RDR
__IO uint32_t RDR
Definition: stm32l4a6xx.h:941
SWPMI_TypeDef::TDR
__IO uint32_t TDR
Definition: stm32l4a6xx.h:940
SWPMI_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l4a6xx.h:936
SWPMI_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32l4a6xx.h:935
SWPMI_TypeDef::OR
__IO uint32_t OR
Definition: stm32l4a6xx.h:942
SWPMI_TypeDef::IER
__IO uint32_t IER
Definition: stm32l4a6xx.h:938
SWPMI_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:933
SWPMI_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32l4a6xx.h:937
SYSCFG_TypeDef
System configuration controller.
Definition: stm32l4a6xx.h:951
SYSCFG_TypeDef::CFGR1
__IO uint32_t CFGR1
Definition: stm32l4a6xx.h:953
SYSCFG_TypeDef::SCSR
__IO uint32_t SCSR
Definition: stm32l4a6xx.h:955
SYSCFG_TypeDef::MEMRMP
__IO uint32_t MEMRMP
Definition: stm32l4a6xx.h:952
SYSCFG_TypeDef::SWPR
__IO uint32_t SWPR
Definition: stm32l4a6xx.h:957
SYSCFG_TypeDef::CFGR2
__IO uint32_t CFGR2
Definition: stm32l4a6xx.h:956
SYSCFG_TypeDef::SKR
__IO uint32_t SKR
Definition: stm32l4a6xx.h:958
SYSCFG_TypeDef::SWPR2
__IO uint32_t SWPR2
Definition: stm32l4a6xx.h:959
TIM_TypeDef
TIM.
Definition: stm32l4a6xx.h:968
TIM_TypeDef::EGR
__IO uint32_t EGR
Definition: stm32l4a6xx.h:974
TIM_TypeDef::CCR1
__IO uint32_t CCR1
Definition: stm32l4a6xx.h:982
TIM_TypeDef::CCMR1
__IO uint32_t CCMR1
Definition: stm32l4a6xx.h:975
TIM_TypeDef::BDTR
__IO uint32_t BDTR
Definition: stm32l4a6xx.h:986
TIM_TypeDef::DIER
__IO uint32_t DIER
Definition: stm32l4a6xx.h:972
TIM_TypeDef::CCR6
__IO uint32_t CCR6
Definition: stm32l4a6xx.h:992
TIM_TypeDef::OR2
__IO uint32_t OR2
Definition: stm32l4a6xx.h:993
TIM_TypeDef::CCR2
__IO uint32_t CCR2
Definition: stm32l4a6xx.h:983
TIM_TypeDef::CCR4
__IO uint32_t CCR4
Definition: stm32l4a6xx.h:985
TIM_TypeDef::SMCR
__IO uint32_t SMCR
Definition: stm32l4a6xx.h:971
TIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32l4a6xx.h:980
TIM_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32l4a6xx.h:970
TIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32l4a6xx.h:978
TIM_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32l4a6xx.h:987
TIM_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32l4a6xx.h:969
TIM_TypeDef::OR3
__IO uint32_t OR3
Definition: stm32l4a6xx.h:994
TIM_TypeDef::CCMR2
__IO uint32_t CCMR2
Definition: stm32l4a6xx.h:976
TIM_TypeDef::CCMR3
__IO uint32_t CCMR3
Definition: stm32l4a6xx.h:990
TIM_TypeDef::CCR3
__IO uint32_t CCR3
Definition: stm32l4a6xx.h:984
TIM_TypeDef::SR
__IO uint32_t SR
Definition: stm32l4a6xx.h:973
TIM_TypeDef::PSC
__IO uint32_t PSC
Definition: stm32l4a6xx.h:979
TIM_TypeDef::RCR
__IO uint32_t RCR
Definition: stm32l4a6xx.h:981
TIM_TypeDef::CCER
__IO uint32_t CCER
Definition: stm32l4a6xx.h:977
TIM_TypeDef::OR1
__IO uint32_t OR1
Definition: stm32l4a6xx.h:989
TIM_TypeDef::CCR5
__IO uint32_t CCR5
Definition: stm32l4a6xx.h:991
TIM_TypeDef::DMAR
__IO uint32_t DMAR
Definition: stm32l4a6xx.h:988
TSC_TypeDef
Touch Sensing Controller (TSC)
Definition: stm32l4a6xx.h:1003
TSC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32l4a6xx.h:1013
TSC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32l4a6xx.h:1009
TSC_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32l4a6xx.h:1006
TSC_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:1004
TSC_TypeDef::IER
__IO uint32_t IER
Definition: stm32l4a6xx.h:1005
TSC_TypeDef::IOHCR
__IO uint32_t IOHCR
Definition: stm32l4a6xx.h:1008
TSC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32l4a6xx.h:1015
TSC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l4a6xx.h:1007
TSC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32l4a6xx.h:1011
TSC_TypeDef::IOSCR
__IO uint32_t IOSCR
Definition: stm32l4a6xx.h:1012
TSC_TypeDef::IOGCSR
__IO uint32_t IOGCSR
Definition: stm32l4a6xx.h:1016
TSC_TypeDef::IOCCR
__IO uint32_t IOCCR
Definition: stm32l4a6xx.h:1014
TSC_TypeDef::IOASCR
__IO uint32_t IOASCR
Definition: stm32l4a6xx.h:1010
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32l4a6xx.h:1025
USART_TypeDef::TDR
__IO uint16_t TDR
Definition: stm32l4a6xx.h:1039
USART_TypeDef::RESERVED3
uint16_t RESERVED3
Definition: stm32l4a6xx.h:1034
USART_TypeDef::RTOR
__IO uint32_t RTOR
Definition: stm32l4a6xx.h:1032
USART_TypeDef::RESERVED4
uint16_t RESERVED4
Definition: stm32l4a6xx.h:1038
USART_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32l4a6xx.h:1026
USART_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32l4a6xx.h:1029
USART_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l4a6xx.h:1035
USART_TypeDef::RQR
__IO uint16_t RQR
Definition: stm32l4a6xx.h:1033
USART_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32l4a6xx.h:1027
USART_TypeDef::RESERVED5
uint16_t RESERVED5
Definition: stm32l4a6xx.h:1040
USART_TypeDef::RDR
__IO uint16_t RDR
Definition: stm32l4a6xx.h:1037
USART_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32l4a6xx.h:1036
USART_TypeDef::GTPR
__IO uint16_t GTPR
Definition: stm32l4a6xx.h:1030
USART_TypeDef::CR3
__IO uint32_t CR3
Definition: stm32l4a6xx.h:1028
USART_TypeDef::RESERVED2
uint16_t RESERVED2
Definition: stm32l4a6xx.h:1031
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32l4a6xx.h:1170
USB_OTG_DeviceTypeDef::DVBUSDIS
__IO uint32_t DVBUSDIS
Definition: stm32l4a6xx.h:1181
USB_OTG_DeviceTypeDef::DCTL
__IO uint32_t DCTL
Definition: stm32l4a6xx.h:1172
USB_OTG_DeviceTypeDef::DSTS
__IO uint32_t DSTS
Definition: stm32l4a6xx.h:1173
USB_OTG_DeviceTypeDef::DAINTMSK
__IO uint32_t DAINTMSK
Definition: stm32l4a6xx.h:1178
USB_OTG_DeviceTypeDef::Reserved20
uint32_t Reserved20
Definition: stm32l4a6xx.h:1179
USB_OTG_DeviceTypeDef::Reserved40
uint32_t Reserved40
Definition: stm32l4a6xx.h:1187
USB_OTG_DeviceTypeDef::DAINT
__IO uint32_t DAINT
Definition: stm32l4a6xx.h:1177
USB_OTG_DeviceTypeDef::DIEPEMPMSK
__IO uint32_t DIEPEMPMSK
Definition: stm32l4a6xx.h:1184
USB_OTG_DeviceTypeDef::DINEP1MSK
__IO uint32_t DINEP1MSK
Definition: stm32l4a6xx.h:1188
USB_OTG_DeviceTypeDef::DVBUSPULSE
__IO uint32_t DVBUSPULSE
Definition: stm32l4a6xx.h:1182
USB_OTG_DeviceTypeDef::DEACHINT
__IO uint32_t DEACHINT
Definition: stm32l4a6xx.h:1185
USB_OTG_DeviceTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32l4a6xx.h:1174
USB_OTG_DeviceTypeDef::DIEPMSK
__IO uint32_t DIEPMSK
Definition: stm32l4a6xx.h:1175
USB_OTG_DeviceTypeDef::DCFG
__IO uint32_t DCFG
Definition: stm32l4a6xx.h:1171
USB_OTG_DeviceTypeDef::DOUTEP1MSK
__IO uint32_t DOUTEP1MSK
Definition: stm32l4a6xx.h:1190
USB_OTG_DeviceTypeDef::DEACHMSK
__IO uint32_t DEACHMSK
Definition: stm32l4a6xx.h:1186
USB_OTG_DeviceTypeDef::Reserved24
uint32_t Reserved24
Definition: stm32l4a6xx.h:1180
USB_OTG_DeviceTypeDef::DOEPMSK
__IO uint32_t DOEPMSK
Definition: stm32l4a6xx.h:1176
USB_OTG_DeviceTypeDef::DTHRCTL
__IO uint32_t DTHRCTL
Definition: stm32l4a6xx.h:1183
USB_OTG_GlobalTypeDef
USB_OTG_Core_register.
Definition: stm32l4a6xx.h:1136
USB_OTG_GlobalTypeDef::GDFIFOCFG
__IO uint32_t GDFIFOCFG
Definition: stm32l4a6xx.h:1159
USB_OTG_GlobalTypeDef::GRXSTSP
__IO uint32_t GRXSTSP
Definition: stm32l4a6xx.h:1145
USB_OTG_GlobalTypeDef::GOTGINT
__IO uint32_t GOTGINT
Definition: stm32l4a6xx.h:1138
USB_OTG_GlobalTypeDef::GINTSTS
__IO uint32_t GINTSTS
Definition: stm32l4a6xx.h:1142
USB_OTG_GlobalTypeDef::GUSBCFG
__IO uint32_t GUSBCFG
Definition: stm32l4a6xx.h:1140
USB_OTG_GlobalTypeDef::GAHBCFG
__IO uint32_t GAHBCFG
Definition: stm32l4a6xx.h:1139
USB_OTG_GlobalTypeDef::GINTMSK
__IO uint32_t GINTMSK
Definition: stm32l4a6xx.h:1143
USB_OTG_GlobalTypeDef::GOTGCTL
__IO uint32_t GOTGCTL
Definition: stm32l4a6xx.h:1137
USB_OTG_GlobalTypeDef::Reserved6
uint32_t Reserved6
Definition: stm32l4a6xx.h:1156
USB_OTG_GlobalTypeDef::GHWCFG3
__IO uint32_t GHWCFG3
Definition: stm32l4a6xx.h:1155
USB_OTG_GlobalTypeDef::GHWCFG2
__IO uint32_t GHWCFG2
Definition: stm32l4a6xx.h:1154
USB_OTG_GlobalTypeDef::CID
__IO uint32_t CID
Definition: stm32l4a6xx.h:1151
USB_OTG_GlobalTypeDef::GSNPSID
__IO uint32_t GSNPSID
Definition: stm32l4a6xx.h:1152
USB_OTG_GlobalTypeDef::GRSTCTL
__IO uint32_t GRSTCTL
Definition: stm32l4a6xx.h:1141
USB_OTG_GlobalTypeDef::GRXSTSR
__IO uint32_t GRXSTSR
Definition: stm32l4a6xx.h:1144
USB_OTG_GlobalTypeDef::GADPCTL
__IO uint32_t GADPCTL
Definition: stm32l4a6xx.h:1160
USB_OTG_GlobalTypeDef::HNPTXSTS
__IO uint32_t HNPTXSTS
Definition: stm32l4a6xx.h:1148
USB_OTG_GlobalTypeDef::GCCFG
__IO uint32_t GCCFG
Definition: stm32l4a6xx.h:1150
USB_OTG_GlobalTypeDef::DIEPTXF0_HNPTXFSIZ
__IO uint32_t DIEPTXF0_HNPTXFSIZ
Definition: stm32l4a6xx.h:1147
USB_OTG_GlobalTypeDef::HPTXFSIZ
__IO uint32_t HPTXFSIZ
Definition: stm32l4a6xx.h:1162
USB_OTG_GlobalTypeDef::GRXFSIZ
__IO uint32_t GRXFSIZ
Definition: stm32l4a6xx.h:1146
USB_OTG_GlobalTypeDef::GLPMCFG
__IO uint32_t GLPMCFG
Definition: stm32l4a6xx.h:1157
USB_OTG_GlobalTypeDef::GPWRDN
__IO uint32_t GPWRDN
Definition: stm32l4a6xx.h:1158
USB_OTG_GlobalTypeDef::GHWCFG1
__IO uint32_t GHWCFG1
Definition: stm32l4a6xx.h:1153
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32l4a6xx.h:1240
USB_OTG_HostChannelTypeDef::HCTSIZ
__IO uint32_t HCTSIZ
Definition: stm32l4a6xx.h:1245
USB_OTG_HostChannelTypeDef::HCSPLT
__IO uint32_t HCSPLT
Definition: stm32l4a6xx.h:1242
USB_OTG_HostChannelTypeDef::HCDMA
__IO uint32_t HCDMA
Definition: stm32l4a6xx.h:1246
USB_OTG_HostChannelTypeDef::HCINT
__IO uint32_t HCINT
Definition: stm32l4a6xx.h:1243
USB_OTG_HostChannelTypeDef::HCCHAR
__IO uint32_t HCCHAR
Definition: stm32l4a6xx.h:1241
USB_OTG_HostChannelTypeDef::HCINTMSK
__IO uint32_t HCINTMSK
Definition: stm32l4a6xx.h:1244
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32l4a6xx.h:1226
USB_OTG_HostTypeDef::Reserved40C
uint32_t Reserved40C
Definition: stm32l4a6xx.h:1230
USB_OTG_HostTypeDef::HFIR
__IO uint32_t HFIR
Definition: stm32l4a6xx.h:1228
USB_OTG_HostTypeDef::HAINTMSK
__IO uint32_t HAINTMSK
Definition: stm32l4a6xx.h:1233
USB_OTG_HostTypeDef::HCFG
__IO uint32_t HCFG
Definition: stm32l4a6xx.h:1227
USB_OTG_HostTypeDef::HFNUM
__IO uint32_t HFNUM
Definition: stm32l4a6xx.h:1229
USB_OTG_HostTypeDef::HPTXSTS
__IO uint32_t HPTXSTS
Definition: stm32l4a6xx.h:1231
USB_OTG_HostTypeDef::HAINT
__IO uint32_t HAINT
Definition: stm32l4a6xx.h:1232
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32l4a6xx.h:1197
USB_OTG_INEndpointTypeDef::DTXFSTS
__IO uint32_t DTXFSTS
Definition: stm32l4a6xx.h:1204
USB_OTG_INEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32l4a6xx.h:1201
USB_OTG_INEndpointTypeDef::Reserved18
uint32_t Reserved18
Definition: stm32l4a6xx.h:1205
USB_OTG_INEndpointTypeDef::DIEPCTL
__IO uint32_t DIEPCTL
Definition: stm32l4a6xx.h:1198
USB_OTG_INEndpointTypeDef::DIEPDMA
__IO uint32_t DIEPDMA
Definition: stm32l4a6xx.h:1203
USB_OTG_INEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition: stm32l4a6xx.h:1199
USB_OTG_INEndpointTypeDef::DIEPTSIZ
__IO uint32_t DIEPTSIZ
Definition: stm32l4a6xx.h:1202
USB_OTG_INEndpointTypeDef::DIEPINT
__IO uint32_t DIEPINT
Definition: stm32l4a6xx.h:1200
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32l4a6xx.h:1212
USB_OTG_OUTEndpointTypeDef::DOEPINT
__IO uint32_t DOEPINT
Definition: stm32l4a6xx.h:1215
USB_OTG_OUTEndpointTypeDef::DOEPDMA
__IO uint32_t DOEPDMA
Definition: stm32l4a6xx.h:1218
USB_OTG_OUTEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32l4a6xx.h:1216
USB_OTG_OUTEndpointTypeDef::DOEPTSIZ
__IO uint32_t DOEPTSIZ
Definition: stm32l4a6xx.h:1217
USB_OTG_OUTEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition: stm32l4a6xx.h:1214
USB_OTG_OUTEndpointTypeDef::DOEPCTL
__IO uint32_t DOEPCTL
Definition: stm32l4a6xx.h:1213
VREFBUF_TypeDef
VREFBUF.
Definition: stm32l4a6xx.h:1048
VREFBUF_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32l4a6xx.h:1050
VREFBUF_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32l4a6xx.h:1049
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32l4a6xx.h:1058
WWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32l4a6xx.h:1061
WWDG_TypeDef::CR
__IO uint32_t CR
Definition: stm32l4a6xx.h:1059
WWDG_TypeDef::CFR
__IO uint32_t CFR
Definition: stm32l4a6xx.h:1060
system_stm32l4xx.h
CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.